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Showing papers on "Division (mathematics) published in 1990"


Journal ArticleDOI
TL;DR: The feasibility of an optical-frequency-to-radio-frequency division method that is based on visible or near-infrared laser oscillators only is explored and the arithmetic average of two visible frequencies is generated.
Abstract: We explore and demonstrate the feasibility of an optical-frequency-to-radio-frequency division method that is based on visible or near-infrared laser oscillators only. Comparing harmonic and sum frequencies, we generate the arithmetic average of two visible frequencies. Cascading n stages provides difference-frequency division by 2(n). For a demonstration we have phase locked the second harmonic and the sum frequency of two independent diode lasers.

185 citations




Journal ArticleDOI
TL;DR: A radix-4 division algorithm with operands scaling is proposed that uses a recurrence with redundant addition and combines simple scaling with a quotient-selection function that depends only on the estimate of the partial remainder and is independent of the divisor.
Abstract: A radix-4 division algorithm with operands scaling is proposed. The algorithm uses a recurrence with redundant addition (carry-save or signed-digit) and combines simple scaling with a quotient-selection function that depends only on the estimate of the partial remainder and is independent of the divisor. The scheme results in a significant speedup with respect to both the radix-2 and radix-4 without scaling. >

78 citations


Journal ArticleDOI
01 Oct 1990
TL;DR: It is shown how common arithmetic functions such as multiplication and sorting can be efficiently computed in a shallow neural network and can be extended to more complicated functions, such as multiple products, division, rational functions, and approximation of analytic functions.
Abstract: A neuron is modeled as a linear threshold gate, and the network architecture considered is the layered feedforward network. It is shown how common arithmetic functions such as multiplication and sorting can be efficiently computed in a shallow neural network. Some known results are improved by showing that the product of two n-bit numbers and sorting of n n-bit numbers can be computed by a polynomial-size neural network using only four and five unit delays, respectively. Moreover, the weights of each threshold element in the neural networks require O(log n)-bit (instead of n-bit) accuracy. These results can be extended to more complicated functions such as multiple products, division, rational functions, and approximation of analytic functions. >

68 citations


Patent
Donald Lee Freerksen1
13 Mar 1990
TL;DR: Combinatorial bias-adjust logic (CFA) as mentioned in this paper removes bias from one exponent before the two operand exponents are added together in adder for a multiply operation, and inserts a bias into another exponent before subtraction by theadder for a divide operation.
Abstract: A floating-point arithmetic unit includes an exponent unit for biased exponents. Combinatorial bias-adjust logic (324) removes the bias from one operand exponent before the two operand exponents are added together in adder (322) for a multiply operation, and inserts a bias into one exponent before the exponents are subtracted by the adder for a divide operation.

61 citations


Journal ArticleDOI
TL;DR: The authors found that children of this age already hold misconceptions such as “multiplication always makes bigger.” However they also hold conceptions that are prerequisite to understanding the area model of multiplication and the measurement model of division.
Abstract: This study was designed to gain information about the understandings children in Israel and the United States have about multiplication and division of whole numbers that may be useful in building accurate understandings of these operations with decimals and the extent to which they hold conceptions about these operations that may interfere with their work with decimals. Data from interviews of the fourth and fifth graders indicate that students of this age already hold misconceptions such as “multiplication always makes bigger.” However they also hold conceptions that are prerequisite to understanding the area model of multiplication and the measurement model of division. These early conceptions might be used to build understanding of multiplication and division by decimals. Implications for the content and sequencing of instructional activities are presented.

40 citations


Patent
06 Dec 1990
Abstract: A mutual division circuit includes a single mutual division unit or a plurality of cascaded mutual division units for dividing a polynomial including a first input polynomial R i-1 (X) as a factor by a second input polynomial Q i-1 (X), thereby to determine a quotient and a remainder R i (X), determining an overall quotient λ i (X) from the quotient and a third input polynomial λ i-1 (X), and producing the remainder R i (X), the first input polynomial R i-1 (X) or the second input polynomial Q i-1 (X), and the overall quotient λ i (X) as a first output polynomial R i (X), a second output polynomial Q i (X), and a third output polynomial λ i (X), respectively. The mutual division circuit also has a data selector (42) for receiving, at an input port thereof, respective initial polynomials of the first, second, and third input polynomials, and supplying output data to the single mutual division unit or a first one of the cascaded mutual division units, and a feedback or data bus (45) for supplying output data from the single mutual division unit or a last one of the cascaded mutual division units to another input port of the data selector (42). The single mutual division unit or the cascaded mutual division units are used a plurality of times for carrying out arithmetic operations therein.

31 citations



Patent
06 Dec 1990
TL;DR: In this article, a mutual division circuit includes a single mutual division unit or a plurality of cascaded mutual division units for dividing a polynomial including a first input Polynomial Ri-1(X) as a factor by a second input Qi-1-(X), thereby to determine a quotient and a remainder Ri(X), determining an overall quotient λi(X).
Abstract: A mutual division circuit includes a single mutual division unit or a plurality of cascaded mutual division units for dividing a polynomial including a first input polynomial Ri-1(X) as a factor by a second input polynomial Qi-1-(X), thereby to determine a quotient and a remainder Ri(X), determining an overall quotient λi(X) from the quotient and a third input polynomial λi-1(X), and producing the remainder R(X), the first input polynomial Ri-1(X) or the second input polynomial Qi-1(X), and the overall quotient x(X) as a first output polynomial Ri(X), a second output polynomial Qi(X), and a third output polynomial λi(X), respectively. The mutual division circuit also has a data selector (42) for receiving, at an input port thereof, respective initial polynomials of the first, second, and third input polynomials, and supplying output data to the single mutual division unit or a first one of the cascaded mutual division units, and a feedback or data bus (45) for supplying output data from the single mutual division unit or a last one of the the cascaded mutual division units to another input port of the data selector (42). The single mutual division unit or the cascaded mutual division units are used a plurality of times for carrying out arithmetic operations therein.

28 citations



Journal ArticleDOI
TL;DR: An algorithm for evaluating the square root of integers and real numbers is developed and shows considerable improvement in speed compared to two methods being widely used.
Abstract: An algorithm for evaluating the square root of integers and real numbers is developed. The procedure consists of two parts: one to obtain a close estimate of the square root and the other to modify the initial value, iteratively, until a precise root is evaluated. The major effort in this development has been concentrated on two objectives: high speed and no division operation other than division by 2. The first objective is achieved through a simple two-step procedure for getting the first estimate, and then modifying it by employing a fast converging iteration technique. The second objective is also fulfilled through applying bit-shift operation rather than division operation. The algorithm is simulated for both integer and real numbers, and the results are compared to two methods being widely used. The results (tabulated) show considerable improvement in speed compared to these other two methods. >

Patent
10 Apr 1990
TL;DR: In this paper, a sign bit is concatenated to a fixed point approximation of the logarithm of the absolute value of the real number being represented, and the output of the first ROM is added to the product of the second ROM and the low part of the shifted z value.
Abstract: An apparatus is provided for logarithmic subtraction that is suitable for general purpose computing using the sign logarithm number system. In the sign logarithm number system, a sign bit is concatenated to a fixed point approximation of the logarithm of the absolute value of the real number being represented. Multiplication and division are easy and fast because the only steps required are to add or subtract the logarithms and exclusive OR the sign bits. In the prior art, logarithmic arithmetic has been restricted to limited precision applications (8-16 bits), such as digital filtering, because of the problem of accurate, high speed subtraction. The present invention provides a new circuit for subtracting two numbers represented in logarithmic form which makes design of arithmetic units for larger word sizes (32 bits) practical. The subtraction circuit approximates log b |1-b z |, where z is the difference of the logarithms being subtracted. The value of z is shifted, and the high part of z is used as input to two ROMs. The output of the first ROM is added to the product of the second ROM and the low part of the shifted z value. In the case of z being close to zero, the low part of z is used as input to a third ROM, which provides a more accurate approximation of log b |1-b z |.

Journal ArticleDOI
TL;DR: It is shown that, if a division is described by AQ=C, then the bit variables involved in a set of equations, each of which determines a leading bit of C, gives an approximation for Q that an be used in a SRT division scheme.
Abstract: It is shown that, if a division is described by AQ=C, where A is the divisor, Q is the quotient, and C is the dividend, then the bit variables involved in a set of equations, each of which determines a leading bit of C, gives an approximation for Q that an be used in a SRT division scheme. The results of an exhaustive statistical simulation, using all possible combinations of two pairs of integers 12 b in length, in normalized form, representing A and C are presented to validate the method. >



Patent
Toshio Suzuki1, Atsuo Itoh1
26 Jan 1990
TL;DR: A cell switching system incorporates time division lines, serial-to-parallel converters, address filters, re-arranging circuits, selectors and parallel to serial con-verters as discussed by the authors.
Abstract: A cell switching system incorporates time division lines, serial-to-parallel converters, address filters, re-arranging circuits, selectors and parallel-to-serial con-verters. The novel system avoids prior art problems such as complicated processing requirement to prevent conflicting cells from being inverted. A number of different cells arriving at the same time for the same destination can be handled.

Journal ArticleDOI
TL;DR: Computer simulations showed that a heart shape developed when the ratio between the rates of anticlinal and periclinal divisions in segments was below a certain threshold, providing a quantitative characterization of the tendency of the cell division pattern to develop a heartshape.
Abstract: We have investigated the relationship between cell division and shape in mathematical models of fern gametophyte development. In particular, we attempted to infer what properties of cell division patterns are responsible for the development of heart-shaped thalli. We focused on those types of gametophytes that develop from an initial cell, splitting off segments alternately to the left and to the right. Computer simulations showed that a heart shape developed when the ratio between the rates of anticlinal and periclinal divisions in segments (the division ratio) was below a certain threshold. In the computer simulations we used map L-systems for the generation of cell division patterns and a center-of-gravity algorithm for the computation of cell shapes. The division ratio provided a quantitative characterization of the tendency of the cell division pattern to develop a heart shape. Together with map DOL-systems it can be applied to real gametophytes to investigate their morphogenesis.


Journal ArticleDOI
TL;DR: In this article, it was shown that the Hopf fibration of S {2n-1} by great (n 1)-spheres determined by a division algebra is differentiable.
Abstract: The authors answer the natural question: When is the fibration of S {2n-1} by great (n-1)-spheres determined by a division algebra differentiable? They show that this happens only for the classical Hopf fibrations, which are determined by the classical division algebras R, C, H and O.

Patent
26 Jan 1990
TL;DR: In this paper, it was shown that when at least one key is in an on-state or operated, the division point is set in the position of the key which is being operated, instead of predetermined key positions.
Abstract: An electronic keyboard musical instrument has a division point setting switch for setting division point on a keyboard. In the case that the division point setting switch is actuated when all keys are in an off-state or not operated, a division point is set in a predetermined key position. In the case that the division point setting switch is actuated when at least one key is in an on-state or operated, the division point is set in the position of the key which is being operated, thereby setting the division point in the key positions arbitrarily, instead of predetermined key positions.

Patent
07 Feb 1990
TL;DR: In this paper, a division judge circuit was proposed to perform high speed recording corresponding to pixel density by detecting heating elements to be driven on the basis of the distribution of the pixel density of one row to be recorded to mutually drive the heating elements at the same time or in a time differential manner.
Abstract: PURPOSE:To perform the high speed recording corresponding to pixel density by detecting heating elements to be driven on the basis of the distribution of the pixel density of one row to be recorded to mutually drive the heating elements at the same time or in a time differential manner and performing the transfer driving of recording paper by setting the number of times of time differential driving to a cycle. CONSTITUTION:A division judge circuit 15 is driven under control on the basis of the clock signal CK from a timing clock generating circuit 10 and the start signal from a CPU 24 and determines whether the respective groups G1-G4 constituting a thermal head 14 are driven by the supply of a current at the same time or in a time differential manner, on the basis of the distribution of the black pixel data in one scanning line to form division judge data Ln. A sub-scanning pixel density detection circuit 21 detects the pixel density of a manuscript in a sub-scanning direction. Since the obtained division judge data Ln shows the combination data of the groups G1-G4 of heating elements, the heating elements are subjected to division driving and the interval for feeding the manuscript or recording paper in the sub-scanning direction corresponding to the number of divisions, that is, the interval for driving the first and second pulse motors 16, 17 is determined.

Patent
29 Mar 1990
TL;DR: In this paper, the authors proposed to reduce the cost of the whole system by providing a driver IC with the transfer function of gate pulses for division drive, dividing a block selective signal into two and decreasing the core wires of a thermal head.
Abstract: PURPOSE:To reduce the cost of the whole system by providing a driver IC with the transfer function of gate pulses for division drive, dividing a block selective signal into two and decreasing the core wires of the connector of a thermal head. CONSTITUTION:A DRIVE and a CLK 2 represent an input signal to a shift register 1 and a block signal for transfer. The shift register 1 represents a serial input and parallel-out type shift register, and the DRIVE input signal is shifted successively by the clock pulse CLK2 for transfer and output to BLK1- BLKN as outputs. The BLK output of a number to be driven from the BLK1-N is connected to a DST input, thus allowing division drive. Operation in which energy applied to a heating resistor at the time of drive is controlled is conducted easily by varying the pulse period T of the CLK2. Accordingly, signal conductors for division drive are divided into two of DRIVE and CLK2, thus reducing the cost of a cable, cable assembly, etc.

Book ChapterDOI
N. K. Ailawadi1
01 Jan 1990
TL;DR: The routing aspects of photonic switching are presented, and in particular, the lithium niobate technology of the directional coupler is presented, as well as several space division switch architectures and their characteristics.
Abstract: This paper reviews various architectures for photonic switching that have been proposed in the literature. The paper presents only the routing aspects of photonic switching, and in particular, the lithium niobate technology of the directional coupler. The paper: 1. provides the motivation for photonic switching, describes the various photonic switching elements, and discusses different control mechanisms required for photonic switching; 2. explains the principles of an electro-optic switch; 3. enumerates the architectural considerations involved in a photonic switch design; 4. discusses several space division switch architectures and compares their characteristics; 5. describes time division switching and different basic time division switching architectures.



Patent
29 Aug 1990
TL;DR: In this paper, a method and apparatus are disclosed wherein a web of material (116) such as paper, being manufactured or processed is monitored to generate a profile signal which is separated into a number of subprofile signals corresponding to the processing stations to be controlled.
Abstract: A method and apparatus are disclosed wherein a web of material (116), such as paper, being manufactured or processed is monitored to generate a profile signal which is separated into a number of subprofile signals corresponding to a number of processing stations to be controlled. The contributions of the individual processing stations, such as headboxes (102, 104) for the manufacture of paper, to various cross direction (CD) profile characteristics of the web of material has been recognized as being spatial frequency dependent. Accordingly, the profile signal generated by monitoring the web of material is divided (142) into two or more subprofile signals corresponding to the processing stations based on the CD spatial frequencies characteristic of the operations performed by the stations. The subprofile signals are then applied to the processing stations (102, 104) to control them to maintain one or more desired CD profile characteristics. The division of the profile signal into subprofile signals can be performed by filtering, Fourier transforms or otherwise. Preferably, profile signal division is performed by a digital processor.

Journal ArticleDOI
TL;DR: The board of the Division of the Plasma Physics Division meet on 24 June 1990, the Sunday before the Annual Divisional Conference in Amden as discussed by the authors, and the most important business rela- ted to future conferences.
Abstract: The Board of the Plasma Physics Division meet on 24 June 1990, the Sunday before the Annual Divisional Conference in Am­ sterdam. The most important business rela­ ted to future conferences. It was decided to combine our 1992 conference with the International Conference on Plasma Physics (ICPP) which will take place in Innsbruck on 29 June-5 July 1992. It was also decided to organize in the week after ICPP a satellite meeting on radiofrequency heating and cur­ rent drive in Brussels. The 1993 Division conference will be held in Portugal. At the end of this year we shall have to elect the Division Board for 1991-1993. According to the Division's Statutes, no more than six members of the present Board may be re-elected. I therefore invite members of the Division to discuss with their colleagues possible candidates and to provide me with their names. The candi­ dates must be members of the Plasma Phy­ sics Division. Each nomination should be accompanied by a statement of consent by the candidate, a one line description of his or her activity, and the names of five mem­ bers of the Plasma Physics Division sup­ porting the candidature. The members of the present Board who are eligible for re-election are: G. M. McCracken, Culham (UK) J.T. Mendonça, Lisbon (P) D.D. Ryutov, Novosibirsk (USSR) H. Schlüter, Bochum (FRG) S. Segre (Vice-Chairman), Rome (I) F. Sluijter (Vice-Chairman), Eindhoven (NL) J. Tachon, Cadarache (F) R.R. Weynants, Brussels (B) To ensure a smooth transition into the new term, the Board has elected F. Sluijter as its Chairman from 1 October 1990. Please send nominations before 30 Sep­ tember 1990 to: Miss Edith Grüter, CRPP/EPFL, Avenue des Bains 21, CH-1007 Lausanne.

Patent
Ai Takaharu1
24 Oct 1990
TL;DR: In this article, a controller of an information recording/reproducing apparatus divides information to be recorded into two or more portions so that the first division portion is successively recorded over a first group of a plurality of blocks formed circumferentially on a disc-like recording medium and then reproduced for verification.
Abstract: An information recording/reproducing apparatus having a function to verify recorded information. A controller of the apparatus divides information to be recorded into two or more portions so that the first division portion is successively recorded over a first group of a plurality of blocks formed circumferentially on a disc-like recording medium and then reproduced for verification, before the second division portion is successively recorded over a second group of blocks which are consecutive to the first group of blocks and then reproduced for the verification, the recording and reproduction being continuously effected up to the last division portion. When verifying the first division portion through the penultimate division portion, only the final group of one or more blocks of the blocks of the just recorded division portion are not verified immediately but, after the recording for a subsequent division portion, verified together with the blocks of the subsequent division portion other than final group of one or more blocks of the subsequently recorded division portion. All blocks of the last division portion reproduced for verification are verified together with previously recorded and non-verified blocks from other division portions.

Book ChapterDOI
M. Nishio1, S. Suzuki1
01 Jan 1990
TL;DR: In this paper, a parallel λ-switch, which offers both space and wavelength switch functions, can reduce the number of wavelength filters and converters, and has a growable structure and non-blocking one-to-many connections capability.
Abstract: A parallel λ-switch, which offers both space and wavelength switch functions, can reduce number of wavelength filters and converters. It has a growable structure and non-blocking one-to-many connections capability.