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Showing papers on "Division (mathematics) published in 1992"


Brian Greer1
01 Jan 1992

284 citations


Patent
18 Feb 1992
TL;DR: An electro-optical device comprising a display drive system with display timing related to the unit time t for writing in a picture element and to the time F for writing-in one picture is disclosed in this paper.
Abstract: An electro-optical device comprising a display drive system with the display timing related to the unit time t for writing-in a picture element and to the time F for writing-in one picture is disclosed. In the device, a gradated display corresponding to the ratio of the division can be obtained by time-sharing the signal during a write-in of time t without changing the time F.

111 citations


Journal ArticleDOI
01 May 1992
TL;DR: In this paper, it was shown that, when field elements are represented by polynomials, division over finite fields can be performed by solving a system of m linear equations over GF(q).
Abstract: Division and bit-serial multiplication in finite fields are considered. Using co-ordinates of the supporting elements it is shown that, when field elements are represented by polynomials, division over GF(qm) can be performed by solving a system of m linear equations over GF(q). For a canonical basis representation, a relationship between the division and the discrete-time Wiener-Hopf equation of degree m over GF(q) is derived. This relationship leads to a bit-serial multiplication scheme that can be easily realised for all irreducible polynomials.

79 citations


Journal ArticleDOI
TL;DR: A class of iterative integer division algorithms is presented based on look-up table and Taylor-series approximations to the reciprocal, which naturally produce an exact remainder, which is very useful for implementing precise rounding specifications.
Abstract: A class of iterative integer division algorithms is presented based on look-up table and Taylor-series approximations to the reciprocal. The algorithm iterates by using the reciprocal to find an approximate quotient and then subtracting the quotient multiplied by the divisor from the dividend to find a remaining dividend. Fast implementations can produce an average of either 14 or 27 b per iteration, depending on whether the basic or advanced version of this method is implemented. Detailed analyses are presented to support the claimed accuracy per iteration. Speed estimates using state-of-the-art ECL components show that this method is faster than the Newton-Raphson technique and can produce 53-b quotients of 53-b numbers in about 25 ns using the basic method and 21 ns using the advanced method. In addition, these methods naturally produce an exact remainder, which is very useful for implementing precise rounding specifications. >

74 citations


Journal ArticleDOI
TL;DR: In this article, a structure theory for left divsion absolute valued algebras is developed, which shows that the norm of such an algebra comes from an inner product.
Abstract: We develop a structure theory for left divsion absolute valued algebras which shows, among other things, that the norm of such an algebra comes from an inner product. Moreover, we prove the existence of left division complete absolute valued algebras with left unit of arbitrary infinite hilbertian division and with the additional property that they have nonzero proper closed left ideals. Our construction involves results from the representation theory of the so called "Canonical Anticommutation Relations" in Quantum Mechanics. We also show that homomorphisms from complete normed algebras into arbitrary absolute valued algebras are contractive, hence automatically continuous.

52 citations


Journal ArticleDOI
TL;DR: Three ways to modify this conversion process so that the result is rounded are described, which can be done on-the-fly as the digits are produced, without the use of a carry-propagate adder.
Abstract: In implementations of operations based on digit-recurrence algorithms such as division, left-to-right multiplication and square root, the result is obtained in digit-serial form, from most significant digit to least significant. To reduce the complexity of the result-digit selection and allow the use of redundant addition, the result-digit has values from a signed-digit set. As a consequence, the result has to be converted to conventional representation, which can be done on-the-fly as the digits are produced, without the use of a carry-propagate adder. The authors describe three ways to modify this conversion process so that the result is rounded. The resulting operation is fast because no carry-propagate addition is needed. The schemes described apply also to online arithmetic operations. >

50 citations


Patent
Paul C. Rossbach1
01 Jun 1992
TL;DR: In this paper, a method and apparatus for performing integer and floating-point divide operations using a single modified SRT divider in a data processor is presented, where the floating point and integer division are performed using SRT division on normalized positive mantissas (dividend and divisor).
Abstract: A method and apparatus for performing integer and floating-point divide operations using a single modified SRT divider in a data processor. The floating-point and integer division is performed using SRT division on normalized positive mantissas (dividend and divisor). Integer division shares portions of the floating point circuitry, however, the sequence of operations is modified during the performance of an integer divide operation. The SRT divider performs a sequence of operations before and after an iteration loop to re-configure an integer divisor and dividend into a data path representation which the SRT algorithm requires for floating-point mantissas. During the iteration loop, quotient bits are selected and used to generate intermediate partial remainders. The quotient bits are also input to quotient registers which accumulate the final quotient mantissa. A full mantissa adder is used to generate a final remainder.

42 citations


Journal ArticleDOI
TL;DR: For example, this article found that 75% of the children were able to solve the problems using a wide variety of strategies even though they had not received formal instruction in multiplication or division for most of the 2 year period.
Abstract: Children’s solution strategies to a variety of multiplication and division word problems were analysed at four interview stages in a 2-year longitudinal study. The study followed 70 children from Year 2 into Year 3, from the time where they had received no formal instruction in multiplication and division to the stage where they were being taught basic multiplication facts. Ten problem structures, five for multiplication and five for division, were classified on the basis of differences in semantic structure. The relationship between problem condition (i.e. small or large number combinations and use of physical objects or pictures), on performance and strategy use was also examined. The results indicated that 75% of the children were able to solve the problems using a wide variety of strategies even though they had not received formal instruction in multiplication or division for most of the 2 year period. Performance level generally increased for each interview stage, but few differences were found between multiplication and division problems except for Cartesian and Factor problems. Solution strategies were classified for both multiplication and division problems at three levels: A wide range of counting strategies were classified as counting-all, skip counting and double counting. Analysis of intuitive models revealed preference for a repeated addition model for multiplication, and a ‘building-up’ model for division.

41 citations


Journal ArticleDOI
TL;DR: In this article, Cayley homomorphisms for infinite-dimensional complete normed real algebras with left unity have been studied and shown to have left unity properties, which is closely related with composition algebra and normalized orthogonal multiplication.
Abstract: In this note we introduce the concept of Cayley homomorphism which is closely related with those of composition algebra and normalized orthogonal multiplication The key result shows the existence of certain types of Cayley homomorphisms for infinite dimension As an application we prove the existence of left division infinite-dimensional complete normed real algebras with left unity

40 citations


Journal ArticleDOI
15 May 1992
TL;DR: In this article, the authors propose newshifted remainder conditioning, and sign multiplexing techniques in combination with novel circuit architecture approaches to obtain efficient divider and square-root architectures.
Abstract: This paper addresses design of high speed architectures for fixed-point, two's-complement, bit-parallel division, square-root, and multiplication operations. These architectures make use of hybrid number representations (i.e. the input and output numbers are represented using two's complement representation, and the internal numbers are represented using radix-2 redundant representation). We propose newshifted remainder conditioning, andsign multiplexing techniques in combination with novel circuit architecture approaches to obtain efficient divider and square-root architectures. Our divider exploits full dynamic range of operands and eliminates the need for on-line or off-line conversion of the result to binary (this is because our nonrestoring division and square-root operators output binary quotient). Furthermore, since the binary input set is a subset of the redundant digit set, no binary-to-redundant number conversion is necessary at the input of the divider and square-root operators. We also present a fast, new conversion scheme for converting radix-2 redundant numbers to two's complement binary numbers, and use this to design a bit-parallel multiplier. This multiplier architecture requires fewer pipelining latches than conventional two's complement multipliers, and reduces the latency of the multiplication operation from (2W---1) to aboutW (whereW is the word-length), when pipelined at the bit-level.

38 citations


Patent
18 Feb 1992
TL;DR: In this article, the authors describe a system for cutting sheets of wood in which a set grid of cuts is used to manage operation of the cutters and the positioning and taking devices for performing the cuts.
Abstract: A station (10) for cutting sheets of wood (13), and in particular for cutting packages of sheets, includes a first device (12) for positioning a package of sheets under a first cutter (15) so as to separate parts of the package sequentially. A further device (14) takes the cut part and sends it to a second cutter (17) for sequentially cutting the part along a second direction so as to obtain another division in subparts sequentially and selectively conveyed outside the station. Electronic controls are used to manage operation of the cutters and the positioning and taking devices for performing the cuts in accordance with a previously set grid of cuts.

Patent
10 Dec 1992
TL;DR: The Euclidean mutual division (EMD) as discussed by the authors is a circuit that has (2t+1) calculation units and ( 2t+3) registers for error correction where t is the number of symbols that can be error-corrected.
Abstract: A Euclidean mutual division circuit that has (2t+1) calculation units and (2t+3) registers for error correction where t is the number of symbols that can be error-corrected. The division unit and each calculation unit conduct Euclidean mutual divisions of either a normal-connection, a cross-connection, or a shift-connection division as directed by a control unit. The final calculation unit outputs a value to a division unit which divides it by another value, then the result of the division is returned to each of the calculation units. Registers that store the inputs for the Euclidean mutual division method include A-side and B-side registers. A-side registers store the coefficients of polynomials Qi(X) and λi(X), and B-side registers store those of Ri(X) and μi(X). The Euclidean mutual division circuit has a reduced circuit scale for high-speed operation and for increased throughput.


Journal ArticleDOI
TL;DR: A radix 4 division architecture is presented which partially overlaps the updating of the remainder with the digit selection procedure, and shows that the proposed architectures offer an efficient alternative.
Abstract: A radix 4 division architecture is presented which partially overlaps the updating of the remainder with the digit selection procedure. It is obtained by separating the radix 4 digit selection process into two concurrent substeps. The proposed unit requires a simple selection table and involves a small extra expense for the additional hardware compared to the usual radix 4 division units. Four possible implementations are derived from the general model, with different types of substeps. The high level evaluation shows that the proposed architectures offer an efficient alternative. >


Patent
09 Oct 1992
TL;DR: In this paper, a hardware floating point remainder generator is presented for performing a remainder function by receiving two floating point numbers (X and Y), by generating the remainder of X/Y according to a series of radix 4 SRT non-restoring division cycles and at most one single bit restoring division step, and by delivering the remainder.
Abstract: A hardware floating point remainder generator is disclosed for performing a remainder (REM) function by receiving two floating point numbers (X and Y), by generating the remainder of X/Y according to a series of radix 4 SRT non-restoring division cycles and at most one single bit restoring division step, and by delivering the remainder.

Journal ArticleDOI
TL;DR: The evaluation-interpolation technique of A. Toom is applied to approximate polynomial division with a remainder, which leads to the same computation and the same record asymptotic parallel complexity estimate as those of the more advanced methods.

Patent
Ron Zinger1
31 Aug 1992
TL;DR: In this article, a single, double and extended precision shifter circuit for a hardware floating point divide circuit is described, which is used to steer the next negative and positive quotient values generated by the quotient prediction circuit into the proper place within respective negative/positive quotient registers.
Abstract: A single, double and extended precision shifter circuit for a hardware floating point divide circuit is disclosed. The divide circuit implements the divide function by receiving two floating point numbers (X and Y) from a main processor, generating the quotient of X/Y using radix 4 SRT nonrestoring division steps, and then delivering the quotient to the main processor. The divide circuit is comprised of a control circuit, a quotient prediction circuit, a partial remainder generator circuit and a quotient generator circuit. The precision shifter circuit operates during the nonrestoring division steps to steer the next negative and positive quotient values generated by the quotient prediction circuit into the proper place within respective negative and positive quotient registers of the quotient generation circuit. The steering is performed according to the precision specified for the divide operation.

Patent
Koichi Kuroiwa1
12 Mar 1992
TL;DR: In this paper, a floating-point division circuit for non-recovery type division on floating-points is presented, including a circuit portion for pre-division processing and pattern determination on a dividend and a divisor, an exponent operation portion, a mantissa division portion, and a quotient generating portion.
Abstract: A floating-point division circuit for performing division on floating-point data using a non-recovery type division method is disclosed. The floating-point division circuit includes a circuit portion for conducting a pre-division processing and pattern determination on a dividend and a divisor, an exponent operation portion, a mantissa division portion, and a quotient generating portion, further including either or both of an exception/non-operation detecting portion and a control portion. The exception/non-operation detecting portion generates a stop signal when detecting a non-operation pattern so as to stop a repetition of operations in the mantissa division portion. The control portion generates either a non-executional signal or a control signal so as to stop a latch operation during a period when no instruction for division is executed.

Patent
12 Mar 1992
TL;DR: In this paper, a power divider formed by the interconnection of an input resistive network and a transmission line network for dividing a signal received on an input port into N output ports is described.
Abstract: A power divider formed by the interconnection of an input resistive network and a transmission line network for dividing a signal received on an input port into N output ports. Four embodiments are described. Three are two-way power dividers and one is a three-way power divider. A 2-way equal division power divider comprises an outer conductor 51 which has a generally rectangular cross section and is filled with a lower dielectric sheet, a center dielectric sheet and an upper dielectric sheet. The dielectric sheets are made of low loss material. Inner conductors are photo-etched from a conducting material that has been deposited or laminated to both surfaces of the center dielectric sheet. Two conductors are spaced a maximum distance from each other at their outputs and are in close proximity to each other at their inputs. Two resistors are connected respectively from the conductor inputs to a power divider input. Another form of two-way equal division power divider, a two-way unequal division power divider, and a three-way equal division power divider are also described.


Patent
Joseph S. Schibinger1
04 Nov 1992
TL;DR: In this paper, a Carry-Save Adder (CSA) is used to verify the result of a division operation. But the use of a carry-save adder is not suitable for full adders, as it is faster and less costly to implement than a full adder.
Abstract: Method and apparatus for verifying the result of an arithmetic operation. The invention provides a time and cost efficient method of performing error detection on the result of an arithmetic operation; especially for a division operation. It does so through the novel use of a Carry-Save Adder (CSA). A CSA is known in the art to be faster and less costly to implement than the use of a full adder.

Journal ArticleDOI
TL;DR: Two algorithms are presented for carrying out division over GF(2 m) and it is shown that the resulting divider is hardware efficient and therefore suitable for VLSI implementation.
Abstract: Two algorithms are presented for carrying out division over GF(2 m ). Although ostensibly different in approach, both algorithms can be implemented by the same hardware. It is further shown that the resulting divider is hardware efficient and therefore suitable for VLSI implementation

Proceedings ArticleDOI
01 Jul 1992
TL;DR: By introducing two Boolean properties into angebraic division operation, a subset of Boolean division can be performed with approximately the same complexity as the algebraic division implemented in the misII environment.
Abstract: By introducing two Boolean properties into an algebraic division operation, a subset of Boolean division can be performed with approximately the same complexity as the algebraic division implemented in the misII environment. The extended algebraic division algorithm is called coalgebraic division. The experimental results show that the execution time of coalgebraic division is very close to that of algebraic division. With a simple restriction during division, coalgebraic division can also preserve the network testability as well as the test patterns. >

Patent
29 Jul 1992
TL;DR: In this paper, the authors present an apparatus for processing harmonically related plural quadrature amplitude modulated carriers (QAMC) at a frequency equal to four times the symbol rate of the highest frequency carrier.
Abstract: The present invention includes apparatus for processing harmonically related plural quadrature amplitude modulated carriers. Sampling apparatus converts the plural modulated carriers signal to sampled data format. The signal is sampled at a frequency equal to four times the symbol rate of the highest frequency carrier such that alternate samples correspond to in-phase and quadrature-phase components of the signal. The sampled data signals are resampled to separate respective in-phase and quadrature-phase components of the respective signals. The in-phase samples of the respective signals are time division multiplexed, and the quadrature-phase samples are time division multiplexed. The time division multiplexed in-phase samples and quadrature-phase samples are coupled to a phase correction apparatus arranged to operate in a time division multiplexed manner.

Journal ArticleDOI
TL;DR: In this paper, a twin-section selfpulsating laser diode was used for optical synchronisation with frequency division and achieved a ratio of 1:2 and 1:3.
Abstract: All optical synchronisation with frequency division is demonstrated for the first time using a twin section selfpulsating laser diode. Frequency division ratios of 1:2 and 1:3 are achieved. The range of frequencies over which synchronisation is maintained is also investigated and is found to decrease with increasing division ratio.

Patent
29 Jul 1992
TL;DR: In this paper, a sampling apparatus is arranged to sample the signals at a frequency equal to four times the symbol rate of the highest frequency carrier such that alternate samples correspond to in-phase and quadrature-phase components of the signal.
Abstract: Apparatus for processing harmonically related plural quadrature amplitude modulated carriers includes sampling apparatus for converting the plural modulated carriers to sampled data format. The sampling apparatus is arranged to sample the signals at a frequency equal to four times the symbol rate of the highest frequency carrier such that alternate samples correspond to in-phase and quadrature-phase components of the signal. The sampled data signals are resampled to separate respective in-phase and quadrature-phase components of the respective signals. The in-phase samples of the respective signals are time division multiplexed and coupled to a Nyquist or symbol shaping filter arranged to operate in a time division multiplexed manner.

Journal ArticleDOI
TL;DR: It is proved that polynomial time on a parallel random access machine (PRAM) with unit-cost multiplication and division or on a PRAM with unit -cost shifts is equivalent to polynometric space on a Turing machine (PSPACE).


Patent
Eiki Ito1
19 Mar 1992
TL;DR: In this paper, a preprocessor of a division device employing a high radix division system includes a first zero counter, a first shifter, a latch, and a second shifter.
Abstract: A preprocessor of a division device employing a high radix division system includes a first zero counter, a first shifter, a second counter, a latch, and a second shifter. From among continued "0" bits at the heads of a divisor and a dividend, the number of units of continued "0" bits are counted by the first zero counter using "n" bits as a unit. The divisor and the dividend are shifted by "the unit number" × "n bits" by the first shifter using "n" bits as a unit. Concurrently, the divisor shifted by the first shifter is counted for the remaining number of head expression " 0" bits by the second zero counter, and the divisor is normalized by the second shifter for obtaining the head bit "1". The dividend is shifted by the second shifter by the number of the head expression "0" bits of the divisor of the second zero counter stored by a latch, namely, by the shift number of the divisor. Thus, the difference between the shift numbers of the divisor and the dividend is always equal to an integer multiple of "n". The digit number of a quotient is also equal to an integer multiple of "n", the division can terminate at a predetermined digit, and a required remainder can be obtained simultaneously with the quotient.