Showing papers on "Division (mathematics) published in 1994"

Division and Square Root: Digit-Recurrence Algorithms and Implementations

Abstract: 1.General Comments. 2. Division by Digit Recurrence. 3. Theory of Digit-Recurrence Division. 4. Division with Scaling and Prediction. 5. Higher Radix Division. 6. On-the-Fly Conversion and Rounding. 7. Square Root by Digit Recurrence. 8. Implementations of Square Root. Appendices: Restoring and Non-Restoring Division Evaluation of Some Implementations.

Division by invariant integers using multiplication

Abstract: Integer division remains expensive on today's processors as the cost of integer multiplication declines. We present code sequences for division by arbitrary nonzero integer constants and run-time invariants using integer multiplication. The algorithms assume a two's complement architecture. Most also require that the upper half of an integer product be quickly accessible. We treat unsigned division, signed division where the quotient rounds towards zero, signed division where the quotient rounds towards -∞, and division where the result is known a priori to be exact. We give some implementation results using the C compiler GCC.

Optical cross-connect system with space and wavelength division switching stages for minimizing fault recovery procedures

Abstract: In an optical cross-connect system, incoming and outgoing fiber optic trunks carrying WTDM signals are terminated to first inlet ports and first outlet ports of an optical space switch. A wavelength division demultiplexer is connected to a second outlet port of the optical space switch and a wavelength division multiplexer is connected to a second inlet port of the optical space switch. A wavelength-divided space switch has first inlet ports connected to the outputs of the wavelength division demultiplexer and first outlet ports connected to the inputs of the wavelength division multiplexer. A time division demultiplexer is connected to a second outlet port of the wavelength-divided space switch and a time division multiplexer is connected to a second inlet port of the wavelength-divided space switch. The outputs of the time division demultiplexer are connected to first inlet ports of a time switch and the inputs of the time division multiplexer are connected to first outlet ports of the time switch. The time switch has second inlet ports and second outlet ports connected to a switched network.

Comparisons of Size, Strength, Speed, and Power in NCAA Division 1-A Football Players

Abstract: Starters and nonstarters on NCAA Division I-A football teams were compared on the predictor variables of body weight, bench press and squat strength, vertical jump height, and 36.6-m run time according to 16 offensive and defensive positions. Data were obtained in 1,618 players from 11 universities. Of the 80 comparisons (position by variables) made, there were significant differences (p < 0.05) favoring the starters in 32 (40%). It was concluded that sufficient relationships exist between playing status (starter and nonstarter) and the predictor variables to indicate that such data could be helpful to coaches in making decisions on player position and status and in developing training programs to meet the needs of individual players at specific positions.

Parallel modified signed-digit arithmetic using an optoelectronic shared content-addressable-memory processor

Abstract: Addition is the most primitive arithmetic operation in digital computation. Other arithmetic operations such as subtraction, multiplication, and division can all be performed by addition together with some logic operations. With the binary number system, addition speed is inevitably limited by the carry-propagation schemes. On the other hand, carry-free addition is possible when the modified signed-digit (MSD) number representation is used. We propose a novel optoelectronic scheme to handle the parallel MSD addition and subtraction operations. An optoelectronic shared content-addressable memroy is introduced. The shared content-addressable memory uses free-space optical processing to handle the large amount of parallel memory access operations and uses electronics to postprocess and derive logic decisions. We analyze the accuracy that the required optical hardware can deliver by using a statistical cross-talk-rate model that we propose. We also evaluate other important device and system performance parameters, such as the memory capacity or the maximum number of parallel bits the adder can handle in terms of a given cross-talk rate at a certain repetition rate, the corresponding diffraction-limited memory density, and the system’s power efficiency. To confirm the underlining operational principles of the proposed optoelectronic shared content-addressable-memory MSD adder, we design and perform initial experiments for handling 8-bit MSD number addition and subtraction and present the results.

Method for manipulating notes on a computer display

Abstract: A method for manipulating notes on a screen of a computer display is provided. Each note area may include graphical, text, and data objects. An initial note area is provided with a header bar which includes the date of creation, the note number, and/or other indicia. When a user desires to make a new note, a division gesture is made on the computer display by moving a stylus horizontally across the screen. Once a division gesture is detected, the height of the preceding note is determined, and the height of the new note is considered to be indefinite or infinite. Each new division gesture creates a new header bar for the new note indicating the date of creation, the note number, and/or other pertinent information.

PLL frequency synthesizer and PLL frequency synthesizing method capable of obtaining high-speed lock-up and highly-reliable oscillation

Abstract: According to an output from a voltage-controlled oscillator, there are generated by a fractional divider a high-frequency division signal and a low-frequency division number. A phase comparison is conducted between the high-frequency division signal and a high-frequency reference signal by a phase comparator. A phase comparison is carried out between the low-frequency division signal and a low-frequency reference signal by a phase comparator. Either one of the outputs from the phase comparators is selected by a selector to be fed to a filter, thereby producing a control voltage for the voltage-controlled oscillator. A high-resolution division is achieved by the fractional division; consequently, disturbance of the oscillation frequency due to a change-over of the selector is suppressed. There is obtained a PLL frequency synthesizer developing a high-speed lock-up and a highly stable oscillation.

Decoder for decoding ECC using Euclid's algorithm

Abstract: A decoder in the form of a Euclid's algorithm operation circuit in which division polyonomials are repeatedly divided by residues resulting from the division process of dividend polynomials and division polynomials until the degree of residues of the division process satisfies a prescribed condition. The Euclid's algorithm operation circuit comprises register groups for storing dividend polynomials and division polynomials, respectively, a feedback loop for storing residues resulting from the division process of the dividend polynomials by the division polynomials, a shifter for shifting contents of registers, and an exchanger for exchanging coefficients of the dividend polynomials with coefficients of the division polynomials. The decoder comprises a syndrome operator for calculating syndromes from received code-words, an erasure locator generator for generating erasure locator data from erasure locator flags synchronous with received code-words, a modified syndrome generator for generating modified syndromes, an erasure locator polynomial generator for generating erasure locator polynomials from the erasure locator data, a Euclid's algorithm operation circuit for obtaining error locator polynomials and error value polynomials, a Chien searcher for obtaining error locations and error values and a correction processor for correcting errors of the received code-word. The modified syndrome generator and the erasure locator polynomial generator are used jointly with the Euclid's algorithm operation circuit.

Optimal initial approximations for the Newton-Raphson division algorithm

Abstract: Newton-Raphson iteration provides a high-speed method for performing division. The Newton-Raphson division algorithm begins with an initial approximation to the reciprocal of the divisor. This value is iteratively refined until a specified accuracy is achieved. In this paper, we develop methods for selecting constant and linear approximations which minimize the maximum absolute error of the final result. These approximations are compared with previous methods which minimize the maximum relative error in the final result or the maximum absolute error in the initial value.

Method and system for performing floating-point division using selected approximation values

Abstract: A method and system for performing floating-point division of a dividend by a divisor within a floating-point unit having multiply and add functions are disclosed. In performing floating-point division, a quotient having a mantissa is produced. The method uses an approximation based on a linear approximation stored within a first table. The first approximation approximates two divided by the divisor. A second table value is also selected from the table lookup. The second table value approximates the reciprocal of the divisor squared. Both the first and second table values operate as linear correction terms. Also according to the present invention, a method and system are disclosed that perform an early exit check during the division operation to confirm whether the resultant quotient has an acceptable accuracy and if the accuracy is unacceptable, then perform a rounding correction based upon a given rounding boundary.

On the Division of Environments by Virtual Walls for Radiosity Computation

Abstract: Based on previous works oriented to reduce the complexity of big environments, the paper presents a feasibility study of a dividing strategy. The original environment is divided into local environments introducing virtual walls. Then, the local environments are treated separately and local results are transfered to the neighbouring local environments.

High-radix division and square-root with speculation

Abstract: The speed of high-radix digit-recurrence dividers and square-root units is mainly determined by the complexity of the result-digit selection. We present a scheme in which a simpler function speculates the result digit, and, when this speculation is incorrect, a rollback or a partial advance is performed. This results in operations with a shorter cycle time and a variable number of cycles. The scheme can be used in separate division and square-root units, or in a combined one. Several designs were realized and compared in terms of execution time and area. The fastest unit considered is a radix-512 divider with a partial advance of six bits. >

Division technique unified quantizer-dequantizer

Abstract: A division technique unified quantizer-dequantizer circuit is disclosed. The unified quantizer-dequantizer includes a division circuit receiving a half step size q and an input signal x. The division circuit outputs a quantized coefficient signal y and a remainder R, where ##EQU1## The unified quantizer-dequantizer also includes a circuit receiving the quantized coefficient signal y, the remainder R, the half step size q and the input signal x. This circuit outputs a reconstructed signal r where, ##EQU2##

A proof of the nonrestoring division algorithm and its implementation on an ALU

Abstract: This article describes a proof of the functional correctness of a nonrestoring division algorithm and its implementation on an ALU. The first part of the proof deals with the correctness of the division algorithm with respect to a specification of division on the integer level. The second part is concerned with the correctness of the actual implementation, which is proven by checking several refinements of the algorithm. All the proofs have been mechanically checked with the Boyer-Moore theorem-proving system, in some cases making use of the interactive proof checker for the system.

Remote control system

Abstract: PURPOSE:To improve the operability of a cursor on a wide screen by holding the displacing positions of operating means such as a joy stick and a shuttle bull at more than a prescribed angle in a prescribed time, and increasing the moving speed of the cursor. CONSTITUTION:A CPU 21 decodes a command transmitted by the displacement of a joy stick of a remote commander 5, and stores it in an area division register 30. Then, a direction in which the cursor is moved is set in a cursor moving direction setting register 31 corresponding to the command data in the area division register 30, and whether or not the direction is the maximum inclined angle is discriminated. Moreover, when the displacing direction of the joy stick 6 is held the same, the moving speed of the cursor is increased. That is, at the time of moving the cursor along a wide range, and operating the selection of each kind of item or the like, the joy stick 6 is held at the maximum inclined angle against the moving direction in the prescribed time, and the further speedy selecting operation can be attained.

A CMOS floating-point vector-arithmetic unit

Abstract: This work describes a floating-point arithmetic unit based on the CORDIC algorithm. The unit computes a full set of high level arithmetic and elementary functions: multiplication, division, (co)sine, hyperbolic (co)sine, square root, natural logarithm, inverse (hyperbolic) tangent, vector norm, and phase. The chip has been integrated in 1.6 /spl mu/m double-metal n-well CMOS technology and achieves a normalized peak performance of 220 MFLOPS. >

Optical cross-connect system with space and wavelength division switching stages.

Abstract: In an optical cross-connect system, incoming and outgoing fiber optic trunks carrying WTDM signals are terminated to first inlet ports and first outlet ports of an optical space switch. A wavelength division demultiplexer is connected to a second outlet port of the optical space switch and a wavelength division multiplexer is connected to a second inlet port of the optical space switch. A wavelength-divided space switch has first inlet ports connected to the outputs of the wavelength division demultiplexer and first outlet ports connected to the inputs of the wavelength division multiplexer. A time division demultiplexer is connected to a second outlet port of the wavelength-divided space switch and a time division multiplexer is connected to a second inlet port of the wavelength-divided space switch. The outputs of the time division demultiplexer are connected to first inlet ports of a time switch and the inputs of the time division multiplexer are connected to first outlet ports of the time switch. The time switch has second inlet ports and second outlet ports connected to a switched network.

Semiconductor aggregate substrate and semiconductor device with fuse structure to prevent breakdown

Abstract: Electrostatic breakdown is avoided during fabrication of individual semiconductor devices using a semiconductor aggregate substrate. The semiconductor aggregate substrate is comprised of a large wafer. A plurality of sections are provided on the surface of the wafer, which are divided by division lines. A display active matrix circuit is integrally formed in each of the segments through normal IC production processing. Guard ring patterns are provided so that they surround the individual display active matrix circuits. A connection pattern is also provided for commonly connecting the guard ring patterns adjoining each other through the division lines. The connection pattern has opening structures for dealing with an external overcurrent on both sides of the division lines. The opening structures are constituted by, for example fuse patterns.

Division unit with Newton-Raphson approximation and digit-by-digit refinement of the quotient

Abstract: The advantages of the convergence with the square of the Newton-Raphson method are combined with the precision characteristics of digit-by-digit algorithms to obtain units for fast division that satisfy the IEEE 754 floating point standard requirements. A general design methodology that leads to a class of alternative architectures providing interesting performances for division is presented, together with one example of possible implementation. In particular, the proposed implementation achieves a speedup varying from 20% to about 30% in comparison with a previous architecture by Fandrianto, with a relatively small additional hardware cost if a multiplier is already available on the arithmetic unit.

Image processing apparatus having unevenly gamut dividing color-converting function

Abstract: An uneven dividing unit unevenly divides an input gamut into divisions which have figures similar to one another. An output-value determining unit determines predetermined lattice-point output values relevant to the divisions. A division selecting unit selects a division among the divisions obtained through the uneven dividing unit, the selected division corresponding to given input color-image data. An interpolating unit interpolates final output values for the given input color-image data using the lattice-point output values relevant to the division selected through the division selecting unit. The uneven dividing performed by the uneven dividing unit is that eliminating lattice points, the lattice-point output values of which are not used in the interpolating performed by the interpolating unit.

A study on the stochastic computation using the ratio of one pulses and zero pulses

Abstract: Stochastic computation uses pulse streams to represent numbers. In this paper, we have studied the novel method to implement the number system which uses the ratio of the number of one (high) pulses and the number of zero (low) pulses in a pulse stream. With this number system, if we let P be the probability that the pulse is one in a pulse stream, then the number Y we want to deal with is defined as Y=P/(1-P). We have studied the method to implement the basic operations such as an addition, a multiplication and a division using this number system and considered the error characteristics of such operations in stochastic computation. Also we introduce an averaging circuit to reduce the error which is inherent in stochastic computation. According to the study, by using this number system we can implement artificial neural networks and represent the simulation results for the digit recognition problem. >

Iterative division apparatus, system and method forming plural quotient bits per iteration

Abstract: An iterative division technique which forms plural quotient bits per iteration. A data processing apparatus (1100) includes a first register (1101) storing the divisor, a second register initially storing the numerator (1103), a plurality of full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) and an equal number of negative detectors (1122, 1123, 1124, 1125, 1126, 1127, 1128), and a loop counter (1131). Initially the full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) compute each integral product of the divisor not a power of 2 between 1 and 2 M -1 inclusive, where M is the number of quotient bits to be computed. These factors are stored in latches (1144, 1146, 1147, 1148). The full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) next subtract in parallel each integral product of the divisor between 1 and 2 M -1 inclusive from the most significant bits of the numerator. Negative detectors (1122, 1123, 1124, 1125, 1126, 1127, 1128) connected to each full adder (1112, 1113, 1114, 1115, 1116, 1117, 1118) indicate the first non-negative difference, which determines plural bits of the quotient and a partial remainder. This process is repeated with partial remainder left shifted M places employed as the numerator a number of iterations based upon the size of the numbers employed and the number of bits per iteration. For signed division the sign of the quotient is set as the exclusive OR of the detected (1102, 1104) respective signs of the numerator and the divisor.

Computing division polynomials

Abstract: Recurrence relations for the coefficients of the nth division polynomial for elliptic curves are presented These provide an algorithm for computing the general division polynomial without using polynomial multiplications; also a bound is given for the coefficients, and their general shape is revealed, with a means for computing the coefficients as explicit functions of n

Cluster classification device

Abstract: PURPOSE:To obtain a proper cluster classification which is free from overintegration and overdivision without previous knowledge by generating a distribution chart of quantities showing similarity of prototypes between adjacent elements on a map from the map, and dividing the map. CONSTITUTION:The data input part 111 of a map generation part 11 inputs an input data group consisting of vectors belonging to respective clusters and a map part 112 generates the map 31 by using the input data group. Then, the distribution generation part 121 of a map analysis part 12 calculates the quantities showing the degrees of integration of the clusters by elements to generate a histogram for the elements. The similarity between a prototype assigned to on element on the map 31 and a prototype assigned to an adjacent element is used as the quantities and a distribution division part 122 divides the histogram, cluster by cluster. Further, the map label part 131 of a a labeling part 13 labels the map-divided parts respectively, and the input data group is labeled by a data input part 132.

System for the measurement of the absolute position of the movable cyclic division mark carrier of an incremental position indicator

Abstract: Process for the measurement of the absolute position of the movable, cyclic division mark carrier of an incremental position indicator or rotation indicator/resolver within and/or with regard to one of its divisional segments, periodically formed and/or delimited by the division marks on the carrier, with two scanning elements, stationarily arranged and addressing the division marks, which are positioned at such a distance from one another along the length or periphery of the segment that they deliver two sine- and cosine-like measurement signals which are evaluated on the basis of the arctangent function for position determination, by utilizing the values or components of a parameter vector identifying the measurement process, which is continuously redetermined during the measurement operation according to preset optimization criteria, for correction of the evaluation for disturbances and inaccuracies in the position indicator.