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Showing papers on "Division (mathematics) published in 2003"


Journal ArticleDOI
TL;DR: Two ways of embedding noncommutative division algebras into matrices: left regular representation, and representation over maximal cyclic subfields are discussed.
Abstract: We present some general techniques for constructing full-rank, minimal-delay, rate at least one space-time block codes (STBCs) over a variety of signal sets for arbitrary number of transmit antennas using commutative division algebras (field extensions) as well as using noncommutative division algebras of the rational field /spl Qopf/ embedded in matrix rings. The first half of the paper deals with constructions using field extensions of /spl Qopf/. Working with cyclotomic field extensions, we construct several families of STBCs over a wide range of signal sets that are of full rank, minimal delay, and rate at least one appropriate for any number of transmit antennas. We study the coding gain and capacity of these codes. Using transcendental extensions we construct arbitrary rate codes that are full rank for arbitrary number of antennas. We also present a method of constructing STBCs using noncyclotomic field extensions. In the later half of the paper, we discuss two ways of embedding noncommutative division algebras into matrices: left regular representation, and representation over maximal cyclic subfields. The 4/spl times/4 real orthogonal design is obtained by the left regular representation of quaternions. Alamouti's (1998) code is just a special case of the construction using representation over maximal cyclic subfields and we observe certain algebraic uniqueness characteristics of it. Also, we discuss a general principle for constructing cyclic division algebras using the nth root of a transcendental element and study the capacity of the STBCs obtained from this construction. Another family of cyclic division algebras discovered by Brauer (1933) is discussed and several examples of STBCs derived from each of these constructions are presented.

516 citations


DOI
25 Jul 2003
TL;DR: In this article, a method for designing bundles in a combinatorial auction protocol that is robust against false-name bids has been presented, where the auctioneer first finds a good division with a winner determination algorithm, and then construct a leveled division set by using this division as a seed.
Abstract: This paper presents a method for designing bundles in a combinatorial auction protocol that is robust against false-name bids. Internet auctions have become an integral part of Electronic Commerce and a promising field for applying AI technologies. However, the possibility of a new type of cheating called a false-name bid, i.e., a bid submitted under a fictitious name, has been pointed out. A protocol called Leveled Division Set (LDS) protocol that is robust against false-name bids has been developed. However, this protocol requires the auctioneer to define a leveled division set. A leveled division set is a series of division sets, where a division set is a set of divisions and a division is a combination of bundles of goods. We need to solve a very complicated optimization problem to construct a leveled division set in order to obtain a good social surplus. We have developed a heuristic method for overcoming this problem. In this method, we first find a good division with a winner determination algorithm, and then construct a leveled division set by using this division as a seed. Through a simulation, we showthat our method can obtain a social surplus that is very close to optimal.

139 citations


Patent
01 May 2003
TL;DR: In this paper, non-binary computing methods utilize a digital multistage phase change material to perform addition, subtraction, multiplication, and division with the controlled application of energy.
Abstract: Non-binary computing methods utilize a digital multistage phase change material. Addition, subtraction, multiplication, and division are accomplished with the controlled application of energy to a phase change material. Energy in an amount insufficient to set the reset state of a phase change material is provided to store one or more numbers and further energy characteristic of the performance of the mathematical operation is provided to effect a computation

139 citations


Patent
05 Dec 2003
TL;DR: In this paper, the authors proposed a radio communication method to use the spatial degree of freedom at its maximum and provide radio communication system having an improved communication capacity by using the radio communication methods.
Abstract: In the environment of a communication area including a SDM-compatible mobile station for space division multiplex transmission and a SDM-uncompatible mobile station not compatible with space division multiplex transmission, a base station having a plurality of antennas and capable of adaptively changing directivity performs allocation of a mobile station which simultaneously performs space division multiplex transmission (SDM) and space division multiplex access (SDMA) by using a predetermined space division multiplex transmission evaluation criterion and a space division multi access evaluation criterion. By using this radio communication method, it is possible to use the spatial degree of freedom at its maximum and provide a radio communication system having an improved communication capacity.

130 citations


01 Jan 2003
TL;DR: The complexity class PMCF of all decision problems solvable in polynomial time by a family of P systems belonging to a given class of membrane systems with input, F, was introduced in this article.
Abstract: In this paper we introduce the complexity class PMCF of all decision problems solvable in polynomial time by a family of P systems belonging to a given class of membrane systems with input, F. We show that the problem of determining if a boolean formula in conjunctive normal form is satisfiable belongs to PMCAM, where AM is the class of recognizer P systems with input and with active membranes using 2-division. We conclude that the class NP is contained in the above mentioned complexity class.

108 citations


Journal ArticleDOI
TL;DR: This paper shows how theorems of Borsuk-Ulam and Tucker can be used to construct a consensus-halving: a division of an object into two portions so that each of n people believe the portions are equally split.

88 citations


Patent
06 Jun 2003
TL;DR: In this paper, a method for performing computations in a mathematical system which exhibits a positive lyapunov exponent, or exhibits chaotic behavior, comprises varying a parameter of the system, such as, e.g., in a pseudo-random number generator of a stream-cipher algorithm, in a blockcipher system or a HASH/MAC system, unpredictability may be improved.
Abstract: A method for performing computations in a mathematical system which exhibits a positive lyapunov exponent, or exhibits chaotic behavior, comprises varying a parameter of the system. When employed in cryptography, such as, e.g., in a pseudo-random number generator of a stream-cipher algorithm, in a block-cipher system or a HASH/MAC system, unpredictability may be improved. In a similar system, a computational method comprises multiphying two numbers and manipulating at least one of the most significant bits of the number resulting from the multiplication to produce an output. A number derived from a division of two numbers may be used for deriving an output. In a system for generating a sequence of numbers, an array of counters is updated at each computational step, whereby a carry value is added to each counter. Fixed-point arithmetic may be employed. A method of determining an identification value and for concurrently encrypting and/or decrypting a set of data is disclosed.

74 citations


Journal ArticleDOI
TL;DR: New nonlinear analysis tools for harmonic-injection dividers are presented based on bifurcation concepts, which allow control over the divided frequency and output power and predict the variation of the synchronization bands versus the circuit element values, which facilitates design correction.
Abstract: New nonlinear analysis tools for harmonic-injection dividers are presented based on bifurcation concepts. The advantage of these tools is their application simplicity and efficiency, which has enabled their use for actual circuit design and optimization. The tools allow control over the divided frequency and output power and predict the variation of the synchronization bands versus the circuit element values, which facilitates design correction. They have been extended to the analysis and optimization of phase-locked harmonic-injection dividers, which contain a low-frequency feedback loop. The use of this loop, together with the accuracy of the analysis, has enabled the implementation of novel frequency-division functions, such as the division of variable order, versus a circuit parameter, or the division by fractional order. The output noise of the frequency dividers is analyzed through the conversion-matrix approach, studying the noise variation along the division bands. The new techniques have been applied to the design of a frequency divider by order 4 and 5, with 18-GHz input frequency, and excellent agreement with experimental results has been obtained.

67 citations


Patent
29 Apr 2003
TL;DR: In this paper, a vehicle window seal assembly (10) includes a division bar (200) formed without structural metal and including one of an insert or an overlay layer of a relatively soft material.
Abstract: A vehicle window seal assembly (10) includes a division bar (200) formed without structural metal and including one of an insert or an overlay layer of a relatively soft material. The division (200) bar can be formed in an H configuration (210) having an elastic hinge (220) between a leg (212,214) of the H profile and a cross piece (216). The division bar (200) can also be formed to receive and engage the insert (250) to locate sealing lips (242) for contacting a moveable glass panel.

53 citations


Journal ArticleDOI
TL;DR: Findings provide support for the view that large single-digit division facts are mediated via multiplication-based representations and that multiplication is the primary mode of representation for both division and multiplication facts.
Abstract: In 2 experiments participants solved division problems presented in multiplication-based formats (e.g., 8 x _ = 72) more quickly than division problems presented in division-based formats (e.g., 72 / 8 = _). In contrast, participants solved multiplication problems presented in a division-based format (e.g., _ / 8 = 9) slowly and made many errors. In both experiments, the advantage for multiplication-based formats on division problems was found only for large problems (i.e., those with products or dividends greater than 25). These findings provide support for the view that large single-digit division facts are mediated via multiplication-based representations and that multiplication is the primary mode of representation for both division and multiplication facts.

51 citations


Patent
06 Oct 2003
TL;DR: In this article, a technique for a time division multiplex system in which access to shared broadcast communication media is granted on a demand basis is proposed, where particular connections are assigned slot times at the transmitter based on demand.
Abstract: A technique for a time division multiplex system in which access to shared broadcast communication media is granted on a demand basis. Particular connections are assigned slot times at the transmitter based on demand. However, no specific information regarding the assignment of time slots need be communicated to the receivers. The transmit side employs a forward error correction technique followed by multiplication by a cover sequence unique to each connection. All receivers listen to the broadcast transmission channel all of the time. The receiver assigned to each connection decodes the data associated with that connection. Data frames that fail the forward error correction process are discarded, and only those frames which are successfully decoded are passed up to a higher layer.

DOI
01 Jan 2003
TL;DR: In this article, the National Science Foundation Division of Design, Manufacturing, and Industrial Innovation (DMI-0200270) grant was used to support the Materials Processing and Manufacturing Programs (MPMPs) program.
Abstract: This research was supported by the National Science Foundation Division of Design, Manufacture and Industrial Innovation, through the Materials Processing and Manufacturing Program, award number DMI-0200270.

Proceedings ArticleDOI
B.R. Lee1, N. Burgess1
09 Apr 2003
TL;DR: This paper presents the design of parameterized fixed-point integer multiplication, squaring and fractional division units targeted at the Virtex-II family of FPGAs from Xilinx and are based on the small 18X18-bit multiplier blocks.
Abstract: This paper presents the design of parameterized fixed-point integer multiplication, squaring and fractional division units. The units are targeted at the Virtex-II family of FPGAs (field programmable gate arrays) from Xilinx and are based on the small 18X18-bit multiplier blocks. New partial product creation and summation techniques that exploit the low level primitives are used that achieve a 20% area and a 30% delay reduction for multiplication. A dedicated squaring component is presented that offers substantial area savings of up to 50%. The division component uses the multipliers for pre-scaling to reduce the delay and complexity of each minimally redundant radix-8 stage.

Patent
Yoichi Nagaso1, Takaharu Saeki1
27 Aug 2003
TL;DR: In this article, a fractional frequency divider (FDFD) is defined, which includes a latch (31) for holding frequency division data, a ΔΣ modulator (33), a digital dither circuit (32), and circuit means (34 through 38) for executing FDFD based on integer part (M value) of the data and an output of the modulator.
Abstract: A fractional frequency divider ( 28 ) includes a latch ( 31 ) for holding frequency division data, a ΔΣ modulator ( 33 ), a digital dither circuit ( 32 ) for receiving a digital input F representing fraction part of the frequency division data from the latch ( 31 ) and supplying a digital output alternately changing between F+k and F−k (where k is an integer) or a F value itself to the ΔΣ modulator ( 33 ), and circuit means ( 34 through 38 ) for executing fractional frequency division based on integer part (M value) of the frequency division data and an output of the ΔΣ modulator ( 33 ). The digital dither circuit ( 32 ) is useful for suppressing a spurious signal generated as a result of concentration of quantization noise at a particular frequency when the ΔΣ modulator ( 33 ) receives a particular F value (e.g., F=2 n−1 ).

Patent
24 Oct 2003
TL;DR: In this paper, an image processing apparatus includes a memory which stores a code stream having a wavelet division level, an interface unit which transmits the code stream to another apparatus, and a processing unit which changes the wavelet-division level of the stream before the transmission of the code streams to such another apparatus by acquiring a target division level that is a wavelett division level of such an apparatus.
Abstract: An image processing apparatus includes a memory which stores a code stream having a wavelet division level, an interface unit which transmits the code stream to another apparatus, and a processing unit which changes the wavelet division level of the code stream before the transmission of the code stream to such another apparatus by acquiring a target division level that is a wavelet division level of such another apparatus, checking a difference between the target division level and the wavelet division level of the code stream, generating data that compensates for the difference, and embedding the generated data into the code stream.

Proceedings ArticleDOI
15 Jun 2003
TL;DR: It is applied to show that a few bits of precision can be saved in the floating-point division (FP-DIV) microarchitecture of the AMD-K7/spl trade/ microprocessor.
Abstract: Back in the 60's Goldschmidt presented a variation of Newton-Raphson iterations for division that is well suited for pipelining. The problem in using Goldschmidt's division algorithm is to present an error analysis that enables one to save hardware by using just the right amount of precision for intermediate calculations while still providing correct rounding. Previous implementations relied on combining formal proof methods (that span thousands of lines) with millions of test vectors. These techniques yield correct designs but the analysis is hard to follow and is not quite tight. We present a simple parametric error analysis of Goldschmidt's division algorithm. This analysis sheds more light on the effect of the different parameters on the error. In addition, we derive closed error formulae that allow to determine optimal parameter choices in four practical settings. We apply our analysis to show that a few bits of precision can be saved in the floating-point division (FP-DIV) microarchitecture of the AMD-K7/spl trade/ microprocessor. These reductions in precision apply to the initial approximation and to the lengths of the multiplicands in the multiplier. When translated to cost, the reductions reflect a savings of 10.6% in the overall cost of the FP-DIV microarchitecture.

Patent
09 Jul 2003
TL;DR: In this paper, a plurality of communications (24, 26, 28) are transmitted in a code division multiple access (CDMA) system and the transmitted communications are received (32, 34, 36).
Abstract: Data from a plurality of communications (24, 26, 28) is transmitted in a code division multiple access communication system. The transmitted communications are received (32, 34, 36). Gain factors (2) are determined for at least one of the received communications. Data of the received communications is detected using a scaling factor (40) derived from the determined gain values.

Patent
Hai Jin1, Xiao Fei Liao1, Qiong Hua Hu1
06 Aug 2003
TL;DR: In this article, a program divisio distributed storing method which is based on cluster video server film resource is described. But the method is not suitable for large-scale data storage systems.
Abstract: The invention refers to a program divisio distributed storing method which is based on cluster video server film resource. It includes following steps: 1) flow media net message definition, flow media distributed control files definition and slice files definition, 2) the flow media source files signal obtaining step, and the user requiring signal obtaining, 3) division files placing static definition, 4) the generation of flow media files analysis and slice task list, 5) division task performing, 6) division transfer storing.

Journal ArticleDOI
TL;DR: The authors showed that children who start with problem situations directly model solutions to these problems and later move to more advanced mathematical approaches as they progress through levels of solutions and problem difficulty, thus, their development of computational fluency and their acquisition of problem-solving skills are intertwined as both develop with understanding.
Abstract: problem situations yields greater problem-solving competence and equal or better computational competence. Children who start with problem situations directly model solutions to these problems. They later move to more advanced mathematical approaches as they progress through levels of solutions and problem difficulty. Thus, their development of computational fluency and their acquisition of problem-solving skills are intertwined as both develop with understanding.

Patent
12 Aug 2003
TL;DR: A visual method of teaching arithmetic, in which graphical representations of familiar objects are used instead of numbers, is particularly well suited for children who are visually oriented and have difficulty with numbers as mentioned in this paper.
Abstract: A visual method of teaching arithmetic, in which graphical representations of familiar objects are used instead of numbers, is particularly well suited for children who are visually oriented and have difficulty with numbers. The shapes of the objects resemble the numerals zero through nine. The objects may appear in any visual medium. Students are first shown examples of multiplication, division, addition, and subtraction, in which objects replace numbers. Each object is then shown by itself. The numeral that corresponds to the number value of each object is then overlaid on top of each object. Students are also shown groups of colored dots or balls, in which the colors of the dots match the colors of the objects and the number of dots corresponds to the numerical value represented by its corresponding object.

Patent
15 May 2003
TL;DR: In this paper, a method of playing a mathematical game to calculate a target value includes generating the target value randomly, generating a plurality of calculating numbers to be used to calculate the target values, and calculating, by a first player, an initial solution by combining the calculating numbers with any combination of any plurality of mathematical operations in any order.
Abstract: A method of playing a mathematical game to calculate a target value includes generating the target value randomly, generating a plurality of calculating numbers to be used to calculate the target value, and calculating, by a first player, an initial solution that is equal to the target value, by combining the calculating numbers with any combination of a plurality of mathematical operations in any order. The calculating numbers can also be generated randomly and the plurality of mathematical operations includes addition, subtraction, multiplication, division, powers and roots. If the first player fails to attain the initial solution equal to the target value, then an alternate solution is attained by the first player that approximates the target value. The second player then uses the same previously generated calculating numbers, with a second different combination of the plurality of mathematical operations in any order, to calculate a second solution that is equal to the target value, or more closely approximates the target value than the first player. The game continues until the target value is attained, or a final value is attained that most closely approximates the target value.

Patent
26 Mar 2003
TL;DR: In this article, the weights of the bit data were determined to be such as 2 0 :2 1 :2 2 :2 3−1 :..., in which a conventional ratio regulation of 1:2:4:8:
Abstract: When time division gradation display is carried out by setting a display state of an electro-optic element capable of R-gradation display A times in one frame period, the present invention determines the weights of the bit data to be such as 2 0 :2 1 :2 2 :2 3−1 : . . . , in which a conventional ratio regulation of 2 0 :2 1 :2 2 :2 3 : . . . i.e., 1:2:4:8: . . . is changed by at least one part at or later the third bit so as to satisfy the relation of B

Patent
01 Apr 2003
TL;DR: In this article, the authors propose a method to measure and monitor performance of processes across different organizational units within a system process by assigning first weight factors to organizational units at a first-level division of the system process.
Abstract: A method measures and monitors performance of processes across different organizational units within a system process. The method assigns first weight factors to organizational units at a first-level division of the system process, receives actual performance data for each of the organizational units at the first-level division, compares the actual performance data against a target to produce a deviation for each of the organizational units, assigns a number of points corresponding to the deviation of each of the organizational units, and determines a first process performance indicator for the first-level division based on the first weight factor and the number points of the organizational units. The method assigns a second weight factor to an organizational unit at a second-level division of the system process, and determines a second process performance indicator for the second-level division based on the second weight factor and the first process performance indicator.

Patent
19 Dec 2003
TL;DR: In this article, a plurality of original partial data are generated by dividing the original data by the prescribed processing unit bit length, and then the divided data in the desired number of division are generated from the plurality of divided partial data, such that the underlying original data cannot be ascertained from any one divided data alone but can be recovered from a prescribed number of divided data among generated divided data.
Abstract: A plurality of original partial data are generated by dividing the original data by the prescribed processing unit bit length, a plurality of random number partial data each having a length less than or equal to the prescribed processing unit bit length are generated in correspondence to the plurality of original partial data, and a plurality of divided partial data that constitute each divided data are generated by using exclusive OR calculation of the original partial data and the random number partial data, each divided partial data having a length equal to the prescribed processing unit bit length. Then, the divided data in the desired number of division are generated from the plurality of divided partial data, such that the original data cannot be ascertained from any one divided data alone but the original data can be recovered from a prescribed number of the divided data among generated divided data.

Patent
Naoki Ejima1
12 Jun 2003
TL;DR: In this article, a data reception device receives a division parameter N based on the video data pixel clock and the audio data sampling frequency transmitted from a data transmission device and a count value CTS counting the audio clock frequency after the division by using the pixel clock.
Abstract: As shown in Fig. 7, a data reception device receives a division parameter N based on the video data pixel clock and the audio data sampling frequency transmitted from a data transmission device and a count value CTS counting the audio clock frequency after the division by the division parameter N by using the pixel clock. The pixel clock is divided by the count value CTS and the divided clock (s501) after the division is phase-controlled by a phase comparison clock (s505) obtained by dividing an audio clock (s403) oscillated from a VCO (504) by the division parameter N. In this way, the audio clock (s403) is generated. Thus, it is possible to provide a data transmission device and a data reception device of simple configuration capable of preferably multiplexing a video data on audio data and transmitting them by using an existing cable of DVI standard.

Patent
08 Apr 2003
TL;DR: In this article, a vehicular image processor that can discriminate an accurate division line at a detection start or on a return from a detection-disabled state is proposed, and if no past white line recognition results are accumulated, an expected vehicle course is predicted from vehicle states, and the expected course and a traveled lane determined from the recognition results were compared.
Abstract: PROBLEM TO BE SOLVED: To provide a vehicular image processor that can discriminate an accurate division line at a detection start or on a return from a detection-disabled state SOLUTION: Image recognition (Step S1 to S5) acquires division line information, and if no past white line recognition results are accumulated, an expected vehicle course is predicted from vehicle states, and the expected course and a traveled lane determined from the recognition results are compared (Step S9) If the difference between them is within a given range, the division line recognition is presumed to be a success, and information on the recognized division line candidates is output as white line information, which is stored in a while line recognition ECU 1 (Step S10) COPYRIGHT: (C)2005,JPO&NCIPI

Book ChapterDOI
18 May 2003
TL;DR: A new division architecture for GF(2m) using the standard basis representation is proposed based on a modified version of the binary extended greatest common divisor (GCD) algorithm, which provides a compact and fast divider.
Abstract: Division over a finite field GF(2m) is the most time and area consuming operation. In this paper, A new division architecture for GF(2m) using the standard basis representation is proposed. Based on a modified version of the binary extended greatest common divisor (GCD) algorithm, we design a compact and fast divider. The proposed divider can produce division results at a rate of one per 2m - 1 clock cycles. Analysis shows that the computational delay time of the proposed architecture is significantly less than previously proposed dividers with reduced transistor counts. Furthermore, since the new architecture does not restrict the choice of irreducible polynomials and has the features of regularity and modularity, it provides a high flexibility and scalability with respect to the field size m.

Book ChapterDOI
08 Sep 2003
TL;DR: A novel technique for computing a 2n-bit modular multiplication using n-bit arithmetic was introduced at CHES 2002 by Fischer and Seifert and makes use of an Euclidean division based instruction returning the remainder and the integer quotient resulting from a modular multiplication.
Abstract: A novel technique for computing a 2n-bit modular multiplication using n-bit arithmetic was introduced at CHES 2002 by Fischer and Seifert. Their technique makes use of an Euclidean division based instruction returning not only the remainder but also the integer quotient resulting from a modular multiplication, i.e. on input x, y and z, both ⌊xy/ z⌋ and xy mod z are returned. A second algorithm making use of a special modular ‘multiply-and-accumulate’ instruction was also proposed.

Patent
24 Sep 2003
TL;DR: In this article, a diffractive micro-structure color wavelength division device makes use of diffraction theory, binary optics theory, and operation of phase iteration algorithm to its complex two-dimensional surface phase microstructure.
Abstract: A diffractive micro-structure color wavelength division device makes use of diffraction theory, binary optics theory, and operation of phase iteration algorithm to its complex two-dimensional surface phase micro-structure. The color wavelength division device has a multi-wavelength modulation function and is capable of wavelength division and focus, thereby resulting in structural simplification and enhancement of light utilized efficiency of a color image system.

Journal ArticleDOI
TL;DR: In this paper, a summary of considerations for teachers when assessing a student's understanding of division concepts is presented, along with examples of assessment activi cation activii cation.
Abstract: This article presents a summary of considerations for teachers when assessing a student's understanding of Division concepts. As with all mathematical concepts, children develop a basic idea of Division through interactions with others in daily life, beginning from the preschool years. As they move into elementary school, Division is introduced as an arithmetic operation, building on their prior knowledge of addition, subtraction, and multiplication. As children advance to middle school, various uses of fractional concepts are introduced, along with algorithms involving rational numbers. Although there is no clear demarcation as to the grade at which a more advanced level of understanding may be taught, for the purpose of discussion, this article is organized into three broad levels: Preschool, Elementary, and Middle School. Within each level, the assessment of (a) student products, (b) student procedures and strategies, and (c) student concepts and explanations, is presented. Examples of assessment activ...