Division (mathematics)

About: Division (mathematics) is a research topic. Over the lifetime, 12717 publications have been published within this topic receiving 87814 citations.

Fast Constant Division Routines

Abstract: When there is no division circuit available, the arithmetical function of division is normally performed by a library subroutine. The library subroutine normally allows both the divisor and the dividend to be variables, and requires the execution of hundreds of assembly instructions. This correspondence provides a fast algorithm for performing the integer division of a variable by a predetermined divisor. Based upon this algorithm, an efficient division routine has been constructed for each odd divisor up to 55. These routines may be implemented in assembly languages, in microcodes, and in special-purpose circuits.

Cascade: hardware for high/variable precision arithmetic

Abstract: The Cascade hardware architecture for high/variable precision arithmetic is described. It uses a radix-16 redundant signed-digit number representation and directly supports single or multiple precision addition, subtraction, multiplication, division, extraction of the square root, and computation of the greatest divisor. It is object-oriented and implements an abstract class of objects, variable precision integers. It provides a complete suite of memory management functions implemented in hardware, including a garbage collector. The Cascade hardware permits free tradeoffs of space versus time. >

A Division-Free Toom–Cook Multiplication-Based Montgomery Modular Multiplication

Abstract: Toom–Cook multiplication is a theoretically more efficient multiplication algorithm than traditionally used Karatsuba and schoolbook multiplication but is rarely used in practical hardware designs due to its inherent exact divisions, which are time-consuming and difficult for parallel and serial acceleration. This brief proposes a method of division-free Toom–Cook multiplication based Montgomery modular multiplication, which makes it possible for Toom–Cook multiplication to be applied in practical and efficient hardware implementations. We also provide a hardware implementation of modular multipliers of 256 bits and 1024 bits with advantages on area-time-product over previous researches.