Division (mathematics)

About: Division (mathematics) is a research topic. Over the lifetime, 12717 publications have been published within this topic receiving 87814 citations.

A low power zero-overhead self-timed division and square root unit combining a single-rail static circuit with a dual-rail dynamic circuit

Abstract: An asynchronous pipeline scheme that combines a low power static circuit with a high-speed dual-rail dynamic circuit is proposed. The scheme utilizes a dual-rail circuit only in the critical path of an SRT division and square root calculation unit. The proposed implementation of the calculation unit reduced power consumption by more than 1/2 of the full-dynamic implementation while maintaining the calculation speed. Because of the elimination of spurious transitions, the proposed implementation showed even less power consumption over synchronous static circuit implementations. By using 0.3 /spl mu/m triple metal CMOS technology, the calculation time of floating point 56-b full mantissa division and square root is expected to be 45 ns in the worst case.

Shared hardware for multiply, divide, and square root exponent calculation

Abstract: The same hardware is used to implement calculations of the exponents for multiplication, division, and square root in either double or single precision. A multiplexor selects the appropriate bias value necessary for exponent computation for the given instruction type, operand precision, and output precision. A first operand multiplexor selects either the exponent of the first operand in the case of a multiplication or division instruction, and selects zero in the case of a square root instruction, since the square root operation only requires one operand. The second operand multiplexor selects the second exponent in the case of a multiplication instruction, the one's complement of the second exponent in the case of a division instruction, and the second exponent divided by two during a square root operation. Flip-flop registers latch the exponent and incremented exponent when a division or square root operation is pending. A multiplexor select between the presently calculated exponents and the saved exponents calculated for a pending division or square root operation. If the instruction scheduler has flexibility in allowing out of order instruction completion, younger multiplication instructions can be dispatched and completed during the several machine cycles during which the division/square root mantissa computation.

Complex interval arithmetic using polar form

Abstract: In this paper, the polar representation of complex numbers is extended to complex polar intervals or sectors; detailed algorithms are derived for performing basic arithmetic operations on sectors. While multiplication and division are exactly defined, addition and subtraction are not, and we seek to minimize the pessimism introduced by these operations. Addition is studied as an optimization problem which is analytically solved. The complex interval arithmetic thus defined is illustrated with some numerical examples which show that in many applications, the polar representation is more advisable.