Showing papers on "Divisor published in 1968"

On periodic groups of automorphisms of extremal groups

Abstract: It is proved that if a periodic group $$\mathfrak{G}$$ has an extremal normal divisor $$\mathfrak{N}$$ , determining a complete abelian factor group $$\mathfrak{G}/\mathfrak{N}$$ , then the center of the group $$\mathfrak{G}$$ contains a complete abelian subgroup $$\mathfrak{A}$$ , satisfying the relation $$\mathfrak{G} = \mathfrak{N}\mathfrak{A}$$ and intersecting $$\mathfrak{N}$$ on a finite subgroup. It is also established with the aid of this proposition that every periodic group of automorphisms of an extremal group $$\mathfrak{G}$$ is a finite extension of a contained in it subgroup of inner automorphisms of the group $$\mathfrak{G}$$ .

Division system and method

Abstract: A system and method for digital division employing a composite of table lookup and iteration techniques. A stored logic table is used which generates a factor M which when multiplied against the divisor, provides a new divisor in a predetermined range close to unity in value. Both the divisor and the dividend are then multiplied by the factor M, the capacity of the table lookup determining the maximum difference of the new divisor from unity. The arrangement is such that, depending upon the difference between the new divisor and unity, a selected number of new partial quotient digits is directly determined from a selected number of digits in newly generated partial remainders. By generating quotient digits in successive groups, only a few iterations are needed to divide one long number by another. Successive division steps entail merely the generation of new partial products, and derivation of the difference of these partial products from the previous partial remainder. By arranging the significant portion of the new divisor to be a negative quantity in a preferred form of system, only adder circuits need by employed. A high speed, high capacity binary digital division system utilizing these techniques is further arranged to utilize carry-save adder circuits to utilize carry and sum quantities without introducing carry propagation delays, and otherwise minimize operating cycle time.