Showing papers on "Divisor published in 1983"

A carry-free algorithm for finding the greatest common divisor of two integers

Abstract: We investigate a variant of the so-called “binary” algorithm for finding the GCD (greatest common divisor) of two numbers which requires no comparisons We show that when implemented with carry-save hardware, it can be used to find the modulo B inverse of an n-bit binary integer in a time proportional to n, using only registers of length proportional to n Such a hardware implementation of this algorithm set up for finding inverses with respect to a 336 bit modulus B would have applications in the currently expanding field of secure data transmission and storage In such an implementation, multiplication in linear time-both modulo B and ordinary—would come along as a by-product because multiplication can be achieved by a sequence of nine inversions, some additions and negations

Apparatus and method for performing division with an extended range of variables

Abstract: A method and apparatus are disclosed which, for obtaining the quotient of division operations in a data processing apparatus, generate as an auxiliary value the inverse square root g of the divisor w. The auxiliary value g is then multiplied by the divident v, and the intermediate result again multiplied by the auxiliary value g. An improvement in operation of the data processing apparatus is obtained despite introduction of the auxiliary value because the range covered by the auxiliary value is significantly smaller than that of the direct inverse of the divisor. A preferred application is the area of signal processing in communications.

A fast algorithm for solving Toeplitz system of equations

Abstract: A fast algorithm for the solution of Toeplitz system of equations is presented. The algorithm requires order N (\log N)^{2} computations where N is the number of equations. For banded Toeplitz matrices the order of computations is reduced to only N \log N + m (\log m)^2 where 2m is the maximum number of nonzero principal subdiagonals of the Toeplitz matrix. The algorithm is in essence a fast implementation of the Trench algorithm in reverse. Thus the algorithm involves imbedding of the given matrix in a cyclic matrix and a fast HD (Half Divisor) algorithm to compute the first row of the inverse matrix. The desired solution is then obtained directly from the first row by applying Fast Fourier Transform techniques in order N \log N computations. Finally, the extension of the algorithm to block Toeplitz matrices is also presented.

Synchronous carry frequency divider and method of using therefor

Abstract: A synchronous carry frequency divider having a series of counters wherein each pair of counters is separated by a flip-flop and wherein the last counter in the series is followed by a terminal flip-flop. The counters and the flip-flops are synchronously clocked so that the divisor ratio is increased by the number of flip-flops employed. When the terminal flip-flop is toggled by the last counter a terminal count signal and a preset enable signal are simultaneously achieved without the delays associated with terminal count decode networks.

High radix division system

Abstract: PURPOSE:To realize a division circuit of a high radix with a simple hardware constitution and to attain high speed division, by obtaining a quotinent of a divisor and a dividend obtained from a divisor obtained newly and a partial residual, by one digit each from the upper-order digit sequentially. CONSTITUTION:The upper-order of a divisor (d) on an input line 20 is given to a reciprocal table 22. The (d) is set to a register 25, an output of the table 22, i.e., an approximate value of the reciprocal of the (d) is set to a register 26, the multiplication is executed by taking the content of the registers 25, 26 as dividend and divider respectively and the result is set to pipeline registers 39, 40. The upper-order bits of the registers 39, 40 are summed at a pre-addition circuit 41 to obtain an approximate value of a partial residual pj. A quotinent digit qi+1 is obtained from this approximate value at a quotinent digit generating circuit 42, the product between this value qj+1 and the content of the register 25 is calculated, and a new partial residual pj+1 is obtained from the content of the registers 39, 40 and the partial residual pj. This residual is set to the registers 39, 40 for the operation.

Gauge Functions and the Divisor Chain Condition

Abstract: A gauge function on a commutative cancellative monoid M is a map p : M?Z+(the set of nonnegative) integers such that for all a,b e?M, p(ab)≥ p(a)+p(b) and p(a) = 0 if and only if a is a unit. In [3], it is shown by V. Srinivasan and H. Shaing that if the monoid of nonzero elements of an integral domain A in which finitely‐generated ideals are principal admits a gauge function, then A is a principal ideal domain. In this paper I show that M admits a gauge function if and only if for each nonunit a e M there is a positive integer N = N(a) such that α is a product of no more than N(a) irreducibles. An example is given to show that this latter condition is stronger than the divisor chain condition defined in [2, 2.14].