Showing papers on "Divisor published in 1985"
TL;DR: Extended quasi-gcd computation means to find such h and additional cofactors u, ν such that uf + νg − h − h is an ϵ-approximate divisor of f and of g.
136 citations
04 Jun 1985
TL;DR: The conditions that the divisor must satisfy to have the quotient digit qi+1 predicted while computing R(i-1) are determined.
Abstract: A division algorithm with a simple selection of quotient digits including prediction is possible if the divisor is restricted to a suitable range. The conditions that the divisor must satisfy to have the quotient digit q i+1 predicted while computing R i+1 are determined. Some implementation considerations are also given.
41 citations
TL;DR: In this article, the authors consider divisor classes on elliptic modular surfaces S(n) and their associated linear systems, and the main role is played by divisors I which have the property that nI is linearly equivalent to the sum of n2 sections if n is odd.
Abstract: In this paper we consider divisor classes on elliptic modular surfaces S(n) and their associated linear systems. A principal role is played by divisors I which have the property that nI (resp. n/2I) is linearly equivalent to the sum of the n2 sections if n is odd (resp. even). Our main result is the description of four different projective realizations of S(5). Some results concerning S(3) and S(4) are also discussed.
29 citations
TL;DR: This correspondence provides a fast algorithm for performing the integer division of a variable by a predetermined divisor in assembly languages, in microcodes, and in special-purpose circuits.
Abstract: When there is no division circuit available, the arithmetical function of division is normally performed by a library subroutine. The library subroutine normally allows both the divisor and the dividend to be variables, and requires the execution of hundreds of assembly instructions. This correspondence provides a fast algorithm for performing the integer division of a variable by a predetermined divisor. Based upon this algorithm, an efficient division routine has been constructed for each odd divisor up to 55. These routines may be implemented in assembly languages, in microcodes, and in special-purpose circuits.
21 citations
TL;DR: In this article, it was shown that as x approaches ∞, #{n ≤ x: d(n) divides n} = ( x √ log x)( log log x) −1 + 0(1).
14 citations
Patent•
27 Jul 1985
TL;DR: In this article, a table information storage unit storing the difference between adjacent approximated reciprocals and an interpolation approximation circuit dividing proportionally the difference and applying the result in a way of approximated reciprocal.
Abstract: PURPOSE:To decrease the division execution time by providing a table information storage unit storing the difference between adjacent approximated reciprocals and an interpolation approximation circuit dividing proportionally the difference and applying the result in a way of approximated reciprocal CONSTITUTION:A divisor set to a divisor register 13 is normalized by a normalizing circuit 14, an approximated reciprocal M is read from a table information storage unit 17 by using a high-order bit of the divisor and the normalized divisor D0 is set to a mutliplicand selection circuit and register 15 After the precision of the approximated reciprocal is improved by an interpolation approximation circuit 18, a -M is outputted, the -M is selected by a multiplier selecting circuit 16 and the calculation of D0X(-M) is conducted by a multiplier 19 The produce is set to a multiplication result register 23 in this case Then after the dividened set to a dividened register 12 is normalized by the circuit 14, the dividened register 12 is set to the register 15 and also the calculation of N0XM is executed The D0X(-M) is set to the register 15 at the same time The calculation above is repeated The check and correction of the quotient are conducted during the repeated calculation
5 citations
TL;DR: In this article, an asymptotic formula for the number of positive integers n ≤ x such that (d, f ( n )) = 1, where f is an integer-valued multiplicative function such that f (p ) is a polynomial in p for p prime, and where d has no prime divisor from a certain finite exceptional set.
3 citations
01 Apr 1985
TL;DR: In this paper, the convergence of a sequence of distributions is studied for a positive integer N, where XN is a random variable uniformly distributed over the set {log d: dl N } and FN is the normalized distribution function for XN.
Abstract: For a positive integer N, let XN be a random variable uniformly distributed over the set {log d: dl N }. Let FN be the normalized (to have expectation zero and variance one) distribution function for XN. Necessary and sufficient conditions for the convergence of a sequence FN of distributions are given. The possible limit distributions are investigated, and the case where the limit distribution is normal is considered in detail.
2 citations
Patent•
26 Apr 1985
TL;DR: In this article, the carry of a result flag, a partial remainder, and a divisor during the arithmetic between a dividend and an arithmetic element was considered. But the carry was not considered in this paper.
Abstract: PURPOSE:To improve an arithmetic speed by deciding on large/small relation among the carry of a result flag, a partial remainder, and a divisor during the arithmetic between a dividend and a divisor 1, 2, or 4, and correcting the partial remainder and synthesizing the obtained quotient simultaneously. CONSTITUTION:An arithmetic computing element 4 when supplied with the dividend stored in a register 3 and any one of divisors 1, 2, and 4 stored in a divisor register 2 subtracts, for example, the divisor 4 from the dividend and controls a small flag according to whether the remainder obtained by the subtraction is larger than the divisor or not. Further, the divisors 2 and 1 are summed up according to the flag and the estimated value of the quotient is stored in a quotient estimating register 6. While this value is corrected by addition and subtraction, the quotient generated in an SOD register 12 is spilt in a shifter 10 and returned to a quotient register 9, and the dividend is shifted by four bits and supplied to the left of the arithmetic computing element 4 to find the next one quotient digit successively.
1 citations