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Showing papers on "Divisor published in 1990"


Patent
Brian M. Miller1
27 Nov 1990
TL;DR: In this paper, a fractional-N type frequency synthesizer includes a frequency divider having a selectable integer divide number which is periodically temporarily altered to provide an average rational divide number for the frequency dividers.
Abstract: A fractional-N type frequency synthesizer includes a frequency divider having a selectable integer divide number which is periodically temporarily altered to provide an average rational divide number for the frequency divider. A number of modulator circuits coupled in cascade fashion provide a zero sum modulation signal which varies the value of the frequency divider divisor value such that the net change in divisor value due to the modulation signal is zero thereby reducing phase noise resulting from the temporary altering of the integer divisor value close to the frequency synthesizer carrier frequency.

127 citations


01 Jan 1990
TL;DR: In this article, the authors discuss algorithms that solve two basic problems in computational number theory (factoring integers into prime factors and finding discrete logarithm) and their analyses depend on many different parts of number theory.
Abstract: Publisher Summary This chapter discusses algorithms that solve two basic problems in computational number theory—factoring integers into prime factors and finding discrete logarithms. In the factoring problem, one is given an integer n 1 and is asked to find the decomposition of n into prime factors. It is common to split this problem into two parts. The first is called primality testing: given n , it is determined whether n is prime or composite. The second is called factorization: if n is composite, a nontrivial divisor of n is to be calculated. In the discrete logarithm problem, one is given a prime number p , and two elements h, y of the multiplicative group F* p of the field of integers modulo p. The algorithms and their analyses depend on many different parts of number theory. Number theory is considered the purest of all sciences, and within number theory the hunt for large primes and for factors of large numbers has always been remote from applications, even to other questions of a number-theoretic nature.

119 citations


Journal ArticleDOI
TL;DR: It is shown that pseudocyclic MDS codes exist if and only if the multiplicative order of a divides (q-1)/n, and that when this condition is satisfied, such codes exist for all k.
Abstract: The (n, k) pseudocyclic maximum-distance-separable (MDS) codes modulo (x/sup n/-a) over GF(q) are considered. Suppose that n is a divisor of q+1. If n is odd, pseudocyclic MDS codes exist for all k. However, if n is even, nontrivial pseudocyclic MDS codes exist for odd k (but not for even k) if a is a quadratic residue in GF(q), and they exist for even k (but not for odd k) if a is not a quadratic residue in GF(q). Also considered is the case when n is a divisor of q-1, and it is shown that pseudocyclic MDS codes exist if and only if the multiplicative order of a divides (q-1)/n, and that when this condition is satisfied, such codes exist for all k. If the condition is not satisfied, every pseudocyclic code of length n is the result of interleaving a shorter pseudocyclic code. >

105 citations


Journal ArticleDOI
TL;DR: In this article, an estimator for the variance is developed by minimizing the mean squared error (MSE) using a generalized weight for the sum of squares instead of 1/(n − 1).
Abstract: An estimator (S W 2) for the variance is developed by minimizing the mean squared error (MSE) using a generalized weight for the sum of squares instead of 1/(n − 1). The optimal divisor found is (n + 1) + (α4 − 3) (n 1 1)/n, where α4 is the kurtosis. For the normal distribution (α4 = 3), the divisor becomes n + 1. Generally, for kurtosis greater than 3 the divisor will be greater than n + 1 and for kurtosis less than 3 the divisor will be less than n + 1. Using n + 1 as a divisor will result in a smaller MSE for distributions with α4 > 3.

60 citations


Journal ArticleDOI
G. Robert1
TL;DR: For any pair of lattices L and L satisfying i)L⊂L and ii) the indexN of L into L is prime to 6, the authors construct from the usual φ-function of L(cf. no 1) some elliptic function.
Abstract: For any pair of latticesL andL satisfying i)L⊂L and ii) the indexN ofL intoL is prime to 6, we construct from the usual φ-function ofL(cf. no 1) some elliptic function $$\psi = \psi (z;L,\underset{\raise0.3em\hbox{$\smash{\scriptscriptstyle-}$}}{L} )$$ of the variablez, with period latticeL, and divisor $$N(0)_L - \sum\limits_{i - 1}^N {(t_i )_L } $$ over the torus ℂL, where the complex numbersti, 1≦i≦N, describe a complete set of representatives of the quotientL/L.

25 citations


Journal ArticleDOI
TL;DR: In this article, the system ℒ(H) = {L(a)|a eH/H× is studied, where L(a) =ka has a factorization into irreducibles of lengthk.
Abstract: LetH be a semigroup with divisor theory and finite divisor class groupG such that every class contains a prime divisor (e.g.H the multiplicative semigroup of the ring of integers of an algebraic number field). For an elementa eH / H× letL(a) =ka has a factorization into irreducibles of lengthk}. In this paper the system ℒ(H) = {L(a)|a eH / H× is studied.

22 citations


Patent
Masayuki Kaneda1
19 Jan 1990
TL;DR: In this article, a divider for dividing a dividend by a divisor to calculate a quotient and a remainder, the divisors being a natural number which is a constant, each of the dividend, the quotient, and the remainder being an integer which is not less than zero, comparing circuits compare the dividend with first through N-th predetermined constants.
Abstract: In a divider for dividing a dividend by a divisor to calculate a quotient and a remainder, the divisor being a natural number which is a constant, each of the dividend, the quotient, and the remainder being an integer which is not less than zero, first through N-th comparing circuits compare the dividend with first through N-th predetermined constants. An n-th predetermined constant is equal to n times as large as the divisor, where n is variable between 1 and N, both inclusive. The first through the N-th comparing circuit produce first through N-th comparison result signals. A decoder decodes a combination of the first through the N-th comparison result signals into first and second partial decoded signals. The first partial decoded signal is equal to the quotient. The second partial decoded signal is equal to lower bits of a product of the quotient and the divisor. A subtracter subtracts the second partial decoded signal from lower bits of the dividend to produce the remainder.

20 citations


Proceedings Article
01 Jan 1990
TL;DR: The (n, k) pseudocyclic maximum-distance-separable (MDS) codes modulo (x/sup n/-a) over GF(q) are considered in this paper.
Abstract: The (n, k) pseudocyclic maximum-distance-separable (MDS) codes modulo (x/sup n/-a) over GF(q) are considered. Suppose that n is a divisor of q+1. If n is odd, pseudocyclic MDS codes exist for all k. However, if n is even, nontrivial pseudocyclic MDS codes exist for odd k (but not for even k) if a is a quadratic residue in GF(q), and they exist for even k (but not for odd k) if a is not a quadratic residue in GF(q). Also considered is the case when n is a divisor of q-1, and it is shown that pseudocyclic MDS codes exist if and only if the multiplicative order of a divides (q-1)/n, and that when this condition is satisfied, such codes exist for all k. If the condition is not satisfied, every pseudocyclic code of length n is the result of interleaving a shorter pseudocyclic code. >

19 citations


Journal ArticleDOI
TL;DR: In this paper, the notions of unitary divisor and biunitary divisors are extended in a natural fashion to give k-ary divi-sors, for any natural number k. The infinitary divi sors of an integer are described in full, and applications to the classical perfect and amicable numbers and aliquot sequences are given.
Abstract: The notions of unitary divisor and biunitary divisor are extended in a natural fashion to give k-ary divisors, for any natural number k. We show that we may sensibly allow k to increase indefinitely, and this leads to infinitary divisors. The infinitary divisors of an integer are described in full, and applications to the obvious analogues of the classical perfect and amicable numbers and aliquot sequences are given.

16 citations


Patent
07 Mar 1990
TL;DR: In this article, a method for performing floating point divide operations in 2-bit, non-restoring iterations is presented, wherein multiples of the divisor are formed by selective gating of one or more representations of the Divisor into a single 3-input adder circuit, to calculate the partial quotients and subsequent partial dividends.
Abstract: Apparatus and method for performing floating point divide operations in 2-bit, non-restoring iterations, wherein multiples of the divisor are formed by selective gating of one or more representations of the divisor into a single 3-input adder circuit, to calculate the partial quotients and subsequent partial dividends. The apparatus produces, without the need of separate holding registers, the zero, 1/2, 3/4, 1 and 3/2 multiples of the divisor.

11 citations



Book ChapterDOI
05 Nov 1990
TL;DR: A non linear code Γ(q, X, G, n, χ) on an alphabet with n+1 letters is defined, and the parameters of this code are computed through the consideration of some character sums.
Abstract: Let q be a power of a prime number, Fq the finite field with q elements, n an integer dividing q−1, n≥2, and χ a character of order n of the multiplicative group F*q. If X is an algebraic curve defined over Fq and if G is a divisor on X, we define a non linear code Γ(q, X, G, n, χ) on an alphabet with n+1 letters. We compute the parameters of this code, through the consideration of some character sums.

Journal ArticleDOI
TL;DR: In this article, the Veronese map is used to obtain the defect of general divisors for a set of Fermat curves with respect to a homogeneous coordinate system.
Abstract: This is a sequel to the paper [Si2-1 in whichwe introduced the use ofmeromorphic connections to handle nonequidimensional value distribution theory. The meromorphic connection is chosen so that the divisor has zero second fundamental form with respect to the meromorphic connection. When we have more than one divisor, they must have zero second fundamental form with respect to the same meromorphic connection. Such a condition is so stringent that it is difficult to find examples to which the method can be applied and which cannot be handled by other means. One example is a collection of Fermat curves in P2 of the form aowg + atw + a2wg 0 for the same homogeneous coordinate system [Wo, wt, w2]. Shift’man I-Sh2] told me that for such a collection of Fermat curves defect relations can be obtained by using a technique of H. Cartan [C2] (see 9), whereas the general case of allowing Fermat curves with respect to different homogeneous coordinates cannot be handled by any of the known methods. The only known result on the defect of general divisors is obtained by using the Veronese map and is given in [Shl] in the following form. Let f: C Pn be a holomorphic curve such that f(C) is not contained in any algebraic hypersurface in Pn. Let {Sj} be a collection of algebraic hypersurfaces of degree d in P. The sum of the defects of f for the

Book ChapterDOI
01 Jan 1990
TL;DR: In this paper, the action of Hecke operators T n (n ∈ IN) and their adjoint operators T* n, on Eisenstein series belonging to the group Γ 0(N) and having integral weight k > 2 and arbitrary character χ modulo N.
Abstract: In this paper we consider the action of Hecke operators T n (n ∈ IN), and their adjoint operators T* n , on Eisenstein series belonging to the group Γ0(N) and having integral weight k > 2 and arbitrary character χ modulo N. It is shown that the space ɛ k (x) spanned by these Eisenstein series splits up into a number of subspaces ɛ k (x,t)> where t is a divisor of N, each being invariant under the operators T n and T* n with (n, N) = 1. If x is a primitive character modulo N, this holds also for T n with (n, N) > 1, but this need not be true for general x modulo N. A basis of modular forms that are eigenfunctions for T n with (n, N) = 1 is constructed for each appropriate t and explicit evaluations of G L \T n are given for each Eisenstein series G L (L ∈ Γ(l)) and any positive integer n prime to N, or any n that is a prime divisor of N, the results being particularly simple when N is squarefree. The corresponding results for G L \T* n when (n, N) > 1 will be given in a subsequent paper.

Journal ArticleDOI
TL;DR: In this paper, it was shown that the number of infinitary harmonic numbers not exceeding x is less than 2.2 x 1/2 2 (1+e)log x/log log x for any e > 0 and x > n 0 (e).
Abstract: The infinitary divisors of a natural number n are the products of its divisors of the , where p y is an exact prime-power divisor of n and (where y α = 0 or 1) is the binary representation of y . Infinitary harmonic numbers are those for which the infinitary divisors have integer harmonic mean. One of the results in this paper is that the number of infinitary harmonic numbers not exceeding x is less than 2.2 x 1/2 2 (1+e)log x/log log x for any e > 0 and x > n 0 (e). A corollary is that the set of infinitary perfect numbers (numbers n whose proper infinitary divisors sum to n ) has density zero.

Journal ArticleDOI
TL;DR: A necessary and sufficient condition for a matrix to be stochastically similar to a matrix with equal diagonal elements is obtained Aand B are called Stochastically similar if B=SAS − 1 where S is quasi-stochastic i.e., all row sums of.S are I.
Abstract: A necessary and sufficient condition for a matrix to be stochastically similar to a matrix with equal diagonal elements is obtained Aand B are called Stochastically similar if B=SAS − 1 where S is quasi-stochastic i.e., all row sums of .S are I. An inverse elementary divisor problem for quasi-stochastic matrices is also considered.

Patent
01 Oct 1990
TL;DR: An improved electronic computer which can produce a quotient/remainder calculation is presented in this paper, where the first and second memories for storing respectively a dividend and a divisor which are input for execution of division are used.
Abstract: An improved electronic computer which can produce a quotient/remainder calculation The computer has first and second memories for storing respectively a dividend and a divisor which are input for execution of division A quotient/remainder calculation is carried out using the dividend and divisor stored respectively in the first and second memories The computer further includes third and fourth memories for storing respectively a quotient and a remainder which are obtained in the division calculation A detector is provided for detecting which of the contents of the third memory or the contents of the fourth memory are displayed The contents of the third memory or the contents of the fourth memory which have not been detected as being displayed are displayed in response to a predetermined input operation

Journal ArticleDOI
TL;DR: For the class of convolutions g(x) ≔ Σ n ≤ z α(n)n a f( x n ), where f is a periodic function of period 1 satisfying a Kubert identity of order l > 1, where a ≤ −1, and where α( n) = 1 or the Moebius function μ(n).

Patent
16 Feb 1990
TL;DR: An optimized division circuit and a method of implementing the circuit includes the steps of determining a Z-Z plot relationship which represents a relationship between a first divisor ratio proportional to a range of previously determined remainder values divided by the divisors and a second divisore ratio equal to a series of succeeding remainder values dividing by the dividers as discussed by the authors.
Abstract: An optimized division circuit and a method of implementing the circuit includes the steps of determining a Z-Z plot relationship which represents a relationship between a first divisor ratio proportional to a range of previously determined remainder values divided by the divisor and a second divisor ratio equal to a range of succeeding remainder values divided by the divisor. A complete look-up table is automatically built from the Z-Z plot relationship which includes, for each different valid combination of divisor and next remainder values, either a corresponding quotient digit or a DON'T CARE indicator. A state value, used in the logical implementation of the circuit, is then assigned to each different quotient digit. The circuit includes a divisor multiple formation circuit, a quotient determining circuit and a quotient assimilation circuit. The divisor multiple formation circuit includes a divisor multiple multiplexer. The quotient determining circuit includes a next partial remainder determining circuit and a next quotient digit selection circuit. The quotient assimilation circuit subtracts negative values of quotient digits from positive values to determine a final quotient value.

Patent
24 Apr 1990
TL;DR: In this article, the upper five bits of a divisor and the upper six bits of the partial remainder of a partial remainder at present are decided by the relation of the divisors and the partial rest at present.
Abstract: PURPOSE: To save time by deciding the upper five bits of a divisor and the upper six bits of a partial remainder at present and deciding the selection of the redundant pair of quotient bits by the relation of the divisor and the partial remainder at present. CONSTITUTION: The divisor D is loaded into a register 5 and the initial partial remainder of division is loaded into the register 10. The register 10 stores the succeeding partial remainder in a redundant form of the carry output and the sum output of a carry preservation adder. However, a divided is loaded into the register 10 in a non-redundant form. The correct quotient bit generated by respective radixes -4 division is decided and selection logic is executed. The quotient bit of radix 4 division is selected from -2-+2 and the quotient bit for the next partial remainder is selected by using the divisor of five bits and the partial remainder of six bits. The addition of a negative quotient and a positive quotient is performed 'during a flight' and a complete quotient is identified. Thus, additional time is saved.


Patent
13 Mar 1990
TL;DR: In this article, the most significant bit number of the original divisor is inspected and whether or not the conversion of the divisors is required is decided, and when the conversion is not required, '1' is impressed to the control terminal of the MX 62 and the original is sent to a divider.
Abstract: PURPOSE: To quickly convert a divisor at a low cost so as to make faster division possible by converting the divisor to a certain value within a prescribed selection range before the division and converting a dividend by the same rate. CONSTITUTION: An original divisor DR is sent to a carrier selection adder 60 and a multiplexer(MX) 62, the most significant bit number of the original divisor is inspected and whether or not the conversion of the divisor is required is decided. When the conversion is not required, '1' is impressed to the control terminal of the MX 62 and the original divisor is sent to a divider. When the original divisor is not present in a desired range, the output of the MX 62 becomes the output of the adder 60 and the output of the adder 60, that is the selection range, becomes 1.5-2.0. One of DR/4 and DR/2 is added to the MX 64 depending on the size of the original divisor DR and a conversion divisor TDR is formed. The conversion the same as the conversion performed to the divisor is also performed to the dividend.

01 Jan 1990
TL;DR: In this paper, a number of modifications of Stefanelli's division and reciprocal algorithms are suggested, based on the redundant representation of the dividend and allow for both an increase to the speed and a decrease to the hardware cost of division and reciprocation devices.
Abstract: A number of modifications of Stefanelli's division and reciprocal algorithms is suggested. These modifications are based on the redundant representation of the dividend and allow for both an increase to the speed and a decrease to the hardware cost of division and reciprocal devices based on Stefanelli's algorithm. Stefanelli's division algorithm (1) is based on the idea of using the redundant set of the allowed quotient digits. The calculation of the binary quotient Q = C / A using Stefanelli's division algorithm consists of two steps. First, the quotient is formulated as a binary number: Q = q 0 2 0 + q 1 2 -1 + q 2 2 -2 + … + q m-1 2 -(m-1) using the redundant binary digits qk (0 ≤ k ≤ m-1). The redundant digits qk assume either positive or negative integer values to satisfy the following system of algebraic equations: q0 = 1 q1 = c 2 - a 2q0 q2 = c 3 - a 2q1 - a 3q0 … qm-1 = c m - a 2qm-2 - a 3qm-3 - …- a mq0. (1) Equations (1) are obtained by representing the multiplication A · Q as a partial product array and assigning the sums of the partial product array elements with equal binary weights to the corresponding binary digits of the dividend C. Divisor A = 0.a 1a2…a n and dividend C = 0.c 1c2 …c n are assumed to be positive and normalized binary fractions. To calculate the quotient with the precision equal to the precision of A and C, the number m of the redundant quotient digits has to be greater than the number n of binary digits of the dividend and the divisor. The binary digits cn+1 , c n+2 , …c m-1 of the dividend and the binary digits an+1 , a n+2 , …a m-1 of the divisor in (1) are assumed to be equal to zero.

Patent
24 Aug 1990
TL;DR: In this paper, the authors propose to execute 63-bit integer type division without using a floating decimal point instruction by executing sorting by means of the number of the effective digits of divisors, in the case of the divisor at >= n bits.
Abstract: PURPOSE:To execute 63-bit integer type division without using a floating decimal point instruction by executing sorting by means of the number of the effective digits of divisors, in the case of the divisor at >= n bits, shifting a divident and the divisor, obtaining a value whose number of the effective digits is <=n bits, and obtaining a quoitient CONSTITUTION:A computer 10 has plural registers respectively holding data of n bits, and holds a binary integer division instruction executing mechanism set in the registers When a divident X is divided by a divisor Y so that the quoitient may be expressed in the range of 2n bits by the computer 10 whose one word consists of n bits, first the number of the effective digits is obtained By the number of the effective digits, a division error or a clear quoitient can be obtained Further by paying attention to the number of the effective digits of the divisor Y, sorting is executed, the division instruction by means of the divisor of n bitz is used, and the division is executed Thus the 63-bit integer type division in a FORTRAN program, etc, can be executed without using the floating decimal point instruction

Proceedings ArticleDOI
01 Apr 1990
TL;DR: An algorithm for integer division that is based on the periodic nature of reciprocals of odd integers is presented and an approach to implementation using systolic arrays is presented.
Abstract: An algorithm for integer division that is based on the periodic nature of reciprocals of odd integers is presented. The method consists of the determination of the value in one period of the reciprocal of odd divisor d (referred to as the B-sequence), multiplication of the dividend D by this value to produce D', and the division of D' by 2/sup n/-1, where n is the length of the B-sequence. The generation of the B-sequence and division by 2/sup n/-1 are addressed in detail. Proofs of correctness are provided for both processes. The algorithms are suitable for VLSI implementation. An approach to implementation using systolic arrays is presented. >

Patent
17 Apr 1990
TL;DR: In this paper, a method to reduce the number of times of memory access and to accelerate a decimal division processing at an office computer level by providing a means to obtain the estimation of a quotient, an addition means, an add/subtraction means, and a correction means in case of generating a negative value in a division result was proposed.
Abstract: PURPOSE:To reduce the number of times of memory access and to accelerate a decimal division processing at an office computer level economically by providing a means to obtain the estimation of a quotient, an addition means, an addition/subtraction means, and a correction means in case of generating a negative value in a division result. CONSTITUTION:The plural high-order digits of a dividend are compared with the plural high- order digits of a divisor by using the subtracter 11 of the means 1 to obtain the estimation of the quotient, and when it is dividend < divisor, the plural high-order digits of the divisor are shifted by one digit, then, they are subtracted from the plural high-order digits of the dividend. And such operation is repeated until a subtraction result shows a negative number, then, the estimated quotient(C) of the quotient can be obtained. Next, the arithmetic operation of (divisor X quotient (C)) is performed by using an adder 21, and after that, the verification of (dividend - (divisor X quotient C)) is performed by using an adder/subtractor 31. When the negative number is obtained as a result, a subtraction result is restored to a positive number by adding the divisor, and a number(estimated number of quotient - 1) is set as a new quotient, and a true quotient and a remainder can be found by performing such arithmetic operation repeatedly. In such a way, it is possible to accelerate the decimal division processing economically at the office computer level by reducing the number of times of access.