Showing papers on "Divisor published in 1994"

The mean square of the error term for the fourth power moment of the zeta-function

Abstract: We prove that /J E2(t) 2 dt« T 2 log c T, where E2(T) denotes the error term in the asymptotic formula for fo\£(k + 'Of* dt\ the proof depends on the second author's explicit formula for a modified version of the latter integral. Several related results are also proved, including the analogue of the above result for the binary additive divisor problem.

Method and system for performing floating-point division using selected approximation values

Abstract: A method and system for performing floating-point division of a dividend by a divisor within a floating-point unit having multiply and add functions are disclosed. In performing floating-point division, a quotient having a mantissa is produced. The method uses an approximation based on a linear approximation stored within a first table. The first approximation approximates two divided by the divisor. A second table value is also selected from the table lookup. The second table value approximates the reciprocal of the divisor squared. Both the first and second table values operate as linear correction terms. Also according to the present invention, a method and system are disclosed that perform an early exit check during the division operation to confirm whether the resultant quotient has an acceptable accuracy and if the accuracy is unacceptable, then perform a rounding correction based upon a given rounding boundary.

Method and apparatus for overriding quotient prediction in floating point divider information processing systems

Abstract: A hardware implementation for quotient prediction overrule in high speed higher radix SRT division computation circuits. A quotient prediction PLA receives a data segment of the divisor, together with data values from one or more multiplexors. One multiplexor receives as input a partial remainder from a carry-propagate-adder (CPA), which CPA combines into nonredundant form redundant sum and carry vectors derived from a carry-save-adder (CSA) which determines the next partial remainder. The PLA evaluates the next most significant bits (MSBs) of the divisor together with the next MSBs of the next (unlatched) partial remainder to determine the next quotient bits. The quotient estimates given by the quotient prediction PLA are then transmitted to both quotient and remainder generation logic, including a divisior multiple gating multiplexor. The quotient estimate signals together with a sign signal determine the divisor multiple to be used in the next division iteration during the next clock cycle. When ordinary quotient prediction is to be overridden, the state machine sends an appropriate control signal one clock cycle early, whereafter a divisor multiple of zero is combined with the current partial remainder. A divisor multiple of zero causes a previously derived remainder to be recycled unchanged in the remainder datapath, thereby permitting multicomponent data values (i.e., quotient and remainder) to be sequentially routed along a shared datapath and single output bus. Other non zero divisor multiples can be used to force particular mathematical operations at chosen times. By determining the next quotient bits and the divisor multiple in the current clock cycle the divisor multiple before the the speedpath of the SRT division implementation is substantially improved.

Iterative division apparatus, system and method forming plural quotient bits per iteration

Abstract: An iterative division technique which forms plural quotient bits per iteration. A data processing apparatus (1100) includes a first register (1101) storing the divisor, a second register initially storing the numerator (1103), a plurality of full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) and an equal number of negative detectors (1122, 1123, 1124, 1125, 1126, 1127, 1128), and a loop counter (1131). Initially the full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) compute each integral product of the divisor not a power of 2 between 1 and 2 M -1 inclusive, where M is the number of quotient bits to be computed. These factors are stored in latches (1144, 1146, 1147, 1148). The full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) next subtract in parallel each integral product of the divisor between 1 and 2 M -1 inclusive from the most significant bits of the numerator. Negative detectors (1122, 1123, 1124, 1125, 1126, 1127, 1128) connected to each full adder (1112, 1113, 1114, 1115, 1116, 1117, 1118) indicate the first non-negative difference, which determines plural bits of the quotient and a partial remainder. This process is repeated with partial remainder left shifted M places employed as the numerator a number of iterations based upon the size of the numbers employed and the number of bits per iteration. For signed division the sign of the quotient is set as the exclusive OR of the detected (1102, 1104) respective signs of the numerator and the divisor.

Standard Bundles on a Hilbert Scheme of Points on a Surface

Abstract: Let S be a smooth irreducible algebraic surface over ℂ, H d a Hilbert scheme of 0-dimensional subschemes of length d in S, dim H d = 2d, and Z d ⊂ S × H d a universal family with natural projections \(S\xleftarrow{{{\tau _d}}}{Z_d}\xrightarrow{{{\pi _d}}}{H_d}\). Fix an arbitrary divisor D on S and denote \(\varepsilon _D^d = {\pi _{d*}}\tau _d^*{O_S}(D)\). Since π d is a flat finite morphism of degree d, the sheaf e D d is in fact the vector bundle of rank d over H d . We call e D d the standard vector bundle over H d . The problem of computation of its Segre classes is connected with a number of questions of enumerative geometry. In recent times it has got applications to the description of the smooth structure of the 4-manifold underlying S — see [10].

Square Roots mod p

Abstract: SUMMARYWe have proved the following: given an odd prime p, chosen at random, and a random quadratic residue y (mod p), the square roots of y (mod p) are, in ⅔ of all cases, the values of x given by Equation (3), where C is the largest odd divisor of p - 1. (It is also true that we can generate the square roots from these starting values in other cases, as Shanks shows.)

Normal and Self-dual Normal Bases from Factorization of$c x^{q+1} + d x^{q} - ax - b$

Abstract: The present paper is interested in a family of normal bases, considered by Sidel'nikov [Math. USSR-Sb., 61 (1988), pp.~485--494], with the property that all the elements in a basis can be obtained from one element by repeatedly applying to it a linear fractional function of the form $\varphi(x) = (ax+b)/(cx+d)$, $a,b,c,d \in F_q$. Sidel'nikov proved that the products for such a basis $\{\alpha_i\}$ are of the form $\alpha_i \alpha_j$ $ = e_{i-j} \alpha_i + e_{j-i} \alpha_j + \gamma$, $i eq j$, where $e_k, \gamma \in F_q$. It is shown that every such basis can be formed by the roots of an irreducible factor of $F(x) = c x^{q+1} + d x^q - ax - b$. The following are constructed: (a) a normal basis of $F_{q^n}$ over $F_q$ with complexity at most $3n-2$ for each divisor $n$ of $q-1$ and for $n = p$, where $p$ is the characteristic of $F_q$; (b) a self-dual normal basis of $F_{q^n}$ over $F_q$ for $n=p$ and for each odd divisor $n$ of $q-1$ or $q+1$. When $n=p$, the self-dual normal basis constructed of $F_{q^p}$ over $F_q$ also has complexity at most $3p-2$. In all cases, the irreducible polynomials and the multiplication tables are given explicitly.

Systematic computations on Mertens' conjecture and Dirichlet's divisor problem by vectorized sieving

Abstract: In this paper we present two vectorized numerical sieve algorithms for the number theoretical functions μ(n) and τ (n). These sieve algorithms are generalizations of Eratosthenes’ sieve for finding prime numbers. We show algorithms for fast systematic computations on Mertens’ conjecture and Dirichlet’s divisor problem. We have implemented the algorithm for Mertens’ conjecture on a Cray C90 and performed a systematic computation of extremes of M(x)/ √ x up to 10. We established the bounds −0.513 < M(x)/ √ x < 0.571, valid for 200 < x ≤ 10.

Non‐trivial Linear Systems on Smooth Plane Curves

Abstract: Let $C$ be a smooth plane curve of degree $d$ defined over an algebraically closed field $k$. A base point free complete very special linear system $g^r_n$ on $C$ is trivial if there exists an integer $m\ge 0$ and an effective divisor $E$ on $C$ of degree $md-n$ such that $g^r_n=|mg^2_d-E|$ and $r=(m^2+3m)/2-(md-n)$. In this paper, we prove the following: Theorem Let $g^r_n$ be a base point free very special non-trivial complete linear system on $C$. Write $r=(x+1)(x+2)/2-b$ with $x, b$ integers satisfying $x\ge 1, 0\le b \le x$. Then $n\ge n(r):=(d-3)(x+3)-b$. Moreover, this inequality is best possible.

Boundedness and $K^2$ for log surfaces

Abstract: Let $\epsilon, C$ be two positive real numbers, and $\mathcal C \subset \mathbb R$ be a DCC (descending chain condition) set. Let $(X, B = \sum b_j B_j)$ denote a projective surface with an $\mathbb R$-divisor. Then (1) The class $\{X\}$ of surfaces for which there exists a divisor $B$ such that $(X,B)$ is $\epsilon$-log terminal and $-(K_X + B)$ is nef (excluding only those for which at the same time $K_X\equiv 0$, $B=0$, and $X$ has at worst Du Val singularities), is bounded. (2) The set $\{(K_X + B)^2\}$ of squares for the semi log canonical pairs $(X, B)$ with ample $K_X + B$ and $b_j \in \mathcal C$, is a DCC set. (3) The class $\{(X,B)\}$ of pairs such that $(X, B)$ is semi log canonical, $K_X + B$ is ample, $(K_X + B)^2 = C$ and $b_j \in \mathcal C$, is bounded.

Divider circuit which calculates an integral quotient of an integral divisor

Abstract: A divider circuit which calculates an integral quotient of an integral divisor and an integral dividend. A first multiplication unit calculates products of the integral divisor and all n-bit pattern values of an n-bit pattern, where n is a predetermined number and the n-bit pattern values respectively correspond to the calculated products. A calculation unit sets the integral dividend as an initial value of an operational integer, specifies a product among the products calculated by the first multiplication unit of which the subordinate n-bit value is equal to the subordinate n-bit value of the operational integer, and calculates a difference of the operational integer and the specified product. When the difference calculated by the calculation unit is not zero, an activation unit sets a new operational integer by canceling the subordinate n bits of the difference and causes the calculation unit to set the integral dividend, specify a product and calculate a difference based on the new operational integer. An output unit successively takes n-bit pattern values respectively corresponding to products specified by the calculation unit, and outputs these n-bit pattern values as the quotient when the difference calculated by the calculation unit is zero.

On the frequencies of large values of divisor functions

Abstract: where ζ is the Riemann zeta-function and s > 1. It follows from (1.2) that for any positive integer k, dk(n) is the number of ordered k-tuples (n1, . . . , nk) of positive integers such that n1 . . . nk = n. In particular, d2(n) is the number of distinct positive divisors of n. For real z, x, w, define ∆z(x,w) = #{n ≤ x : dz(n) > w}, (1.3) ∆z(x,w) = #{n ≤ x : dz(n) ≥ w}, (1.4) where #B means the number of members of the finite set B (note that ∆z(x,w) ≤ ∆z(x,w)). Our main objective is to obtain good upper bounds for ∆z(x,w) and good lower bounds for ∆z(x,w) when z > 1, x is large, and logw is larger than the normal order of log dz(n) for n ≤ x. Before stating our results, we must specify some notation. Unless otherwise stated, r, t, u, v, w, x, y, z, α, β, δ, e denote real numbers, with e > 0. (For consistency with the notation of some earlier authors, we shall let y denote a positive integer in Section 3.) We use γ to denote Euler’s constant, while k, m, n represent positive integers and p is a (positive) prime number. If a is a nonnegative integer, p ‖n means that p |n and

CMOS Implementation of a hybrid radix-4 divider

Abstract: A 1.2 ?m CMOS combinational implementation of a new hybrid radix-4 division algorithm is presented. The algorithm is named hybrid because the dividend, the quotient, and the remainder are represented using the signed-digit-set {2,1,0,1,2}; while the divisor is represented using the conventional digit-set {0, 1, 2, 3}. The divider requires the divisor Y to be pre-scaled to the range 1 ? Y ≪ 1 + 118. For 16 bit accuracy, it is about 50 % less expensive but 12 % slower than a corresponding radix-2 divider.

J-Diviseurs Topologiques de Zéro Dans Une Algèbre de Jordan N.C. Normée

Abstract: Let A be a normed non commutative Jordan K-algebra (K = R or C). An element a ∈ A is said to be a J-topological divisor of zero in A, is there is a sequence {x n } in A, ‖x n ‖= 1 such that U a(x n ) → 0 (U a(x) = axa + (xa)a − xa 2). In this work we prove: if D is a normed, Jordan non commutative K-algebra ≠ 0, with no nonzero J-topological divisor of zero, then D is a division algebra, which is isomorphic to C when D is complex, and a flexible quadratic algebra when D is real.

Method and apparatus for integer division.

Abstract: An apparatus for dividing an integer by another integer to produce the quotient that is an integer. This apparatus aligns the dividend and the divisor by aligning the extreme right bit of the divisor with the bit position M of the dividend. The integer value represented by the dividend bit aligned with the divisor among the bits of the dividend is compared with the divisor. The quotient bits at the positions corresponding to the dividend bit M and the dividend bit on the left side of the former are set to 0 in accordance with this comparison result. In the alignment state described above, the dividend is divided by the divisor in accordance with the comparison result so that the value of the quotient bits, which are not set to 0, among the quotient bits is generated.

Decimal dividing circuit

Abstract: PURPOSE:To attain an efficient arithmetic operation CONSTITUTION:A dividend register 1 stores a decimal dividend to be computed, a multiple register 2 stores one number which is one time, twice, four times, and eight times as large as a divisor to be computed, and a divisor register 3 stores a decimal divisor to be computed An adding and subtracting circuit 4 operates the addition and subtraction of the dividend data being the output 101 of the dividend register 1 and the multiple data of the divisor being the output 102 of the multiple register 2 A comparison circuit 5 compares the dividend data being the output 101 of the dividend register 1 with the divisor data being the output 103 of the divisor register 3 A storage circuit 6 stores the number which is one time, twice, four times, and eight times as large as the divisor to be computed calculated by using the adding and subtracting circuit 4 A division quotient calculating circuit 7 calculates a quotient based on the carry output 105 of the adding and subtracting circuit 4 and the compared result output 106 of the comparison circuit 5

Method and device for conducting division in data processor

Abstract: PURPOSE: To realize an integer/floating point division operation through the use of a single correction SRT divider in a data processor. CONSTITUTION: Floating point/integer division is executed on a normalized plus mantissa (a dividend and a divisor) by using SRT division. Integer division shares a part of a floating point circuit and the sequence of the operation is changed during an integer division operation. The SRT divider 30 executes a series of operations before and behind a repetitive loop and reconstructs the integer/divisor and the dividend for the expression of a data route that an SRT algorithm requests to the mantissa of a floating point. During a repetitive loop, a quotient bit is selected and it is used for generating an intermediate partial remainder. The quotient bit is inputted to a quotient register for accumulating a final quotient mantissa. A mantissa full adder is used for generating the final remainder.

Fixed decimal point dividing method

Abstract: PURPOSE:To perform fixed decimal point division at high speed similarly to integer division by shifting a divided to the side of an MSB by the bit number of a decimal part and obtaining the quotient and the remainder by performing integer division while regarding these components as integral data. CONSTITUTION:Concerning the divident and a divisor for which the format is L+2M bits, the M bits from the LSB are the decimal part and the L bits are expressed as an integral part in the fixed decimal point data, the divided is shifted to the side of an MSB by M bits, the integer division is performed while regarding this divided and the original divisor as the integral data, and the quotient is obtained while cutting off places less than the accuracy of the fixed decimal point. When the integer division is simply performed to the original divided and divisor without shifting the divided, the quotient less than the decimal point is cut off, and the quotient of the integer part alone is obtained. Since the integer division is performed after the divided is shifted by the bit (digit) number of the decimal part, the quotient is obtained while cutting off places less than the accuracy of the fixed decimal point of the format same as the divided and the divisor.

Device and method for division

Abstract: PURPOSE:To cope with optional divisors and dividends by providing a calculating means for obtaining the reciprocal of the divisor in a decimal number, a means for multiplying an arithmetic result and the dividend together and the means for deleting only the number of digits of the arithmetic result from multiplied result. CONSTITUTION:This device is provided with a filter circuit 101 for deleting the low- order bits of the dividend based on the filter value of a prime number resolver 102, the resolver 102 for obtaining the power of two from the inputted divisor, obtaining its exponent as the filter value to be inputted to the filter circuit 101, deleting only the value of the exponent of the power of two within the low-order bits of the inputted divisor and obtaining the remaining bits as the input value of a reciprocal computing element 103, the computing element 103 for obtaining the filter value in order to obtain a divisor result from the result of the multiplication for obtaining the reciprocal of a value inputted from the resolver 102 as a multiplier to be inputted to a multiplier 104, the multiplier 104 for multiplying the multiplier of the computing element 103 and the multiplicand of the filter circuit 101 together and the filter circuit 105 for deleting the low-order bits of the multiplied result of the multiplier 104 based arm the filter value of the computing element 103 and obtaining a divided result.

Square root arithmetic unit

Abstract: PURPOSE:To attain the high speed of the arithmetic operation of a square root by adding a correcting circuit to a divider, in an arithmetic unit which calculates the square root. CONSTITUTION:A divider 1 is equipped with a divisor register 12, partial remainder register 16, partial quotient predicting circuit 21, partial quotient correcting circuit 23, divisor multiple preparing circuit 19, and partial remainder arithmetic circuit 20, and the partial quotient of plural bits can be searched all at once. And also, this device is equipped with an initial value setting circuit 2 which predicts the value of the high-order digit of the square root from an operand, and sets it in the divisor register 12, divisor multiple correcting circuit 3 which adds the partial quotient predicted this time to a number twice as large as a quotient searched in the previous arithmetic cycle, and uses a value obtained by multiplying the value by the partial quotient predicted this time as a corrected divisor multiple, and divisor correcting circuit 4 which corrects the divisor of the divisor register by the partial quotient corrected by the partial quotient correcting circuit 23 in each arithmetic cycle.

Design of C-testable high-speed dividers

Abstract: This paper presents a design of a C-testable carry-free divider circuit and its test generation The divider circuit takes the dividend and divisor digits, in redundant binary form, as its inputs and produces the quotient and remainder digits, also in redundant binary form The circuit is fully testable with a test set of 72 test patterns irrespective of its bit size In order to easily generate the test patterns and the corresponding control signals, a graph labeling scheme is employed to derive a set of simple labels for the dividend, the divisor the quotient, the remainder, and the control signals