Topic
Divisor
About: Divisor is a research topic. Over the lifetime, 2462 publications have been published within this topic receiving 21394 citations. The topic is also known as: factor & submultiple.
Papers published on a yearly basis
Papers
More filters
•
25 Mar 2010TL;DR: A clock divider and method of operating the same can be found in this article, where the clock dividers can be configured to divide clock frequencies by both even and odd divisors.
Abstract: A clock divider and method of operating the same. In various embodiments, the clock divider may be configured to divide clock frequencies by both even and odd divisors. The divisor may be an integer that is represented by an N-bit value, and the clock divider may be programmable by writing the N-bit value to a register. The divisor may be even or odd. During operation, the clock divider may decrement a counter down from an initial value (derived from the N-bit value representing the divisor) to a trigger value. When the trigger value is detected, the clock divider may cause the output clock to toggle. The trigger value may depend on whether the divisor is even or odd. The clock divider may be re-programmed during operation by writing a new N-bit value into the register. Re-programming may include changing the divisor from an even value to an odd value.
5 citations
••
01 May 1995TL;DR: A C-testable carry-free divider circuit design and its test generation is presented, using a graph labelling scheme to derive a set of simple labels for the dividend, the divisor, the quotient, the remainder and the control signals.
Abstract: Presents a C-testable carry-free divider circuit design and its test generation. The divider circuit takes the dividend digits, in redundant binary form, and divisor digits, in binary form, as its inputs and produces the quotient and remainder digits, also in redundant binary form. The circuit is fully testable with a test set of 72 test patterns irrespective of its bit size. To generate the test patterns and the corresponding control signals easily, a graph labelling scheme is employed to derive a set of simple labels for the dividend, the divisor, the quotient, the remainder and the control signals.
5 citations
•
TL;DR: In this paper, the Seshadri constant of the anti-canonical divisor at some smooth point is shown to be greater than a constant in the dimension of a Fano variety.
Abstract: We prove that a Fano variety (with arbitrary singularities) of dimension $n$ in positive characteristic is isomorphic to $\mathbb{P}^n$ if the Seshadri constant of the anti-canonical divisor at some smooth point is greater than $n$ and classify Fano varieties whose anti-canonical divisors have Seshadri constants $n$. In characteristic $p>5$ and dimension $3$, we also show that Fano varieties $X$ with Seshadri constants $\epsilon(-K_X,x)>2+\epsilon$ at some smooth point $x\in X$ (for some fixed $\epsilon>0$) have bounded anti-canonical degrees.
5 citations
•
21 Jan 1999TL;DR: In this paper, a polynominal comprising powers of the basic unit of computer operation is used to determine integer remainders, and no shift operation is required as opposed to the conventional method, which can be determined simply by addition and subtraction.
Abstract: An integer Z101 is divided by another integer I102 to determine the remainder R109 The integer I102 is expressed by a polynominal comprising powers of the basic unit of computer operation By limiting the divisor according to the basic unit of computer operation, no shift operation is required as opposed to the conventional method, and remainders can thus be determined simply by addition and subtraction This allows code size to be compact, resulting in high-speed determination of integer remainders
5 citations
••
TL;DR: The proposed divisor architecture is able to achieve a delay of order, similar to the solution presented by Takagi, and there is a saving of some 40% in the number of gates and a gain in terms of power saving when compared with the state of the art.
Abstract: Division is the highest latency arithmetic operation in present digital architectures and high-performance computing systems; as such drives the demand for efficient hardware division units. Accordingly, this paper proposes a novel architecture for a nonrestoring divisor based on the radix-2 signed-digit (SD2) representation. This notation has been chosen to achieve fast computation, as proposed by Avizienis (IEEE Transactions on Electronic Computers, vol. EC-10, no. 3, pp. 389-400, Sep. 1961), but the architecture presented in this paper, due to its structure and the definition of the cell implementing its architecture, saves area as well. The proposed divisor architecture is able to achieve a delay of order , similar to the solution presented by Takagi (IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, E89-A, no. 10, pp. 2874-2881, 2006) being considered as the state of the art, instead of other solutions that give growth. This is in line with the fact that even if our carry-chains have a less impact on the circuit the basic cell is larger compared to the one proposed by Takagi Our cells are larger that those proposed in literature, considering them as single circuit, but considering the overall structure there is a saving of some 40% in the number of gates and a gain of 55% in terms of power saving when compared with the state of the art.
5 citations