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Divisor

About: Divisor is a research topic. Over the lifetime, 2462 publications have been published within this topic receiving 21394 citations. The topic is also known as: factor & submultiple.


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Posted Content
TL;DR: In this article, it was shown that the Mobius function exhibits cancellation on shifted primes, that is, for any fixed shift h > 0, provided that h = 0.
Abstract: It is a folklore conjecture that the Mobius function exhibits cancellation on shifted primes; that is, $\sum_{p\le X}\mu(p+h) \ = \ o(\pi(X))$ as $X\to\infty$ for any fixed shift $h>0$. We prove the conjecture on average for shifts $h\le H$, provided $\log H/\log\log X\to\infty$. We also obtain results for shifts of prime $k$-tuples, and for higher correlations of Mobius with von Mangoldt and divisor functions. Our argument combines sieve methods with a refinement of Matomaki, Radziwill, and Tao's work on an averaged form of Chowla's conjecture.

4 citations

Posted Content
TL;DR: In this paper, the authors studied the codimension two locus H in A_g consisting of principally polarized abelian varieties whose theta divisor has a singularity that is not an ordinary double point.
Abstract: We study the codimension two locus H in A_g consisting of principally polarized abelian varieties whose theta divisor has a singularity that is not an ordinary double point. We compute the class of H in A_g for every g. For g=4, this turns out to be the locus of Jacobians with a vanishing theta-null. For g=5, via the Prym map we show that H in A_5 has two components, both unirational, which we completely describe. This gives a geometric classification of 5-dimensional ppav whose theta-divisor has a quadratic singularity of non-maximal rank. We then determine the slope of the effective cone of A_5 and show that the component N_0' of the Andreotti-Mayer divisor has minimal slope 54/7. Furthermore, the Iitaka dimension of the linear system corresponding to N_0' is equal to zero.

4 citations

Patent
22 Sep 2005
TL;DR: In this paper, the authors provide an apparatus and a method for achieving a safe and high speed operation in hyperelliptic encryption processing, where a base point D in scalar multiplication processing based on a hypelliptic curve encryption and data calculated beforehand in a window method as an execution algorithm of the scaler multiplication are set as a degenerate divisor.
Abstract: PROBLEM TO BE SOLVED: To provide an apparatus and a method for achieving a safe and high speed operation in hyperelliptic encryption processing SOLUTION: A base point D in scalar multiplication processing based on a hyperelliptic curve encryption and data calculated beforehand in a window method as an execution algorithm of the scaler multiplication are set as a degenerate divisor which has a smaller weight than a genus g of the hyperelliptic curve and adding processing in the scaler multiplication processing to which the window method is applied is executed by the adding processing of the degenerate divisor + a non-degenerate divisor Thereby, the safe and high speed operation in which tolerance to SPA analysis or the like which is one mode of key analysis in the operation is not impaired, is realized COPYRIGHT: (C)2006,JPO&NCIPI

4 citations

Journal ArticleDOI
01 Mar 2000
TL;DR: A high-speed 64b/32b integer divider using the digit-recurrence division method and the on-the-fly conversion algorithm, is presented and a fast normaliser is used as the preprocessor of the proposedinteger divider.
Abstract: A high-speed 64b/32b integer divider using the digit-recurrence division method and the on-the-fly conversion algorithm, is presented. A fast normaliser is used as the preprocessor of the proposed integer divider. To reduce maximum division time, the proposed divider uses radix-4/2 division, instead of the traditional radix-2 division. On-the-fly quotient adjustment is also realised in the converter module of the divider. The entire design is written in the Verilog hardware description language using the COMPASS 0.6 /spl mu/m 1P3M cell library (V3.0), and then synthesised by SYNOPSYS. Finally a real chip is fabricated and fully tested. The test results are very impressive. A performance evaluation of a 128b/64b signed integer divider using the same design methodology is also included in this study.

4 citations

Posted Content
TL;DR: In this article, the authors considered the case k = 1 and showed bounds for the irrationality measure of ${\rm e}^{2\pi m} and for the partial quotients in its continued fraction expansion.
Abstract: Sums of the form $\sum_{n\le x}E^k(n) (k\in{\bf N}$ fixed) are investigated, where $$ E(T) = \int_0^T|\zeta(1/2+it)|^2 dt - T\Bigl(\log {T\over2\pi} + 2\gamma -1\Bigr)$$ is the error term in the mean square formula for $|\zeta(1/2+it)|$. The emphasis is on the case k=1, which is more difficult than the corresponding sum for the divisor problem. The analysis requires bounds for the irrationality measure of ${\rm e}^{2\pi m}$ and for the partial quotients in its continued fraction expansion.

4 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20222
2021157
2020172
2019127
2018120
2017140