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Divisor

About: Divisor is a research topic. Over the lifetime, 2462 publications have been published within this topic receiving 21394 citations. The topic is also known as: factor & submultiple.


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Patent
31 Aug 1989
TL;DR: In this article, the approximate inverse number is obtained without increasing the number of LSI even when table information is beyond memory capacity by providing a circuit for preparing higher 2 bits of approximate inverse and a table for lower 18 bits.
Abstract: PURPOSE:To obtain an approximate inverse number without increasing an LSI even when table information are beyond memory capacity by providing a circuit for preparing higher 2 bits of approximate inverse and a table for lower 18 bits of approximate inverse (memory). CONSTITUTION:When the execution of a floating-point dividing instruction is started, a divisor to be set to a divisor register 2 is supplied through a digit normalizing circuit 4 to a divider 10 and supplied to a bit normalizing circuit 5. Then, a memory referring address is prepared to obtain the approximate inverse number. A table for lower 18 bits of approximate inverse 8 is referred according to addresses d2, d3...d11 and approximate inverses S3, S4...S20 are obtained. Then, according to the correspondence between the address and higher 2 bits of an inverse an S1 and an S2 are prepared in a circuit for preparing higher 2 bits of approximate inverse 7. Thus, approximate inverse numbers 1, S1, S2...S20 can be obtained. Then, since the approximate inverse can be obtained without increasing the number of the LSIs even when the table information to accompany the divisor are over the memory capacity, hardware quantity can be reduced.

1 citations

01 Jan 2015
TL;DR: This paper presents the condition of add-shift schemes that had been modified from existing algorithm to eliminate the integer multiplication and to round the unsigned result to the nearest integer.
Abstract: An implementation of division in hardware is expensive. One of the alternatives is by replacing it with cheaper adder and shifter. This paper presents the condition of add-shift schemes that had been modifiedfrom existing algorithm. The constant denominators are 3, 5, 6, 7 and 9. The modifications are to eliminate the integer multiplication and to round the unsigned result to the nearest integer. The comparison results of the outputs between C++ and Verilog codes are used to verify the accuracy of the division process. Verilog code needs to be changed for any incorrect results. The required results were obtained. The outputs (div_out) of all denominators (deno) have been rounded to the nearest integer. However, the maximum bit widths of numerators (n) are only 13 except for the divisor of 3 that produces the maximum bit width up to 16.

1 citations

Posted Content
TL;DR: In this article, the arithmetic fundamental lemma conjecture was proved over a general $p$-adic field with odd residue cardinality $q\geq \dim V$, which is similar to the one used by the second author during his proof of the AFL over $\mathbb{Q}_p$.
Abstract: We prove the arithmetic fundamental lemma conjecture over a general $p$-adic field with odd residue cardinality $q\geq \dim V$. Our strategy is similar to the one used by the second author during his proof of the AFL over $\mathbb{Q}_p$ (arXiv:1909.02697), but only requires the modularity of divisor generating series on the Shimura variety (as opposed to its integral model). The resulting increase in flexibility allows us to work over an arbitrary base field. To carry out the strategy, we also generalize results of Howard (arXiv:1303.0545) on CM-cycle intersection and of Ehlen--Sankaran (arXiv:1607.06545) on Green function comparison from $\mathbb{Q}$ to general totally real base fields.

1 citations

Proceedings ArticleDOI
03 Aug 1994
TL;DR: In order to easily generate the test patterns and the corresponding control signals, a graph labeling scheme is employed to derive a set of simple labels for the dividend, the divisor the quotient, the remainder, and the control signals.
Abstract: This paper presents a design of a C-testable carry-free divider circuit and its test generation The divider circuit takes the dividend and divisor digits, in redundant binary form, as its inputs and produces the quotient and remainder digits, also in redundant binary form The circuit is fully testable with a test set of 72 test patterns irrespective of its bit size In order to easily generate the test patterns and the corresponding control signals, a graph labeling scheme is employed to derive a set of simple labels for the dividend, the divisor the quotient, the remainder, and the control signals

1 citations

Posted Content
TL;DR: In this article, the Chung-Feller theorem was used to show that the number $n+ 1$ is a divisor of the central binomial coefficient for lattice paths.
Abstract: It is well known that for all $n\geq1$ the number $n+ 1$ is a divisor of the central binomial coefficient ${2n\choose n}$ Since the $n$th central binomial coefficient equals the number of lattice paths from $(0,0)$ to $(n,n)$ by unit steps north or east, a natural question is whether there is a way to partition these paths into sets of $n+ 1$ paths or $n+1$ equinumerous sets of paths The Chung-Feller theorem gives an elegant answer to this question We pose and deliver an answer to the analogous question for $2n-1$, another divisor of ${2n\choose n}$ We then show our main result follows from a more general observation regarding binomial coefficients ${n\choose k}$ with $n$ and $k$ relatively prime A discussion of the case where $n$ and $k$ are not relatively prime is also given, highlighting the limitations of our methods Finally, we come full circle and give a novel interpretation of the Catalan numbers

1 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20222
2021157
2020172
2019127
2018120
2017140