Divisor

About: Divisor is a research topic. Over the lifetime, 2462 publications have been published within this topic receiving 21394 citations. The topic is also known as: factor & submultiple.

K\"ahler-Einstein metrics with conic singularities along self-intersecting divisors

Abstract: In this paper, we extend the existence and regularity theorems for Kahler-Einstein metrics having conic singularities along a simple normal crossing divisor to the case of normal crossing divisor, ie when components of the divisor are allowed to intersect themselves transversely

Variety of singular quadrics containing a projective curve

Abstract: We study the variety of rank $\leq k$ quadrics containing a general projective curve and show that it has the expected dimension in the range $g-d+r\leq 1$. By considering the loci where this expectation is not true, we construct new divisor classes in $\overline{\mathcal{M}}_{g,n}$. We use one of these classes to show that $\overline{\mathcal{M}}_{15,9}$ is of general type.

Double cubics and double quartics

Abstract: We study a double cover $\psi:X\to V\subset\mathbb{P}^{n}$ branched over a smooth divisor $R\subset V$ such that $R$ is cut on $V$ by a hypersurface of degree $2(n-\mathrm{deg}(V))$, where $n\geqslant 8$ and $V$ is a smooth hypersurface of degree 3 or 4. We prove that $X$ is nonrational and birationally superrigid.

Floating-point division and squareroot circuit with early determination of resultant exponent

Abstract: A circuit calculates the exact biased resultant exponent before calculating the resultant mantissa of a division operation. The circuit includes a carry-save adder, a conditional-sum adder, a multiplexer and a comparator. The conventional carry-save adder receives the biased exponent of the dividend (e1), the one's complement of the biased exponent of the divisor (˜e2), and the bias. The conditional-sum adder receives the sum and carry resultants of the carry-save adder, outputting {er0=e1+(˜e2)+bias} and {er1=e1+(˜e2)+bias+1}. The comparator controls the multiplexer to respectively select as the resultant exponent either er0 or er1 when the fraction of the dividend is less than or greater than or equal to the fraction of the divisor. A circuit for determining the resultant exponent of a squareroot operation includes a conditional-sum adder, a multiplexer and a selection logic circuit. The conditional-sum adder receives ½ of e2 and an adjusted bias. The adjusted bias is ½ of the bias (incremented if e2 is odd), causing the conditional-sum adder to output {er0=½e2+adjusted bias} and {er1=½e2+adjusted bias+1}. The selection logic controls the multiplexer to select er0, except in the case in which all three of the following conditions exist: (i) the fraction of the operand has no zeros; (ii) the squareroot operand is even; and (iii) the rounding mode is rounding to positive infinity.

A lower bound on the minimum distance of a -generator quasi-cyclic code

Abstract: Let be the nite eld of elements and be the algebra of -ary polynomials modulo The -generator quasi-cyclic (QC) code of block length over , of index a divisor of , with generator is the -cyclic submodule of dened as