Divisor

About: Divisor is a research topic. Over the lifetime, 2462 publications have been published within this topic receiving 21394 citations. The topic is also known as: factor & submultiple.

Reduced Divisors and Embeddings of Tropical Curves

Abstract: Given a divisor $D$ on a tropical curve $\Gamma$, we show that reduced divisors define an integral affine map from the tropical curve to the complete linear system $|D|$. This is done by providing an explicit description of the behavior of reduced divisors under infinitesimal modifications of the base point. We consider the cases where the reduced-divisor map defines an embedding of the curve into the linear system, and in this way, classify all the tropical curves with a very ample canonical divisor. As an application of the reduced-divisor map, we show the existence of Weierstrass points on tropical curves of genus at least two and present a simpler proof of a theorem of Luo on rank-determining sets of points. We also discuss the classical analogue of the (tropical) reduced-divisor map: For a smooth projective curve $C$ and a divisor $D$ of non-negative rank on $C$, reduced divisors equivalent to $D$ define a morphism from $C$ to the complete linear system $|D|$, which is described in terms of Wronskians.

Iterative binary divider utilizing multiples of the divisor

Abstract: A high speed divider is provided for a digital computer for generating a predetermined number of partial quotient bits per iteration by initially using a decode table implemented by a logic network to examine a predetermined number of high order bits of the divisor and another predetermined number of high order bits of the dividend, on the first iteration, and on successive iterations, of the partial remainder. The decode table is generated using the principle that for a given range of the divisor and dividend, as established by fixing the high order digits thereof, a limited range of possible partial quotients exists. The number of difference networks required to form partial remainders is limited to the number of decoded possible values for the partial quotient to be generated. A number of trial possible partial remainders are generated by the difference networks using the multiples of the divisor equal to the decoded possible partial quotient values. A second decode table, implemented by a logic network, determines, from the multiples of the divisor gated to the difference networks, and the results determined therein, which has produced the new partial remainder for the next iteration. The bits of the partial quotient are determined by a selector which examines the multiples of the divisor gated to the difference networks and the network from which the new partial remainder was derived. The process of iteration continues until the entire quotient is generated.

Division and/or square root calculating circuit

Abstract: An iterative division and/or iterative square root circuit 20 uses quotient digits q j+1 within the calculation that are dependent upon the input divisor D or radicand A and current partial remainder or partial radicand P j for the cycle reached. As the input divisor D or radicand A is fixed throughout the calculation, the critical path through the iterative circuit may be speeded up by preselecting and storing a subset QC of quotient digit values using a primary quotient digit selecting circuit 18, 22 operating in dependence upon the divisor D or radicand A and independently of the partial remainder or partial radicand P j . Within the iterative circuit 20, the quotient digits q j+1 to be used for each cycle can then be selected from this subset QC by a secondary quotient digit selecting circuit 24 in dependence upon the partial remainder or partial radicand P j and independent of the divisor D or radicand A.

Fast divider for a constant divisor

Abstract: In a divider for dividing a dividend by a divisor to calculate a quotient and a remainder, the divisor being a natural number which is a constant, each of the dividend, the quotient, and the remainder being an integer which is not less than zero, first through N-th comparing circuits compare the dividend with first through N-th predetermined constants. An n-th predetermined constant is equal to n times as large as the divisor, where n is variable between 1 and N, both inclusive. The first through the N-th comparing circuit produce first through N-th comparison result signals. A decoder decodes a combination of the first through the N-th comparison result signals into first and second partial decoded signals. The first partial decoded signal is equal to the quotient. The second partial decoded signal is equal to lower bits of a product of the quotient and the divisor. A subtracter subtracts the second partial decoded signal from lower bits of the dividend to produce the remainder.

On the singularities of the pluricomplex green's function

Abstract: It is shown that, on a compact Kahler manifold with boundary, the singularities of the pluricomplex Green's function with multiple poles can be prescribed to be of the form $\log\sum_{j=1}^n|f_j(z)|^2$ at each pole, where $f_j(z)$ are arbitrary local holomorphic functions with the pole as their only common zero. The proof is a combination of blow-ups and recent a priori estimates for the degenerate complex Monge-Ampere equation, and particularly the $C^1$ estimates away from a divisor.