Divisor

About: Divisor is a research topic. Over the lifetime, 2462 publications have been published within this topic receiving 21394 citations. The topic is also known as: factor & submultiple.

Log minimal model program for the moduli space of stable curves of genus three

Abstract: In this paper, we completely work out the log minimal model program for the moduli space of stable curves of genus three. We employ a rational multiple $\alpha\delta$ of the divisor $\delta$ of singular curves as the boundary divisor, construct the log canonical model for the pair $(\bar{\mathcal M}_3, \alpha\delta)$ using geometric invariant theory as we vary $\alpha$ from one to zero, and give a modular interpretation of each log canonical model and the birational maps between them. By using the modular description, we are able to identify all but one log canonical models with existing compactifications of $M_3$, some new and others classical, while the exception gives a new modular compactification of $M_3$.

A log PSS morphism with applications to Lagrangian embeddings

Abstract: Let $M$ be a smooth projective variety and $\mathbf{D}$ an ample normal crossings divisor. From topological data associated to the pair $(M, \mathbf{D})$, we construct, under assumptions on Gromov-Witten invariants, a series of distinguished classes in symplectic cohomology of the complement $X = M \backslash \mathbf{D}$. Under further "topological" assumptions on the pair, these classes can be organized into a Log(arithmic) PSS morphism, from a vector space which we term the logarithmic cohomology of $(M, \mathbf{D})$ to symplectic cohomology. Turning to applications, we show that these methods and some knowledge of Gromov-Witten invariants can be used to produce dilations and quasi-dilations (in the sense of Seidel-Solomon [SS]) in examples such as conic bundles. In turn, the existence of such elements imposes strong restrictions on exact Lagrangian embeddings, especially in dimension 3. For instance, we prove that any exact Lagrangian in a complex 3-dimensional conic bundle over $(\mathbb{C}^*)^2$ must be diffeomorphic to $T^3$ or a connect sum $\#^n S^1 \times S^2$.

A converse to Lagrange's theorem

Abstract: An integer n >0 is called a CLT -number if any group of order n has subgroups of order d for every divisor d of n . The Set of CLT -numbers n is characterized by properties of the prime factorization of n . In addition, if G has order dividing a CLT -number then the structure of G/C G (U) is given where U is a chief factor of G . As a consequence, it is shown that G is solvable of Fitting height at most 3.

VHDL Implementation of Non Restoring DivisionAlgorithm Using High Speed Adder/Subtractor

Abstract: Binary division is basically a procedure to determine how many times the divisor D divides the dividend B thus resulting in the quotient Q. At each step in the process the divisor D either divides B into a group of bits or it does not. The divisor divides a group of bits when the divisor has a value less than or equal to the value of those bits. Therefore, the quotient is either 1 or 0. The division algorithm performs either an addition or subtraction based on the signs of the divisor and the partial remainder. There are number of binary division algorithm like Digit Recurrence Algorithm restoring, non-restoring and SRT Division (Sweeney, Robertson, and Tocher), Multiplicative Algorithm, Approximation Algorithms, CORDIC Algorithm and Continued Product Algorithm. This paper focus on the digit recurrence non restoring division algorithm, Non restoring division algorithm is designed using high speed subtractor and adder. High speed adder and subtractor are used to speed up the operation of division. Designing of this division algorithm is done by using VHDL and simulated using Xilinx ISE 8.1i software has been used and implemented on FPGA xc3s100e-5vq100.

Division over GF(2/sup m/)

Abstract: Two algorithms are presented for carrying out division over GF(2 m ). Although ostensibly different in approach, both algorithms can be implemented by the same hardware. It is further shown that the resulting divider is hardware efficient and therefore suitable for VLSI implementation