Drain-induced barrier lowering
About: Drain-induced barrier lowering is a(n) research topic. Over the lifetime, 6163 publication(s) have been published within this topic receiving 101547 citation(s).
Papers published on a yearly basis
29 Apr 2003
TL;DR: Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.
Abstract: High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.
••01 Dec 2009
TL;DR: In this paper, a self-aligned top-gate amorphous oxide TFTs for large size and high resolution displays are presented, where Ar plasma is exposed on the source/drain region of active layer to minimize the source and drain series resistances.
Abstract: We have demonstrated self-aligned top-gate amorphous oxide TFTs for large size and high resolution displays. The processes such as source/drain and channel engineering have been developed to realize the self-aligned top gate structure. Ar plasma is exposed on the source/drain region of active layer to minimize the source/drain series resistances. To prevent the conductive channel, N 2 O plasma is also treated on the channel region of active layer. We obtain a field effect mobility of 5.5 cm2/V·s, a threshold voltage of 1.1 V, and a sub-threshold swing of 0.35 V/decade at sub-micron a-GIZO TFTs with the length of 0.67#x00B5;m. Furthermore, a-IZO TFTs fabricated for gate and data driver circuits on glass substrate exhibit excellent electrical properties such as a field effect mobility of 115 cm2/V·s, a threshold voltage of 0.2 V, a sub-threshold swing of 0.2 V/decade, and low threshold voltage shift less than 1 V under bias temperature stress for 3 hr.
04 Jan 2012-Applied Physics Letters
TL;DR: In this paper, a single-crystal gallium oxide (Ga2O3) metal-semiconductor field effect transistors (MESFETs) with a gate length of 4 μm and a source-drain spacing of 20 μm is presented.
Abstract: We report a demonstration of single-crystal gallium oxide (Ga2O3) metal-semiconductor field-effect transistors (MESFETs). A Sn-doped Ga2O3 layer was grown on a semi-insulating β-Ga2O3 (010) substrate by molecular-beam epitaxy. We fabricated a circular MESFET with a gate length of 4 μm and a source–drain spacing of 20 μm. The device showed an ideal transistor action represented by the drain current modulation due to the gate voltage (VGS) swing. A complete drain current pinch-off characteristic was also obtained for VGS < −20 V, and the three-terminal off-state breakdown voltage was over 250 V. A low drain leakage current of 3 μA at the off-state led to a high on/off drain current ratio of about 10 000. These device characteristics obtained at the early stage indicate the great potential of Ga2O3-based electrical devices for future power device applications.
06 Feb 2009-Applied Physics Letters
TL;DR: In this article, the authors describe a metaloxide-semiconductor MOS transistor concept in which there are no junctions and the channel doping is equal in concentration and type to the source and drain extension doping.
Abstract: This paper describes a metal-oxide-semiconductor MOS transistor concept in which there are no junctions. The channel doping is equal in concentration and type to the source and drain extension doping. The proposed device is a thin and narrow multigate field-effect transistor, which can be fully depleted and turned off by the gate. Since this device has no junctions, it has simpler fabrication process, less variability, and better electrical properties than classical MOS devices with source and drain PN junctions.
TL;DR: In this paper, a gate injection transistor (GIT) was proposed to increase the electron density in the channel, resulting in a dramatic increase of the drain current owing to the conductivity modulation.
Abstract: We have developed a normally-off GaN-based transistor using conductivity modulation, which we call a gate injection transistor (GIT). This new device principle utilizes hole-injection from the p-AlGaN to the AlGaN/GaN heterojunction, which simultaneously increases the electron density in the channel, resulting in a dramatic increase of the drain current owing to the conductivity modulation. The fabricated GIT exhibits a threshold voltage of 1.0 V with a maximum drain current of 200 mA/mm, in which a forward gate voltage of up to 6 V can be applied. The obtained specific ON-state resistance (RON . A) and the OFF-state breakdown voltage (BV ds) are 2.6 mOmega . cm2 and 800 V, respectively. The developed GIT is advantageous for power switching applications.
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