Showing papers on "Drain-induced barrier lowering published in 1968"

A new insulated gate tetrode with high drain breakdown potential and low miller feedback capacitance

Abstract: Insulated gate field effect transistors (IGFET's) with the gate offset from the drain electrode exhibit high drain breakdown potential and very low Miller feedback capacitance. The new insulated gate tetrode (IGT) described in this paper utilizes a second stacked gate to create the offset channel. The main advantage is the possibility of optimizing the device performance, especially the drain breakdown potential for both P -and N -channel devices. Considered in the paper are design and fabrication problems, V-I characteristics, drain breakdown potential, dynamic drain resistance, small-signal equivalent circuit, and large-signal limitations. P -channel IGT's with drain breakdown potentials up to 300 V have been built. The design of the IGT depends mainly on the tradeoff between drain breakdown potential and the limited frequency response caused by the time constant of the offset channel. The results to date indicate that the IGT has a large drain voltage range and an extremely low Miller feedback capacitance and is adaptable to different operating conditions. The IGT appears very promising for use in power amplifiers and switching applications.

Theoretical threshold voltages for MOS field effect transistors

Abstract: By employing the charge neutrality condition in the vicinity of the gate insulator in the MOS structure, theoretical curves of the threshold voltages for both n- and p-channel MOSFETs are obtained as a function of substrate doping concentration, built-in positive charge at the oxide-silicon interface, oxide thickness, and surface trapping. Curves of theoretical threshold voltages for MOSFETs employing Al2O3-SiO2 gate insulators are also obtained. The effect of gold doping of the silicon substrate upon the threshold voltages of MOSFETs is discussed. As a result, the conditions which determine whether a particular MOSFET will be a depletion type or an enhancement type are specified as a function of the construction parameters of the device.

Insulated gate field effect transistor used as a voltage-controlled linear resistor

Abstract: The channel resistance of a metal-oxide-semiconductor fieldeffect transistor, or other insulated gate field effect transistor, is linearized by applying to the gate electrode, in addition to the gate voltage for controlling the conductivity, an external feedback voltage having a value of one-half the supply voltage to nullify the effect of the internal feedback due to the supply voltage. In some cases the base electrode is disconnected, but spurious effects caused thereby can be avoided. The voltagecontrolled linear resistor can be employed in DC and AC circuits in applications such as an AC phase shift circuit.

A simple theory for threshold voltage modulation in IGFETs

Abstract: The threshold voltage of an insulated gate field-effect transistor is a function of source-to-substrate reverse bias. In this letter, the previously presented theory is first reviewed. It is then extended to apply to large source-to-substrate reverse bias where the source and drain depletion regions meet under the channel. The result is a pair of theoretical expressions which agree well with experimental measurements.

Silicon N-Channel Normally-Off Insulated-Gate Field-Effect Transistors

Abstract: Characteristics of n-channel normally-off insulated-gate field-effect transistors (IGFETs) are studied theoretically and experimentally. The obtained theoretical drain current is as follows:- ID=-IDOeq(VGS-VTO)/mkT(1-e-qVDS/kT) where IDO is a constant, VGS and VTO are gate potential and the threshold voltage to make the onset of inversion, VDS is drain to source bias and m is reciprocal slope which is numerical constant determined by the parameters of the given FET. As predicted by the theory, experimental log IDvsVGS relation exhibits excellent linearity in the low level. The reciprocal slope and the thereshold voltage for the intrinsic drain current are influenced by the surface states as much as by the fixed charges located at the interface. P-type (100) oriented substrate wafer of up more than 14 is needed to make n-channel normally-off IGFET in the present technique, where up is a normalized Fermi potential of the substrate.

Detection circuit including compensation for the threshold of the forward characteristic of a semiconductor junction

Abstract: A transistor detector circuit features a diode coupled in series with the base of the transistor to temperature compensate the circuit against temperature shifts in the base-emitter threshold voltage. A second transistor and a second diode can also be used for detecting signals of greater amplitude.

Capacitor-transformer voltage equalization network for series connected transistor switches

Abstract: During the turnoff transition of series connected complementary transistor pair switches against a voltage in excess of the permissible standoff voltage of any one switch, it becomes necessary to equalize the voltage drop across each switch. Such equalization is accomplished by connecting a capacitor between the collector and base of each transistor in a complementary pair switch, with the capacitor having a larger displacement current than the collector current of that transistor. In this way, the rate of change of the collector to base voltage is maintained substantially equal between the several series connected transistors. This maintains substantially equal standoff voltage in each transistor during rise and fall times, providing transistor storage times are equal and turnoff signals are received at the same time. In order to overcome this potential cause of excessive voltage against any complementary pair transistor switch, pulse transformers are connected with one coil in series with the capacitor and the other coil in series with the emitter of the majority current carrying transistor so that the capacitive displacement current provides a voltage pulse in series aiding with the base-to-emitter voltage of the minority current carrying transistor to slow the transition speed of the succeeding complementary transistor pair switch first turning off and to allow its transition speed to approach that of the slower transition speed switch elements.