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Showing papers on "Drain-induced barrier lowering published in 1969"


Patent
30 Sep 1969
TL;DR: The threshold voltage of an IGFET is precisely controlled by the introduction of a quantity of dopants into the gate and channel region by exposure to an energetic ion beam as mentioned in this paper, which is the same as the effect described in this paper.
Abstract: The threshold voltage of an IGFET is precisely controlled by the introduction of a quantity of dopants into the gate and channel region by exposure to an energetic ion beam.

24 citations


Journal ArticleDOI
Paul Richman1
TL;DR: In this paper, the authors used selective gold-doping techniques to achieve enhancement-type characteristics for both n-and p-channel MOSFETs on high-resistivity π substrates.
Abstract: p -Channel enhancement mode MOS field-effect transistors have been fabricated on high-resistivity p -type (π) silicon substrates. A high off-state impedance can be achieved with zero gate voltage if the substrate resistivity is sufficiently high so that the p + π low-high junctions formed by the diffusion of the drain and source regions exhibit the desired rectifying characteristics. n -channel MOSFETs can also be fabricated on these high-resistivity π substrates. While the n -channel devices usually exhibit depletion mode characteristics, both n - and p -channel enhancement type MOSFETs can be simultaneously fabricated on a single substrate if Al 2 O 3 -SiO 2 gate insulating layers are used and if Q SS is kept sufficiently small. Selective gold-doping techniques can also be employed to achieve enhancement-type characteristics for both n - and p -channel devices. The channel lengths must be sufficiently large to eliminate SCL current flow from drain to source with zero gate voltage. By using techniques such as beam-lead interconnections or dielectric isolation, complementary MOS integrated circuits can be fabricated on a single substrate and only two diffusions are required. Additional advantages of this approach include extremely high carrier mobilities, very low threshold voltages for both units, and negligible variation of MOSFET characteristics with reverse substrate bias.

10 citations


Patent
15 May 1969
TL;DR: In this article, a MIS FET is constructed with linearly graded PN junctions and the diffusion profile, as related to the geometry of the gate, is such that the junction depletion layer will extend into the drain region to a point under the thick field oxide so that a critical electric field is not produced in the thin gate oxide causing rupture thereof.
Abstract: An MIS FET device and method of making the same wherein a device of nominal topology is made capable of sustaining drain to source potentials substantially higher than the normal breakdown potentials of prior art devices. The present invention is constructed with linearly graded PN junctions and the diffusion profile, as related to the geometry of the gate, is such that the junction depletion layer will extend into the drain region to a point under the thick field oxide so that a critical electric field is not produced in the thin gate oxide causing rupture thereof.

10 citations


Patent
Karsten E Drangeid1
12 Dec 1969
TL;DR: In this article, a field effect transistor with a gate electrode which is considerably extended in the direction of the semiconductor current channel is described, and a solid-state delay line is disclosed, where two DC voltage sources are connected to the source and drain electrodes and to the ends of the gate electrode.
Abstract: A solid-state delay line is disclosed which includes a field effect transistor with a gate electrode which is considerably extended in the direction of the semiconductor current channel. Two DC voltage sources are connected to the source and drain electrodes and to the ends of the gate electrode, respectively, and cause currents to be adjusted such that the voltage drops per unit length in the semiconductor channel and in the gate electrode are equal. A uniform thickness of the charge carrier variation zone, i.e., a depletion zone or an enhancement zone, is obtained in the semiconductor channel and the delay of signals propagating through the semiconductor channel is proportional to the length of the extended gate electrode.

9 citations


Patent
17 Apr 1969
TL;DR: In this paper, a method of making a field effect transistor with an accurately aligned gate by forming the source and drain regions from a doped layer on the substrate surface is described.
Abstract: Disclosed is a method of making a field effect transistor with an accurately aligned gate by forming the source and drain regions from a doped layer on the substrate surface. The resulting transistor has reduced internal capacitance and improved speed characteristics.

9 citations


Patent
08 Aug 1969
TL;DR: In this article, a test circuit for determining the pinch-off voltage of a field effect transistor is presented, where the gate electrode is grounded and observation of the voltage drop across the resistance element gives a reading differing from theoretical pinchoff voltage by only a small percentage.
Abstract: A test circuit for determining the pinch-off voltage of a field effect transistor comprises, in series, a source of unidirectional voltage of a magnitude greater than the expected pinch-off voltage and less than the breakdown voltage, the source and drain electrodes respectively of the field effect transistor under test, and a resistance element of relatively large magnitude, typically, at least one megohm. The gate electrode is grounded and observation of the voltage drop across the resistance element gives a reading differing from theoretical pinch-off voltage by only a small percentage.

7 citations


Journal ArticleDOI
P.S. Rao1
TL;DR: In this paper, the effect of the substrate on the gate and drain noise parameters in MOSFETs is calculated up to first order terms in jw, under the assumption that the channel has thermal noise.
Abstract: The effect of the substrate on the gate and drain noise parameters in MOSFETs is calculated up to first order terms in jw, under the assumption that the channel has thermal noise. It is shown that the substrate doping has little influence on the gate noise, i g 2 , and on the cross correlation between gate and drain noise i g i d ∗ . The theory cannot explain Halladay and van der Ziel's data. Therefore a non-thermal noise source must be operating in the channel.

7 citations


Patent
George Cheroff1
15 Jan 1969
TL;DR: In this paper, a field effect transistor of the insulated gate type is used as a photodetector with a gain greater than unity, where the transistor is biased in the '''''off'''' state by a substrate potential resulting from the provision of an external voltage supply in the source-to-substrate loop.
Abstract: A field-effect device is provided which comprises a field effect transistor of the insulated gate type. The device is capable of being used as a photodetector with a gain greater than unity. To this end, the transistor is biased in the ''''off'''' state by a substrate potential (source-to-substrate) resulting from the provision of an external voltage supply in the source-tosubstrate loop. Upon the radiation of the source and drain junctions in the transistor, a current is caused to flow between the source and drain electrodes which result in a current gain in excess of unity.

7 citations


Patent
26 Nov 1969
TL;DR: In this paper, a field-effect transistor with two gates has a resistance and a reactance serially connected across its drain and source, with one gate tied to the junction of these two impedances whereas the other gate has a modulating signal applied to it.
Abstract: A field-effect transistor with two gates has a resistance and a reactance serially connected across its drain and source, with one gate tied to the junction of these two impedances whereas the other gate has a modulating signal applied to it. The resistance may be constituted by the output circuit of a differential transistor amplifier having its input connected in parallel with drain and source of the field-effect transistor.

5 citations


Journal ArticleDOI
TL;DR: In this paper, a new thin-film transistor is described which is capable of withstanding several hundred volts, which can switch currents of the order of 100 μA with control voltages of a order of 50 V.
Abstract: A new thin-film transistor is described which is capable of withstanding several hundred volts. The device, which we call the high voltage thin-film transistor, will switch currents of the order of 100 μA with control voltages of the order of 50 V. Switching speeds of a fraction of a msec have been achieved with high impedance loads (greater than 10 7 -Ω), such as electroluminescent cells.

5 citations


Patent
23 Apr 1969
TL;DR: In this paper, an insulated gate field effect transistor is described in which an additional region of the opposite type conductivity is inset in the source or drain regions and connected to the gate.
Abstract: An insulated gate field-effect transistor is described in which an additional region of the opposite type conductivity is inset in the source or drain regions and connected to the gate. The additional junction thereby formed is reverse biased during operation. When inset in the drain, the reverse-biased junction provides additional gate-drain capacitance for a Miller integrator circuit, whereas when inset in the source, the additional junction can act as a safety diode between the gate and source. The low breakdown voltage of the additional junction due to the high-impurity content of the regions increases the protection afforded by the safety diode.