Showing papers on "Drain-induced barrier lowering published in 1971"

Threshold voltage compensating circuits for fets

Abstract: A field effect semiconductor device including a plurality of field effect semiconductor elements formed on a common substrate and a compensating circuit for controlling the threshold voltage of said transistors by comparing the threshold voltage of one transistor to a reference voltage and generating a backward bias control voltage across a PN-junction of the one transistor between the source thereof, which is connected to the source of at least one of the other transistors, and the common substrate.

Poly-silicon electrodes for c-igfets

Abstract: Poly-silicon electrodes are provided for use with source and drain regions of insulated gate field-effect transistors as well as a method for contacting silicon gate devices utilizing polysilicon electrodes and a single etching step. The single etching step obviates the use of an additional masking operation for forming preohmic holes in the vicinity of the source and drain regions for the device. The provision of preohmic holes at the source and drain regions necessitates large area source and drain regions so as to permit clearance for the metallization through preohmic holes. These large areas decrease packing density. The subject method however permits high density packing of the silicon gate devices because small area source and drain regions and small area electrodes can be used. Because of the use of poly-silicon electrodes, the process allows the probing of the chip at intermediate stages in device fabrication. This allows the elimination of those chips which have not satisfied design limitations at an intermediate step in the fabrication process. In the process the source and drain regions and the electrodes are doped simultaneously in a diffusion step. In this diffusion process part of the source and drain regions are diffused through that portion of the poly-silicon contact extending over the source or drain region. In this manner ohmic contact is made between the electrodes and the underlying source or drain regions.

The distribution of mobile carriers in the pinch-off region of an insulated-gate field-effect transistor and its influence on device breakdown

Abstract: A method of determining the distribution of injected carriers within the pinch-off region of an insulated-gate field-effect transistor is described. The analysis is based on two-dimensional solutions of both Poisson's Equation and the current continuity equation for minority carriers, within a small region adjacent to the drain junction. The effect of carrier velocity saturation in the pinch-off region, on the carrier density distribution is assessed. Regions of maximum field are determined. The magnitude of the maximum field within the device is shown to be dependent on the concentration gradient of impurities at the edge of the drain diffusion.

Electron gate currents and threshold stability in the n-channel stacked gate MOS tetrode

Abstract: A new structure is given for the n-channel stacked gate MOS tetrode which consists of a polycrystalline silicon buried control gate and thermally grown oxide for the offset gate insulator. As a result of the large band-bending in the offset gate depletion region of an operating tetrode, some drain current electrons surmount the Si-SiO 2 energy barrier and are injected into the oxide. Since the electron trapping is relatively small in the thermal-oxide offset gate insulator, it was possible to measure gate currents of up to 2 \times 10^{-4} A/cm2. The gate current was measured as a function of the drain current, the drain voltage and the offset gate voltage. The resulting behavior confirms previous models of the tetrode device. Since electron trapping is much less in thermally grown oxide than in deposited pyrolytic oxide which was used formerly, the offset gate threshold voltage shifts less. As a result of this effect the new structure is used to advantage in fabricating the n-channel stacked gate tetrode in that the drain current is comparatively insensitive to changes in the offset gate voltage.

Semiconductor electronic circuit with semiconductor bias circuit

Abstract: A semiconductor electronic circuit employs a semiconductor bias circuit, in which at least two inverter circuits are provided, each comprising a depletion type MOS transistor and an enhancement type MOS transistor, which are formed on a p-conductivity type semiconductor chip. The depletion type MOS transistor has its gate and source electrodes short-circuited and serves as a load transistor, while the enhancement type MOS type transistor has its drain electrode connected in series to the source electrode of the depletion type transistor. The input terminal and the output terminal of the first inverter circuit are connected to each other, and the voltage obtained at the output terminal is applied as a bias voltage to the input terminal of the second inverter circuit.

Field-effect transistor circuit for detecting changes in voltage level

Abstract: Two field-effect transistors interconnected in such a way that the output voltage produced by the first, which is a function of its voltage threshold, controls the conductivity of the second. One transistor may be reverse biased source-to-substrate to maintain its threshold voltage higher than that of the other. A small change in voltage level may be detected by this circuit by causing that change concurrently to reduce the source-to-substrate reverse bias of the first transistor and to reverse bias the source-to-substrate of the second transistor.

Method of measuring magnetic fields utilizing a three dram igfet with particular bias

Abstract: A mode of operation of a three-drain configured insulated gate field effect transistor which is extremely sensitive to magnetic fields is disclosed. The gate of the transistor is biased to a level less than transistor threshold, or alternatively, is connected to substrate ground. A first drain region opposite the source is biased to achieve avalanche breakdown of the junction. The other two drains are defined on either side of a line joining the source and first drain. These two drains are biased at a voltage below that required for avalanche of their junctions. In response to a magnetic field a voltage difference is generated across these two drains. In one embodiment of the invention, the region opposite the source is of a conductivity type the same as the substrate. In this configuration the detector does not require avalanche breakdown.

Variable threshold memory system using minimum amplitude signals

Abstract: Selected devices of an MNOS array are placed in one threshold state by placing their gate electrodes at a first voltage level and their source and drain electrodes and their semiconductor substrate at a second voltage level. Selected devices are placed in a second threshold state by reversing the above mentioned voltage conditions. In both instances, appropriate voltages are applied to the non-selected devices to prevent them from changing their states. The substrate can be switched to assume various voltage levels.

Combined bipolar and field effect transistors

Abstract: In an integrated circuit of the type in which the drain region of an insulated gate field effect transistor (IGFET) also constitutes a base region of a bipolar transistor, the IGFET has interdigitated source and drain regions separated by a serpentine channel region. An emitter stripe of the bipolar transistor is included in each drain region protrusion. This configuration increases the efficiency of modulation of the bipolar emitter currents by the IGFET channel currents.

Method for making a schottky-barrier field effect transistor

Abstract: A Schottky-barrier field effect transistor is disclosed with a semiconductor channel of relatively low conductivity between the source and drain electrodes which may be electrically influenced by a Schottky-barrier gate electrode located on the semiconductor channel. The transistor is characterized by a zone or region of higher conductivity which extends from the vicinity of the source electrode to near the gate electrode. Further, source and drain regions are conveniently provided for the transistor of semiconductor of the same conductivity type as the channel semiconductor at the Schottky-barrier electrode. Advantageously, the drain region may be made of semiconductor of high conductivity and the same conductivity type as the source region. The high conductivity region may be achieved through either diffusion or epitaxial growth technique.

Inhomogeneous channel resistivity field effect devices

Abstract: Improvement in the operation of several field-effect devices is predicted through the use of specific longitudinal inhomogeneous channel resistivity profiles with heavier doping near the source than the drain end. One device, an inhomogeneous channel field-effect transistor or ICFET, is shown to have a marked reduction in the product of channel resistance and gate to channel capacitance. Effectively, these results imply that higher frequency operation is possible without reducing the device length. General equations for this device are developed and the cut-off frequency is derived in terms of the distributed resistance and capacitance product. One of the solutions of these equations for an exponential impurity profile has shown that a frequency response improvement of six times and gain bandwidth improvement of thirty times is obtained when the doping level changes by a factor of 100 from source to drain. A homogeneous FET of the same length with the same drain value of doping concentration is used for the comparison, thus keeping the breakdown voltages and pinch-off voltages equivalent. Another device, called the inhomogeneous channel current limiter, is a two terminal field-effect device which has a larger saturation current while the pinch-off voltage and the peak source to drain operating voltage are unchanged. Equations for this device have also been developed and the solutions indicate that the saturation current can be increased by one or two orders of magnitude for a linear impurity profile with a change in doping levels by a factor of 10 or 100 between the source and drain. The comparison is again made with a homogeneous device having a doping concentration equal to that at the drain end of the inhomogeneous device. These results can also be generalized to MOSFET devices.

Characteristics of the junction-gate field effect transistor with short channel length

Abstract: A two-section model of a junction-gate field effect transistor with short channel length was derived. In this model, the current conducting channel is divided into a source and a drain section. The gradual channel approximation with a modification to include the hot electron effect is assumed applicable in the source section. The velocity saturation transport with excess carrier accumulation effect is formulated for the drain section. The normalized design curves and the characteristics of two sample devices are presented.

Field effect transistor impedance coupling network whose output voltage equals the input voltage

Abstract: A field effect transistor impedance coupling circuit having two series connected field effect transistors. The source of the first transistor is connected to the drain of the second transistor through a resistor. The gate of the first transistor is the input. The drain of the second transistor is the output. The second transistor is connected as a constant current source, and the resistance value of the resistor is selected so that the output voltage equals the input voltage.

Photoresponses of MOS transistor

Abstract: Illumination effects on the drain current were studied for a p-channel enhancement-type MOS transistor, and the results show that the photoresponses are mainly due to electron excitation in the conduction band from surface states lying near the top of the valence band. It also appears that the hole density of the channel decresses in the vicinity of the drain region but is almost constant over the entire channel when more than 200 µm away from the drain edge.

Decrease of FET threshold voltage due to boron depletion during thermal oxidation

Abstract: Oxidation of a boron doped silicon wafer reduces the surface concentration of boron due to segregation into the oxide. This in turn reduces the threshold voltage of an FET fabricated on such a wafer. This effect is calculated for realistic process types including a sequence of several oxidations at different temperatures. The threshold voltage is found to be reduced by about 1 V (1000 A oxide) which is quite considerable. The depletion effect on threshold voltage is expressed in terms of two parameters (effective doping and apparent surface charge). The approximations used can be adapted to most processes. Also, the effect of boron depletion on the MOS capacitance-voltage curve is calculated. An apparent flat-band voltage shift of only 0·1 V is found (1000 A oxide, 2 ohmcm).

A high voltage ion-implanted MOSFET

Abstract: The drain breakdown voltage of usual p-channel MOS devices is limited to about 30 to 40 V by field crowding at the drain junction. By optimizing certain design parameters like diffusion depth, substrate resistivity and gate oxide thickness, 80 V breakdowns can be achieved. To date, higher breakdowns are only possible with special device geometries (e.g. the stacked gate tetrode) which are generally not compatible with common MOS processes. By adding an ion-implantation step to the conventional aluminum-gate MOS process, it is possible to fabricate MOSSFET's with source-drain breakdown potentials of greater than 240 V on the same chip with conventional MOS circuitry. The device looks identical to the conventional MOSFET except that an unmetalized gate oxide region is left between the gate and the drain juction. During a subsequent ion-implantation this portion of the channel is lightly doped with a p-type dopant in the case of p-channel devices. Since-both the metal and the field oxide are thick enough to stop all ions, the implantation affects only the high voltage devices on the wafer. The implanted channel has the effect of reducing the field in the vicinity of the drain junction, thereby increasing the source-drain breakdown voltage. P-channel devices were made on 10 Ω-cm material using 1µm diffused junctions. The aluminum gate was 10 µm long and the implanted channel was 25µm long. Breakdowns up to 240 V were achieved after an optimum dose of 2 \times 10^{12} boron ions/cm2were implanted at 80 keV through 1300 A of gate SiO 2 . The wafers were subsequently annealed for 15 minutes at 525°C in N 2 . Implanted resistors made at the same time had sheet resistivities of 25 kΩ/□. Of critical importance in obtaining best results are low threshold voltages and accurate implantation dose control To obtain long term reliability it is necessary to prevent charge build-up on the oxide over the implanted channel. This is accomplished by the deposition of a layer of phosphosilicate glass after ion-implantation. It is now possible to include decoding circuitry on the same chip as the high voltage drivers for display tubes.

A high-speed memory array using variable threshold transistors

Abstract: A computer memory utilizing an array of variable threshold transistor memory cells for storing respective digital bit data. Each transistor is characterized by an electrically controllable conduction threshold which can be set to a binary value upon the application of a pulse voltage of respective polarity and sufficient amplitude across the gate electrode and substrate. The binary states of addressed transistors are sensed by applying a reference voltage having an amplitude intermediate the binary conduction thresholds simultaneously to the gate electrodes of every transistor in the array and then applying a pulsed voltage to the source and drain electrodes of the addressed transistors. The addressed transistors conduct if in state ONE and do not conduct if in state ZERO.