Showing papers on "Drain-induced barrier lowering published in 1972"

Subthreshold drain leakage currents in MOS field-effect transistors

Abstract: There are two contributions to the drain-source leakage current in MOS field-effect transistors for gate voltages below the extrapolated threshold voltage (V tx ) : 1) reverse-bias drain junction leakage current, and 2) a surface channel current that flows when the surface is weakly inverted. Nearly six orders of magnitude of drain-source current from the background limit imposed by the drain junction leakage to the lower limits of detection of most curve tracers (0.05 µA) are controlled by gate-source voltages below the extrapolated threshold voltage. It is shown that this current flows only for gate voltages above the intrinsic voltage V i , the gate voltage at which the silicon surface becomes intrinsic. For gate voltages between V i and V tx the surface is weakly inverted with the resulting channel conductivity being responsible for the drain-source current "tails" observed for gate voltages below V tx . The importance of the intrinsic voltage in designing low-leakage CMOS and standard PMOS circuitry is discussed.

Field effect semiconductor device having an unsaturated triode vacuum tube characteristi

Abstract: A field effect transistor comprises a semiconductor channel, a source and a drain electrode formed at the opposite ends of the channel and a gate electrode provided on the side of the channel. The channel has a small impurity density and therefore the depletion layer extending from the gate goes deep into the channel to substantially close the conductive portion of the channel even in the absence of a gate voltage. The drain current will not flow where the drain voltage is below a certain threshold voltage, and will flow where the drain volage is above the threshold voltage exhibiting a linear resistance characteristic. This drain-current to drain-voltage characteristic simulates the anode-current to anode-voltage characteristic of the triode vacuum tube very closely.

Substrate bias circuit

Abstract: A semiconductor substrate including a field effect charge pump for injecting charge into the substrate and a field effect transistor circuit, connected between the substrate and a reference voltage source, responsive to the level of substrate charge for clamping the substrate bias voltage at a desired level. By controlling the gate voltage applied to the field effect transistor circuit and the number and arrangement of transistors in the circuit, the substrate bias voltage can be clamped at a value greater than, equal to, or less than the transistor threshold voltage.

An injection level dependent theory of the MOS transistor in saturation

Abstract: A qualitative and quantitative theory of the MOS transistor in saturation is developed, taking into account the fact that the carrier concentration in the drain region is not negligible. With reference to the behavior in saturation, an injection level is defined. This level is directly related to two parameters: the drain saturation field E DS and the effective depth of the drain region x D . A division of the current domain in low, medium, and high levels is proposed. For low injection levels (for which the saturation field is smaller than the critical field), an iterative procedure for the calculation of the drain saturation conductance is given. A method for determining the channel configuration is presented. Inconsistencies in the pinchoff concept are revealed by the calculation of this configuration and by the analysis of the validity domain of the equations based on gradual approximation.

Dynamic two device memory cell which provides d.c. sense signals

Abstract: A semiconductor two device memory cell is disclosed in which the two devices are complementary. The cell is best implemented in the integrated circuit environment and may be fabricated using well known non-complementary fabrication techniques. The cell incorporates a floating region or substrate - within - a - substrate on which charge is stored in different amounts to achieve different potentials on the region thereby controlling, in one mode, the threshold of a field effect transistor of which the floating region forms a part. In a different mode, the floating region or substrate forms a drain or source region for a switching transistor which is formed in its own substrate. The latter substrate, which is formed from a semiconductor chip or wafer, besides forming the channel region of the switching transistor acts as a source for a sensing transistor which is formed by a region of opposite conductivity type in the floating region, the floating region and the substrate itself. The floating region is charged to one of two potentials when the floating region is a drain or source of the switching transistor and, the amount of current flow is controlled by the potential on the floating region when it operates as the substrate for the sensing transistor.

Insulated dual gate field-effect transistor signal translator having means for reducing its sensitivity to supply voltage variations

Abstract: An oscillator circuit is described using a dual gate MOS-FET transistor. Drift of the oscillating frequency of the oscillator circuit caused by drain supply voltage variations is minimized by suitable bias voltages applied to the two gates. The gate bias voltages are derived from the same principle supply, but the gate voltage variations must be nonlinear with respect to the drain voltage variations to achieve frequency stability. The suitable gate voltages are achieved by means of a voltage divider composed of dual gate MOS-FET transistors.