Showing papers on "Drain-induced barrier lowering published in 1973"

An analysis of the threshold voltage for short-channel IGFET's

Abstract: For short-channel insulated-gate field-effect transistors (IGFET) operating with source-to-substrate reverse bias, the threshold voltage is in general a function of channel length and drain-to-source voltage. It is shown in this analysis that these dependences can be attributed to the two-dimensional distribution of the depletion charges. Starting from two fundamental relations, the overall charge neutrality and the voltage relations based on the energy band diagram, a generalized threshold voltage equation in integral form is derived. A closed-form threshold equation is then obtained using a regional approximation with a simplified piecewise-linear depletion profile. The equation includes as new factors, the channel length, junction depth and drain voltage, and passes to the conventional form for increasing channel length. The theoretical threshold voltage expression is found to predict the correct tendencies and is shown to be in reasonable agreement with experimental measurements.

Nonavalanche injection of hot carriers into SiO2

Abstract: Carriers can be injected into the SiO2 from a junction reverse biased below avalanche and lying in the silicon near the Si–SiO2 interface. This effect was studied for electron injection in n‐channel MOS transistors. The electrons originated from a forward‐biased (supply) junction lying below the source, drain, and channel region. The electrons were heated in the space‐charge layers of source and drain reverse biased below avalanche breakdown and in the space‐charge layer below the channel induced by the combined effect of a positive gate voltage and the reverse bias on source and drain. Injection into the oxide occurs mainly from the latter region. The current through the oxide and the charge trapped in the oxide were measured as a function of several parameters. These measurements yield the threshold values of the reverse source (drain) voltage, VTR, and of the gate voltage, VGT, necessary for injection. From the dependence of VTR on the concentration of dopant in the channel region, the value of the mea...

Low capacitance V groove MOS NOR gate and method of manufacture

Abstract: An MOS transistor is provided having a surface diffused drain and a common substrate source. A heavily doped base layer and a lightly doped space charge region are provided between the drain and source regions. The gate is formed on the inclined surface of a V groove which penetrates into the transistor to the substrate exposing the base layer to the gate structure. The gate is formed in the V groove by a silicon oxide insulative layer and conductive layer. Appropriate leads contact the gate conductor and the drain.

Low power, high speed, high output voltage fet delay-inverter stage

Abstract: An integrated circuit and a method operating the circuit is disclosed wherein first and second MISFET transistors are connected with the source node of the first common with the drain node of the second and providing the output node of an inverter or delay stage. The output node is capacitively coupled back to the gate of the first transistor. A third transistor also connects the gate of the first transistor to a source of voltage, such as the drain voltage, in such a manner that the first transistor can be controlled and also such that a voltage higher than the drain voltage can be permitted on the gate of the first transistor. The first transistor is turned off and the second turned on to provide a logic ''''0'''' output, and conversely the first on and the seond off to provide a logic ''''1'''' output, with no power consumption in either state. To switch from a logic 0 output to a logic 1 output, the first transistor is switched on just prior to the time the second is being switched off so that as a result, the gate of the first transistor is ''''bootstrapped'''' to a voltage in excess of the drain voltage as a result of being capacitively coupled to the output node as the second transistor is switched off. The very high gate voltage results in very rapid switching of the first transistor to an output level equal to the drain voltage, yet results in excess power consumption only during the short switching cycle while both transistors are on. The same results can be achieved without using the second transistor if the gate node of the first transistor is switched on very rapidly. The circuit third transistor is switched on very rapidly. The circuit can be used as a delay stage for clock generators or as an inverter stage, depending upon the node selected as the data input.

Theory of the M. O. S. transistor in weak inversion - new method to determine the number of surface states

Abstract: The drain current I D versus gate voltage V G of a MOST operating in weak inversion, and the influence of surface potential fluctuations on this characteristic have been studied before [1] The purpose of this paper is to derive an expression of the drain current I D versus the drain voltage V D for long channel devices. It is demonstrated that the surface potential fluctuations don't affect the slope of the I D -V D curve whereas the density N SS of surface states strongly influences the slope for small drain voltages. This yields a simple and useful technique to determine N SS on M.O.S. transistors.

High voltage, high frequency double diffused metal oxide semiconductor device

Abstract: High voltage, high frequency metal oxide semiconductor device having a precisely controlled channel extending to the surface and in which a metallization overlies a thick insulating layer and substantially covers the depletion region in the drain for breakdown voltage control.

Logic circuit arrangement employing insulated gate field effect transistors

Abstract: A logic circuit arrangement consisting of insulated gate field effect transistors of opposite channel types wherein the drain electrode of a single first insulated gate field effect transistor of one channel type is connected to the drain electrode of at least one second insulated gate field effect transistor of the opposite channel type constituting a logic gate. The gate electrode of second transistor is supplied with a data signal and the gate electrode of first transistor and the source electrode of second transistor are supplied with clock pulse signals bearing a complementary relationship with each other. The source electrode of first transistor may receive a clock pulse signal supplied to the source electrode of second transistor or constant voltage; and an output signal from the logic circuit is delivered from the junction of the first and second transistors.

Computer analysis of the double-diffused MOS transistor for integrated circuits

Abstract: The effective length of an MOS transistor can be made narrow by using double diffusion similar to a bipolar transistor. Computations were conducted for an n-channel double-diffused transistor with different surface concentrations, channel lengths, channel gradients, surface-states densities, and substrate concentrations. A shorter channel length and a higher surface-state density, e.g. \langle1, 1, 1\rangle crystal, gave a higher drain current and transconductance. The maximum transconductance in many cases occurs at low gate voltages. The computations indicate that a gain-bandwidth product in the gigahertz range can be expected when the graded channel region is less than 1 µm. The difference between an n-type substrate and a p-type substrate is not substantial. The analysis is also useful in predicting the performance of any integrated logic circuit using the diffused enhancement transistor as the active switch and a depletion-mode transistor (without a diffused channel) as the load device. The computation indicates that satisfactory performance can be obtained using a load device with the same geometry and an ON voltage of only a fraction of a volt, This revelation indicates that double-diffused channel MOS transistors not only give higher speed but also smaller chip area for integrated circuits and a lower supply voltage (hence less power dissipation).

Current source biasing circuit

Abstract: A first field effect transistor is employed as a current source with another like field effect transistor biased close to the threshold voltage thereof connected through a semiconductor junction to the gate of the first field effect transistor so that the current output of the source is substantially independent of supply voltage variations and the turn-on voltage of the first field effect transistor is determined by the forward voltage of the junction.

Method of making a planar graded channel MOS transistor

Abstract: The method of fabrication of a planar narrow channel metal oxide semiconductor field effect transistor (MOSFET) by a double diffusion through a self-aligned silicon gate wherein a first type dopant is diffused into the same self-aligned window of the source diffusion already diffused with a second type dopant. The diffused source and drains are self-aligned by means of the silicon gate, thus permitting narrow gate lengths. The diffusion profile is such that the impurity concentration near the source is higher than that near the drain. When a reverse bias is applied between, for example, an n-type drain and a p-type diffused region, the depletion layer cannot widen as much toward the source as a uniform channel because of the impurity concentration profile. Thus a narrow channel length can be used withoout drain-source punch-through at low voltages. Meanwhile, the self-aligned silicon gate permits a close spacing between the source and drain contacts, thus reducing the feedback capacitance between the drain and the gate.

Magnetic field detector employing plural drain igfet

Abstract: A mode of operation of a three-drain configured insulated gate field effect transistor which is extremely sensitive to magnetic fields is disclosed. The gate of the transistor is biased to a level less than transistor threshold, or alternatively, is connected to substrate ground. A first drain region opposite the source is biased to achieve avalanche breakdown of the junction. The other two drains are defined on either side of a line joining the source and first drain. These two drains are biased at a voltage below that required for avalanche of their junctions. In response to a magnetic field a voltage difference is generated across these two drains. In one embodiment of the invention, the region opposite the source is of a conductivity type the same as the substrate. In this configuration the detector does not require avalanche breakdown.

Process for the production of high value ohmic load resistors and mos transistors having a low starting voltage

Abstract: In a process for the production of circuits having at least one field effect transistor including a source, a drain, and a gate electrode, and having a resistor on a common substrate in which, starting with a substrate body having at least one field effect transistor, the process includes the formation of an enhancement type field effect transistor by ion implantation in the channel to decrease the starting voltage and the formation of the resistor by ion implantation adjacent the field effect transistor, wherein the resistor has a value which is high in comparison with the forward resistance of the conductive field effect transistor and low in comparison with the reverse resistance of the field effect transistor.

Magnetic field dependent field effect transistor

Abstract: A magnetic field effect transistor comprises a semiconductor body with a region of a specific type of conductivity, a source and a drain electrode between which is provided a channel region formed by a narrowed part of the region of the specific type of conductivity at least one barrier layer defining the channel region and controlling the channel region through the space charge region issuing from the barrier layer, and at least one additional electrode positioned laterally of the direct charge carrier path between the source and drain electrodes and to which at least part of the charge carrier can be deflected in the presence of a suitable magnetic field.

Method of manufacturing a field-effect transistor

Abstract: The method for making an improved field-effect transistor by using a thick insulating layer, the thickness of which is larger than the diffusion length of the impurity forming the base region in a following process step, as a mask for successive diffusion of two different impurities of different conductivity types and by using a portion of the thick insulating layer on the drain region as a portion of the gate insulating layer to reduce a parastic capacitance between the gate and the drain.

Mos integrated circuit process

Abstract: A method of forming an enhancement mode and a depletion mode transistor on a single substrate of a first conductivity type wherein each of the transistors has a pair of second conductivity type source and drain regions which are separated by a channel region and wherein an insulating layer is present on the surface of the substrate. The improvement comprises the steps of introducing a first conductivity type impurity in the substrate at the surface thereof, except in the channel region of the depletion mode transistor, reducing the amount of introduced impurity in the channel region of the enhancement mode transistor, producing contact holes in the insulating layer above the respective source and drain regions, and forming the respective gate, source and drain electrodes. The process eliminates field inversion without the necessity of a substrate bias and provides an automatic alignment of the channel of the enhancement mode transistor and the region of reduced concentration of the introduced impurity.

Variable resistance field effect transistor

Abstract: A variable resistance field effect transistor with a wide range of resistance and a linear ohmic characteristic having one or more small channels and one or more large channels formed by a gate region between a source region and a drain region in which both the small and large channels are located closer to the source electrode than to the drain electrode. The field effect transistor is such that as the gate voltage is changed from full drain current flow to pinch-off, the small channels are pinched off at first, after which the large channel or channels will reach a pinch-off voltage. In depletion type field effect transistors, with zero voltage on the gate electrode, the entire current through all of the small channels is much larger than the total current flowing through the large channels. The small channels may be of different size, since even if one channel is pinched off at a certain gate voltage, the next larger channel is not pinched off at that voltage. In another embodiment, the gate region is such that the channel area is gradually increased so that the pinch-off voltage is also gradually changed in accordance with the size of the channel.

Drain voltage limitations of short-channel M.O.S. transistors

Abstract: The maximum drain voltage for which an M.O.S.T. still obeys its normal pentode-like characteristics is an important consideration, especially to the circuit designer. For short channel devices the restrictions on the maximum drain voltage are even more severe than for longer channel devices, and therefore an accurate method of predicting these voltage limitations is required. The drain voltage is limited by two mechanisms; namely (a) punch-through of the drain depletion region to the source and (b) breakdown due to impact ionization in the high field region at the drain edge. A two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through or avalanche breakdown, from a solution of Poisson's Equation within the substrate depletion region, is adopted. The punch-through voltage is defined as the drain-to-source voltage at which the longitudinal field at any point along the edge of the source region inverts in sign to permit the drift of minority carriers from source to drain. Breakdown voltage, however, is determined by the drain voltage at which the maximum field in the device reaches the critical value for avalanche multiplication. Good agreement is achieved between theoretical and practical results for both mechanisms on a variety of devices. The effects of varying both the physical device parameters and gate voltage are also described.