Showing papers on "Drain-induced barrier lowering published in 1974"

A simple theory to predict the threshold voltage of short-channel IGFET's

Abstract: A simple expression for the threshold voltage of an IGFET is derived from a charge conservation principle which geometrically takes into account two-dimensional edge effects. The expression is derived for zero drain voltage and is valid for short and long-channel lengths. The dependence of the threshold voltage on the source and drain diffusion depth, r j , and channel length, L , is explicitly given. In the limit, L / r j → ∞, the threshold voltage equation reduces to the familiar expression for the long-channel case. The theory is compared with the measured threshold voltages on IGFET's fabricated with 1·4, 3·8 and 7·4 μm channel lengths. The dependence of the threshold voltage under backgate bias voltages ranging from zero to breakdown agrees closely with the theory.

Threshold voltage controllability in double-diffused-MOS transistors

Abstract: The sensitivity of double-diffused metal-oxide-semiconductor (D-MOS) transistor threshold voltage to fabrication process variations has been studied. Computed impurity profiles are used to study the process dependencies. For the double diffused process, the channel predeposition is shown to be the most critical step in threshold voltage control for long channel devices. Experimental results confirm this relationship. Process considerations appropriate for the fabrication of short channel D-MOS devices are also presented. Computed variations of threshold voltage with expected process tolerances for the channel predeposition are consistent with experimental results. Computer results show that for D-MOS deviceswith source junction depths of about 1 µm and channel lengths greater than 2 µm, threshold voltage can be controlled to ±20 percent using thermal diffusion and ±5 percent using ion implanted predeposition. Greater variation in threshold voltage is found for shorter channel lengths.

Drain voltage limitations of MOS transistors

Abstract: A comprehensive investigation has been carried out into the factors which influence the maximum drain voltage of an M.O.S. transistor for normal pentode-like operation. The drain voltage is limited by two principal mechanisms, namely punch-through of the drain depletion region to the source, and breakdown, due to impact ionization in the high field region at the drain edge. A two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through or avalanche breakdown, from a solution of Poisson's equation within the substrate depletion region, is described. The solutions are obtained using finite difference numerical methods which take into account the gate-induced potential profiles at the edge of the source and drain junctions. Boundary conditions of zero effective gate bias and channel current are imposed which simplify the solution of Poisson's equation to an electrostatic one. The punch-through voltage VPT is defined as the drain-to-source voltage at which the longitudinal field at any point along the edge of the source region inverts in sign to permit the drift of minority carriers from source to drain. Breakdown voltage, VBD, however, is determined by the drain voltage at which the maximum field in the device reaches the critical value for avalanche multiplication. Good agreement is achieved between theoretical and practical results for both mechanisms on a wide variety of devices. It is shown that VPT decreases as the channel length and substrate doping concentration decrease and as the oxide thickness and diffusion depth increase. VBD, however, decreases as the channel length, oxide thickness and diffusion depth decrease. Punch-through and breakdown are discussed for gate bias conditions above and below threshold. The sharp fall in breakdown voltage as the gate bias rises above threshold is explained on the basis of injected charge from the channel into the drain depletion region.

Mosfet transistor and method of fabrication

Abstract: An n channel MOSFET transistor which includes doping of previously formed source and drain elements with a heavy diffusion of phosphorous or arsenic creating n + + regions in the source and drain. The extra diffusion step is preferably accomplished just prior to contact metalization.

Mos transistor gain block

Abstract: An MOS gain block constituted by a pair of like MOS transistors operating in the weak inversion region and serially-connected to a low-voltage supply. One transistor acts as an active element whereby an input voltage applied to the gate produces an output voltage at the drain thereof. The other transistor whose gate is coupled to the drain of the active element, acts as a load element with respect to the active element, the stage load resistance varying to compensate for changes in the transconductance of the active element resulting from changes in supply voltage, thereby maintaining the gain of the block at a substantially constant level despite changes in supply voltage.

MOSFET's in the 0°K approximation: Static characteristics of MOSFET's in the 0°K approximation☆

Abstract: The static electrical characteristics below current saturation of MOSFET's with degenerate source and drain regions are calculated for operation at 0°K. The expression for current takes the same form as at room temperature although the flat-band voltage and the voltage across the depletion region at threshold are altered slightly. Potential hills occur in the channel if the gate does not overlap source and drain or if the oxide thickness is increased in the overlap regions. Although these barriers do not affect operation appreciably at room temperature, at 0°K a finite drain voltage (source-drain threshold voltage) is required to initiate conduction. This threshold voltage is included in the theory and the theory is compared with experimental results on p -channel enhancement mode MOSFET's at 4·2°K using hole mobility in the channel as a matching parameter. The channel hole mobility (assumed constant along the channel) is found to be relatively independent of gate voltage but to increase with increasing (negative) drain voltage. Values ranging between 500 and 1000 cm 2 /V-sec are deduced for drain voltages ranging from −1·2 V to −7 V. This compares to channel hole mobility values of 200–300 cm 2 /V-sec at room temperature. It is found that the channel width is on the order of 30–50 A—appreciably less than that at room temperature.

Insulated gate field effect transistor having high transconductance

Abstract: An insulated gate field effect transistor having improved high-frequency operating characteristics includes an extended region electrically connected to one of the source and drain regions and spaced from the surface of the substrate. The extended region extends toward the other of the source and drain regions such that the distance between the source and drain regions is relatively small within the substrate and relatively large at the surface of the substrate.

Self aligned drain and gate field effect transistor

Abstract: A method for manufacturing a field effect transistor device utilizing the intentional buildup of material on the source region of the device to mask the gate region of the device and obtain an edge on the drain region which closely follows the contour of the edge on the source region thus permitting a narrow, constant width gate region and more uniform capacitance and current flow between the source and drain regions. The material buildup on the source region of the device is a film of metal which is evaporated on a semiconductor wafer so as to define a pattern with one straight edge.

Punchthrough resetting jfet image sensor

Abstract: A solid-state picture pick-up device according to the invention comprises a number of field effect transistors in which the channel region is bounded by two oppositely located gate electrodes each forming a rectifying junction with the channel region and in which the photosensitive junction is formed by a gate electrode which shows a floating potential. Said gate electrode may be charged by simultaneously applying to the other gate electrode a voltage pulse of a sufficiently large amplitude so that punch-through occurs between the gate electrodes. Since in this manner each transistor may be adjusted at its own threshold voltage, the influence of the spreading in the threshold voltages on the output signals is considerably reduced.

Raised source and drain IGFET device and method

Abstract: Disclosed is an integrated circuit field effect transistor having a source and drain which protrude above the silicon substrate so as to create shallow junctions with the substrate while maintaining a relatively low sheet resistivity in the region. Two self-aligned source and drain fabrication processes are disclosed for the device. The first process yields a polysilicon field shield and the second process yields a field region composed of thermal silicon dioxide.

Substrate current-a device and process monitor

Abstract: Typical characteristics of an n-channel, enhancement-mode, insulated-gate field effect transistor (IGFET) are shown in Figure 1. The drain current is plotted against the drain voltage for different values of the gate voltage. It can be seen from the figure that, after saturation is reached, the drain current increases again as the drain voltage is further increased. This additional current is attributed to the substrate current and can be measured simultaneously in the substrate lead.

Temperature compensated voltage reference device

Abstract: A temperature compensated voltage reference device has a field effect transistor that is reverse biased at a particular operating point so that temperature Variation of the biasing voltage across the gate to source junction of the field effect transistor is substantially negated by a forward biased bipolar transistor that has a temperature dependent voltage across its base to emitter junction.

High power field effect transistor

Abstract: A field effect transistor is provided wherein conductive mesas are topped by source and drain electrodes, respectively, and rise out of a semiconductor epitaxial layer onto which there is formed a Schottky barrier layer. A heat sink metal layer backs the barrier layer and forms a gate terminal for control of flow of current between the source and drain electrodes via the epitaxial layer adjacent to the barrier.

New phenomena on drain‐to‐source breakdown voltage of n‐channel FET

Abstract: Drain‐to‐source avalanche breakdown voltage which continues to increase gradually (walkout) with increasing drain voltage turns back instantaneously and negative resistance characteristics appear in the drain current‐vs‐drain voltage curve when the drain avalanche current exceeds a critical value. These phenomena can possibly be attributed to turn on of the avalanche‐current‐induced n+p n+ bipolar transistor operation. Further the model postulates electron injection and neutralization of holes trapped during walkout.

Model and linear applications of the JIGFET (Junction and Insulated Gate Field-Effect Transistor)

Abstract: The JIGFET is a novel type of depletion MOS transistor formed by the implantation of a channel between source and drain. Because of its high bulk-transconductance, its linearity and low noise, the JIGFET has been thoroughly studied and modelled for linear applications. The model based on the depletion approximation has been found to be in good agreement with the solution of the Poisson's equation and the experimental results in both the depletion and the inversion regions.

High frequency field-effect transistors and method of making same

Abstract: A high frequency insulated gate field effect transistor comprises a semiconductor body of one type of conductivity, a base region of the same type of conductivity as the semiconductor body but with a higher impurity concentration than the body, and drain and source regions of the opposite type of conductivity. A portion of the base region is disposed between the drain region and the source region and the impurity concentration of the base region is reduced from the source region toward the drain region and is less at its junction with the drain region than that of the drain region. Such transistor can be incorporated in an integrated circuit as an amplifier transistor with a depletion type transistor as a load transistor. A common region serves both as a drain region of the amplifier transistor and a source region of the load transistor. A process of making the transistor and the integrated circuit comprises masking a semiconductor body, forming windows in the mask and successively diffusing through the same window both a first impurity to form the base region and a second impurity to form the source region.

Simple method of m.o.s.-transistor threshold-voltage measurement

Abstract: A method of m.o.s.-transistor threshold-voltage measurement is described. The method is based on the measurement of the time interval between the pulse that releases the linear voltage ramp applied to the transistor gate, and the pulse of the transient current resulting from the channel formation. This method is particularly useful for investigation of threshold-voltage instabilities.

Magnetic Sensitivity of Junction Field Effect Transistors with Uniform Channel Current Density

Abstract: MOS field effect transistors with two additional diffused contacts in the channel region were studied by Rao and Carr. The present work provides detailed theoretical analysis for an n-channel Junction Field Effect Transistor with a rectangular geometry. The variation of the Hall voltage with the drain to source voltage was plotted.