Showing papers on "Drain-induced barrier lowering published in 1975"

Theory of the MOS transistor in weak inversion-new method to determine the number of surface states

Abstract: The drain current I D versus gate voltage V G of an MOST operating in weak inversion, and the influence of surface potential fluctuations on this characteristic have been studied before [1], [2]. The purpose of this paper is to derive an expression of the drain current I D versus the drain voltage V D for devices with a channel length not smaller than 20 µm. It is demonstrated that the surface potential fluctuations do not affect the slope of the I D -V D curve, whereas the density N ss of surface states strongly influences the slope for small drain voltages. This yields a simple and useful technique to determine N ss on MOS transistors.

Properties of ESFI MOS transistors due to the floating substrate and the finite volume

Abstract: The specific current-voltage characteristics of epitaxial silicon films on insulator (ESFI®) SOS MOS transistors are shown, discussed in comparison to bulk silicon MOST's, and explained by the differences in geometrical considerations, charge distribution, and operation mode, The ESFI MOST's are produced on silicon islands, in most applications, the electrical substrate is at floating potential. This results in two effects. At first a threshold voltage change occurs with increasing drain voltage, producing a kink in the current curve; if the drain voltage further increases, a parasitic bipolar transistor begins to work and effects another kink or bend in the curve. On the other hand, the finite vo|ume effects a strong dependence of the base width of the parasitic bipolar transistor on the drain voltage and causes a rise of the current amplification with the drain voltage. The finite volume below the gate oxide also limits the bulk-charge magnitudes with subsequent increase in mobile carrier charge, thereby increasing the transconductance. All these effects are also described theoretically; the I D -V D characteristics could be simulated by computer model based on the physical effects.

Silicon on sapphire MOS transistor

Abstract: An MOS transistor constructed using silicon on sapphire technology in which the channel region can be electrically connected either to the source or drain terminal is disclosed. The transistor is advantageous in that the shift of the threshold voltage of the transistor in the presence of radiation is substantially decreased. Connecting the channel region of the transistor to the source terminal also substantially reduces what is normally referred to as the "kink" effect in MOS transistors utilizing floating substrate channel regions. Reducing the sensitivity to radiation and the kink effect results in a transistor having improved electrical characteristics.

Device design considerations for ion implanted n-channel MOSFETs

Abstract: Device design considerations are presented for ion implanted, n-channel, polysilicon gate, enhancement-mode MOSFETs for dynamic switching applications. A shallow channel implant is used to raise the magnitude of the gate threshold voltage while also maintaining a low substrate sensitivity (i.e., without substantially increasing the dependence of the threshold voltage on the source-to-substrate "backgate" bias). Design trade-offs between channel implantation energy and dose and substrate bias were examined using both computer analyses and experimental devices. The design objective was to identify the combination of these three parameter values that gives both a low substrate sensitivitya nd a steep subthreshold conduction characteristic under the conditions of a gate threshold voltage of 1 V and a substrate bias range of 0 to -1 V. One-dimensional and two-dimensional computer analyses were performed to predict the effect of the device parameters on the electrical characteristics. MOSFETs were then fabricated to investigate the extremes of the design parameter range, and the experimental and predicted device characteristics were compared. An enclosed device structure proved particularly useful in evaluating the subthreshold characteristic at very low values of drain current.

Influence of the channel width on the threshold voltage modulation in m.o.s.f.e.t.s

Abstract: The threshold vollage of an m.o.s. field-effect transistor is modulated by the source-to-substrate reverse bias. In the letter, the theory for long- and short-channel transistors is extended to include the influence of the channel width. The result is an analytical expression for the threshold voltage as a function of geometry and bias that agrees well with experimental data.

Field distribution in junction field-effect transistors at large drain voltages

Abstract: An analytical approximation to the field distribution in the channel portion between gate and drain of the junction field-effect transistor is derived, assuming an infinitely small channel width-to-height ratio, and modified for finite channel widths by introducing an effective impurity concentration which depends on drain current. The approximation is applicable also in the limiting case of zero gate edge curvature, i.e., for Schottky-barrier gate. The theoretical field distribution is used to extract impact-ionization coefficients from published experimental data on gate current enhancement at large drain voltages. These impact-ionization coefficients agree with published data derived from bulk impact ionization.

The “barrier mode” behaviour of a junction FET at low drain currents

Abstract: The behaviour of a junction FET with a gate-source reverse bias exceeding the pinch-off voltage is discussed. It is seen that both the transfer and output characteristics have an exponential character, and this is attributed to the presence of a potential barrier between the source and drain. Simple expressions are given for both the conductance and transconductance in terms of parameters which, in the case of long gate devices, may be evaluated analytically, or, in the case of short gate devices, evaluated numerically using a relatively simple computer model.

Charge cancelling structure and method for integrated circuits

Abstract: According to the invention, the electrical charge which is transferred to a circuit node by the switching ON or OFF of a field effect transistor whose source or drain is connected to that node is cancelled by connecting the source and drain of another field effect transistor to that circuit node and applying to its gate terminal a complement of the switching signal applied to the gate electrode of the first field effect transistor.

Threshold voltage characteristics of double-boron-implanted enhancement-mode MOSFETs

Abstract: Threshold voltage characteristics are presented for a double boron-ion-implanted n-channel enhancement MOSFET device for high speed logic circuit applications. A 15-Ω-cm high resistivity p-type (100) substrate was used to achieve low junction capacitance and low threshold substrate sensitivity. A shallow boron implant was used to raise the threshold voltage, and a second, deeper, boron implant was used to increase the punch-through voltage between the source and the drain. This design is especially beneficial for short channel devices, while maintaining the low junction capacitance and low threshold substrate sensitivity of the high resistivity substrate. A one-dimensional analysis was performed to predict the effects of ion implantation dose and energy on the device characteristics, and a quasi two-dimensional analysis was used to account for the short channel effect. The calculated results agree well with the behavior of experimental devices fabricated in the laboratory.

Negative impedance transistor device

Abstract: Transistor device exhibiting negative resistance characteristics includes an enhancement mode insulated gate field effect transistor interacting with an integral bipolar transistor. The transistor device has a bulk region separated from a shallow substrate region by a pn-junction located in proximity to source and drain regions of the field effect transistor. The source region also serves as the emitter, the substrate region serves as the base, and the bulk region serves as the collector of the integral bipolar transistor wherein the substrate base is left floating. Normally, the collector of the bipolar transistor is connected to the gate of the field effect transistor, and a resistor of finite value is included in the gate circuit. Oscillator, astable multivibrator, gated oscillator, gated astable multivibrator, and bistable multivibrator circuits are illustratively constructed with the transistor device.

Junction field effect transistor of vertical type

Abstract: A junction field effect transistor of a vertical type having: a drain region having a first conductivity type; a gate region composed of branches formed on said drain region by a selective vapor deposition or liquidous phase deposition method and having a second conductivity type opposite to the first conductivity type of the drain region, at least that surface of each of the branches of the gate region which locates on the side opposite to the drain region side being covered with an insulating layer; and source regions formed between the respective branches of the gate region by conducting a further growth of said drain region. This field effect transistor has a sufficiently reduced area of P - N junction between the gate region and the respective source regions, resulting in a marked reduction in the junction capacitance. Besides, the insulated gate region with respect to the source regions give rise to a high gate-to-source breakdown voltage property.

Compound transistor circuitry

Abstract: A compound transistor circuitry having an output characteristic resembling that of a pentode vacuum tube comprises: a first field effect transistor having a saturated-type output characteristic resembling that of a pentode vacuum tube; and a second field effect transistor having an unsaturated-type output characteristic resembling that of a triode vacuum tube. The first and second field effect transistors have a conducting channel of a single and same conductivity type, respectively. The second field effect transistor is connected in series with the drain current path of the first field effect transistor. This second field effect transistor is rendered conductive only when the drain-source voltage of the first field effect transistor exceeds its pinch-off voltage.

Non-volatile memory cell and array using substrate current

Abstract: A non-volatile read mostly memory cell in a monocrystalline semiconductor body wherein the sensing of the information is achieved by measuring the substrate current. The cell includes spaced source and drain regions, a gate dielectric layer capable of trapping a charge, a substrate contact electrode; a means to induce a trapped charge into the gate dielectric layer, including a means to apply a voltage larger than the threshold voltage to the gate electrode to form an inversion layer, and a means to apply a voltage to the drain electrode causing channel current to flow; a means to remove the trapped charge, including a means to apply a voltage equal to or exceeding the avalanche voltage to the drain to cause avalanching; a means to determine the presence or absence of a charge in the gate dielectric including a means to apply a voltage to the gate which is larger than the threshold voltage and a voltage to the drain that is significantly less than the avalanche voltage, and a means to determine the substrate current.

Field effect transistor having improved threshold stability

Abstract: FIELD EFFECT TRANSISTOR HAVING IMPROVED THRESHOLD STABILITY Abstract of the Disclosure An improved field effect transistor device in a monocrystalline semiconductor body provided with source and drain regions and a gate electrode disposed over the channel between the source and drain regions wherein at least the drain region is formed of a first region where the impurity concentration increases with depth with the peak concentration being spaced inwardly from the major surface, and a second region located within the first region having a peak impurity concentration at the major surface. The drain region structure in operation promotes the current flow between the source and drain to flow deeper in the channel region and spaced from the gate dielectric layer. In the method for forming the field effect transistor, an impurity is introduced into the semi.-conductor body underlying at least the ultimate drain region, an epitaxial semiconductor layer deposited, and a second impurity region formed over the first region to form the drain contact. In an alternate embodiment of the method for forming a field effect transistor, a first ion implanta-tion is formed in the drain region, such that the peak impurity concentration is located well within the body spaced from the surface thereof, and a second ion implantation, or diffusion, performed forming the source and also the ohmic contact for the drain which is located over the first region and within the first implanted region.

Theoretical influence of surface states and bulk traps on thin film transistor characteristics

Abstract: It is shown that the theoretical derivation of drain current versus drain voltage characteristics of thin film transistors (TFT) is obtained, in the gradual channel approximation, by integration of the conduction electron charge versus gate voltage curve. The influence of bulk traps and surface states on these curves is evaluated quantitatively by using specific models. It is shown that at high donor concentrations, bulk traps have much more influence on TFT characteristics and even make it difficult to obtain good characteristics. At low donor concentrations, surface states have more influence but still allow good characteristics except at unusually high concentrations. Finally, the importance is shown of measurements of the channel conductance at low drain voltage as a function of the gate voltage for gaining insight in the physical parameters that determine TFT behavior.

Low transient effect switching device and method

Abstract: A P-channel MOS double gated transistor is provided with an electrical shield element located between the drain and the second gate. The shield is electrically connected to the first gate and is dc biased by the first gate control voltage at FIRST GATE SELECT. The presence of the first gate control voltage causes all the shield capacitances to charge and causes a depletion region between the shield and the drain. Prior to SECOND GATE SELECT, the electrical transient effects of activating the shield with a dc bias have expired. SECOND GATE SELECT introduces new transients (noise current), noteable charging of the capacitance between the drain and the second gate and formation of the final section of depletion region proximate the second gate completing the P channel. This capacitance is drastically reduced by the intervening shield, and the depletion transient is minimized by the priming depletion region established by the shield voltage.

Capacitive means for controlling threshold voltages in insulated gate field effect transistor circuits

Abstract: Circuit means for eliminating the effect of excessive threshold voltages in insulated gate field effect transistor inverter-type circuits utilizes capacitor pull-up. Capacitors are selectively coupled from various phased voltage outputs of a multi-phase voltage supply to the driver-gate of various field effect transistors to provide increased voltage during voltage pulses of the phase involved. A voltage between the threshold voltage and a required minimum noise margin is thereby added to the driver-gate input signal to overcome the threshold voltage effect. This circuit means is particularly useful in dynamic circuits such as multiphase shift registers and bipolar-to-high voltage field effect transistor coupled circuits.

Negative resistance integrated circuit - has two MOS FET's with specified gate connections for switching nide change-over

Abstract: The complementary metal-oxide-semiconductor technology is used to produce an integrated circuit with a negative resistance characteristic under voltage application to a given circuit region. A metal-oxide-semiconductor transistor of a first channel type has its gate connected to the switching nodes and its source-drain path in series with a load to operating voltage source. A second such transistor of opposite channel type has its source-drain path connecting the switching node to the operating voltage source terminal, coupled to the load. This second transistor gate is connected to the junction point of the load and the first transistor. Thus the application of a voltage to a given region at the switching node the source-drain path of the second transistor becomes conductive.

Negative resistance network

Abstract: This negative resistance network includes a first predetermined channel insulated gate enhancement type field effect transistor having a drain-source path connected to positive and negative input terminals on which a predetermined input voltage is impressed. The gate potential of the first field effect transistor is controlled by a second insulated gate enhancement type field effect transistor having an opposite channel type to the first field effect transistor, a gate connected to the drain thereof which is connected to the predetermined one of the positive and negative input terminals and a source connected to one pole of a dc power supply having a predetermined voltage, and by a third insulated gate enhancement type field effect transistor having the same channel type as the first field effect transistor, a drain and a gate connected to the drain of the second field effect transistor as well as to the gate of the first field effect transistor and a source connected to the source thereof which is connected to the other input terminal as well as to the other pole of the dc power supply, whereby the first field effect transistor shows a negative resistance characteristic attaining a relatively low current consumption over a relatively wide level range of the input voltage.

Method of manufacturing a semiconductor integrated circuit device which includes at least one V-groove jfet and one bipolar transistor

Abstract: A method of manufacturing a semiconductor integrated circuit device, which includes at least one junction field-effect transistor and at least one bipolar transistor, is characterized in that a groove portion is formed by chemically etching a part of a diffused layer for the channel region of the junction field-effect transistor, and that a layer for the gate of the junction field-effect transistor having a conductivity type to opposite to that of the channel region is formed by diffusion in the diffused layer of the channel region beneath the groove portion, whereby the pinch-off voltage V p of the junction field-effect transistor is made as small as possible and is also made smaller than the base-emitter reverse withstand voltage V BEO of the bipolar transistor.

Compound field effect transistor

Abstract: A horizontal junction-type field effect transistor having a saturated drain current to drain voltage characteristic and constituting an input transistor and a vertical junction-type field effect transistor having an unsaturated drain current to drain voltage characteristic and constituting an output transistor are connected in cascode fashion to compose a compound field effect transistor. This compound field effect transistor has a saturated characteristic, a high transconductance gm and a high breakdown voltage resembling those of a pentode vacuum tube. This compound field effect transistor is constructed in the form of monolithic integrated circuitry by the combined use of the dielectric isolation technique utilizing mesa groove and the pn-junction isolation technique.

Self-scanning photo-sensitive circuits

Abstract: High density self-scanning photo-sensitive circuits employ a voltage transfer mode with charge amplification. The circuits include a field effect transistor and a capacitor coupled from the gate electrode of the transistor through a diode to the source electrode of the transistor. A photodiode is connected to the gate electrode of the transistor. Means are provided for precharging the capacitor to substantially the threshold voltage of the transistor while applying an additional constant voltage of predetermined magnitude to the gate electrode to operate the transistor in its linear region. An analog signal from the photo-diode is also applied to the gate electrode of the transistor which is amplified by the transistor with little or no threshold voltage loss. In a preferred array of these circuits, the photo-diodes or light sensitive devices are arranged linearly, in quantities of a thousand or more, and video signals from alternate devices are coupled to one or two common busses through individual gating transistors.

Method and system of driving power field effect transistor

Abstract: A method and a system of obtaining a large power with the use of a junction field effect transistor by extending the working range to improve the utilization rate of the power source voltage. The range for the gate voltage is set up to some predetermined forward voltage at which the gate and the source will be subjected to a forward biasing. The source-to-drain internal resistance is reduced by this forward gate voltage, but no gate current is allowed to flow probably due to the existence of a non-linear element between the gate and the source.

TFT characteristics with distributed traps in the semiconductor

Abstract: The development and solutions for the current-voltage drain characteristics of a TFT with exponentially distributed trapping centers in the semiconductor are presented. The development involves rederiving the current-voltage characteristic equation considering the dependence of carrier mobility upon trapping centers. The solutions provide insight regarding the drain current characteristics. The drain current with traps is found to be more dependent on the gate voltage than the trapless case and this dependence is a function of the steepness in the trap concentration. It is observed that a significant change in the shape of the drain characteristics near the knee region is caused by traps. Also the magnitude of the drain current is very dependent on the concentration and steepness of traps. Finally, the general expression for drain current dependence on temperature is found to be in good agreement with CdS experimental data.

Method of adjusting the threshold voltage of field effect transistors

Abstract: A method of adjusting the threshold voltages of field effect transistors, in particular of SCHOTTKY gate field-effect transistors, is provided. During the process of manufacture of the transistor, the channel charge carrier density is modified by ion implantation. A monitoring device, in the form of a test transistor, is manufactured at the same time as the production transistors and on the same wafer thereas. An appendix of the test transistor makes it possible to measure the threshold voltage and saturation current, during ionic implantation.

Static characteristics of extremely thin gate oxide m.o.s. transistors

Abstract: The drain current of an extremely thin gate oxide m.o.s. transistor shows an exponential dependence both on drain voltage and gate voltage, even in the `postthreshold? region. The input gate current of a device with 20 A gate oxide is estimated to be negligible for a logic-circuit operation with 0.2 V supply voltage.

An improved 1/f noise model of an MOS transistor

Abstract: An improved 1/f noise model of an MOS transistor is developed which verifies previously observed dependencies on geometry and the density of surface states (N SS ) but predicts an explicit bias dependence in addition to the dependence brought out by the change of N SS with bias. The model is an extension of the tunneling mechanism proposed by McWhorter in which carriers in the channel tunnel into and out of traps distributed in the oxide. The essential difference between this work and previous work is in the assumed transformation between the fluctuation in the number of trapped carriers and the resulting fluctuation in the drain current. The improved noise model results in the experimentally verified prediction that noise gradually decreases as the drain bias increases until saturation is reached. In addition, the improved noise model predicts a definite gate bias dependence of 1/f noise, increasing as the gate voltage decreases to threshold and below and increasing as the gate voltage increases well above threshold.

High frequency, field-effect transistor

Abstract: A high frequency, Schottky barrier gate, field-effect transistor is provided with a substantially constant impedance over a broadband of frequencies. The transistor is comprised of a thin dielectric layer providing an effective dielectric constant at gate and drain contacts greater than √2. The dielectric layer is supported on the major surface of a conductor substrate, and is preferably 5 microns in thickness and has a dielectric constant greater than about 5. The transistor is also comprised of a thin semiconductor layer of less than about 2 microns in thickness at least at gate portions with an N-type concentration of between about 5 × 10 14 and 5 × 10 17 carriers/cm 3 . The gate contact of the transistor is an elongated Schottky barrier contact adjoining the semiconductor layer spaced between elongated source and drain contacts which make ohmic contact with the semiconductor layer. Means are also provided to maintain the source contact at substantially the same RF potential as the conductor substrate.

A five-parameter model for current and cross modulation in field-effect transistors with high drain voltage

Abstract: A new five-parameter model for the behavior of field-effect transistors with high drain voltage has been developed. The resulting single expression is shown to predict the drain-current-gate-voltage characteristics of a variety of devices with an accuracy of ±0.002 V over many decades of drain current. Several methods for the evaluation of model parameters are discussed. The effect of temperature is successfully included in the model in one case. Cross-modulation characteristics can be calculated which are in qualitative agreement with measurements.

VDS voltage capabilities of a diffused j.f.e.t. with a vertical-channel arrangement

Abstract: In the letter, it is shown that the VDS voltage limitation in a jfet with a vertical-channel arrangement in the off state is due, not to the breakdown voltage of the gate-drain junction, as for a classical jfet, but to the field-effect lowering of the potential barrier created in the channel by the polarisation of the gate The analysis is based on the 2-dimensional numerical solution of the general semiconductor equations