Showing papers on "Drain-induced barrier lowering published in 1977"

Effect of electron trapping on IGFET characteristics

Abstract: At large applied voltages, electrons flowing from the source to the drain of a n-channel insulated-gate field-effect transistor (IGFET) may gain sufficient energy from the high-field region near the drain to be emitted into the gate insulator layer near the drain junction. The trapping of these hot electrons in the gate insulator results in transconductance degradation and/or threshold voltage shift. There is also evidence of surface-state generation resulting from hot-electron emission into the SiO2 layer. The extent of the resultant transconductance degradation and/or threshold shift depends strongly on the electron trapping characteristics of the gate insulator. For devices having SiO2/Si3N4 as gate insulator, electron trapping is completely dominated by the Si3N4 layer. In this case, channel hot-electron effect results in threshold shift alone. For devices having SiO2 as gate insulator, the trapping characteristics depend on its positive oxide-charge concentration. In this case, channel hot-electron effect results in a combination of transconductance degradation and threshold shift.

Insulated gate field-effect transistor read-only memory array

Abstract: An array of read-only memory cells is formed from a plurality of insulated gate field-effect transistors. Information may be programmed into individual transistors within the array by application of selected potentials to the connecting lines of the array. An individual cell is programmed by causing some of the electrons flowing between the source and drain to acquire sufficient energy to be injected into and trapped in the insulating material separating the channel from the gate electrode. The trapped electrons cause a change in the current-voltage characteristics of the transistor, which may be detected during reading of the memory cell most easily by reversing the polarity of the source and the drain. Embodiments of such an array are shown and may be utilized as a ROM, PROM and EPROM.

Voltage detection circuit composed of at least two MOS transistors

Abstract: A voltage level detection circuit comprises a first MOS transistor having the gate and the drain connected together with a power source voltage V DD via a resistor and the source grounded and a second MOS transistor having the gate connected with the drain of the first MOS transistor and the source grounded via a resistor. The circuit functions to compare the power source voltage V DD with a sum of the threshold voltage levels of the first and second MOS transistors, whereby voltage detection outputs are developed at the source of the second MOS transistor.

Method of making an insulated gate field effect transistor by implanted double counterdoping

Abstract: An insulated gate field effect transistor having spaced highly doped source and drain regions with less highly doped source and drain extensions, which define the ends of the channel of the transistor, has both the source and drain extensions and the channel of the transistor defined in a controllable manner by the steps of forming a continuous zone of the same conductivity type as the source and drain regions in the space between these two regions and then counterdoping a portion of this layer.

A field effect transistor logic gate having depletion mode and enhancement mode transistors

Abstract: A logic gate having a first depletion mode field effect transistor with a gate electrode adapted for coupling to a control signal source, a second depletion mode field effect transistor and an enhancement mode field effect transistor, such enhancement mode field effect transistor being serially connected to the second depletion mode transistor. The second depletion mode transistor and the enhancement field effect transistor are fed by the first depletion mode transistor. One of such serially connected transistors has a Schottky gate contact. With such arrangement the logic gate includes a "complementary" pair of relatively short channel length devices fed by a relatively short channel length device to provide low static power dissipation and large output capacitance drive capability.

Insulated gate field effect transistor having a deep channel portion more highly doped than the substrate

Abstract: The source and drain of an N-MOSFET can be brought closer together without substantially increasing capacitance and punch-through effects, by using a very high resistivity P-substrate, a moderately high resistivity P- type region in the channel zone and a thin but low resistivity surface-adjacent channel portion through which current flows. The P- type region and the surface-adjacent channel portion are ion-implantations. The P- type region extends deep enough into the substrate to shield the source from electrostatic coupling with the drain. Diffused, low reactance integrated circuit resistors can be made using the same principles.

Field effect transistor having a surface channel and its method of operation

Abstract: A field effect transistor includes a semiconductor substrate of a first conductivity having a source zone and a drain zone of an opposite, second conductivity spaced apart therein and extending to the surface thereof. A surface channel adjoins the surface, is of the second conductivity, and extends in an area located between the source and drain zones. A gate electrode is carried above the surface channel, either on an insulator, or directly on the surface to form a Schottky junction. A second zone lies beneath the surface below or in overlapping relation to the surface channel and extends between the drain and source zones. The second channel is doped with dopant particles whose energy level in the forbidden band of the semiconductor substrate, at an operating temperature T, lies at a distance of more than 1/2 kT from the conduction band edge and valence band edge of the semiconductor substrate. Application of proper potentials with respect to the start voltage required for ionization of the dopant particles in the second channel causes the field effect transistor to function as a high-speed switch. Connection of the field effect transistor in series with a resistance between the poles of a power supply which has a voltage greater than the start voltage causes the field effect transistor to operate, in combination with the resistor, as an oscillator.

A simple approach for accurately modeling the threshold voltage of short-channel mosts

Abstract: We present a theory which models short-channel effects in MOS transistors (MOST) Our approach accounts for the effects of the source and drain depletion regions on the energy band configuration and the effective depletion layer charge under the channel We derive an equation for low drain bias threshold voltage which accurately predicts the measured threshold on devices ranging in size from very small (15 μm) to very large (100 μm) effective channel lengths The equation reliably predicts the phenomenon of decreasing threshold voltage and body effect observed experimentally from devices of decreasing channel length The equation is valid for any bulk silicon MOS technology provided that the substrate doping is approximately uniform (ie ion-implantation has not been used to adjust the threshold) Our approach can be applied directly to the modeling of the short-channel drain to source current This application of the theory will be presented in a later paper

Gate controlled diode protection for drain of IGFET

Abstract: An integrated circuit includes an insulated-gate field effect transistor and a protection device coupled to either the source or drain of the transistor. The protection device includes a gate-controlled diode having a breakdown voltage that is less than the breakdown voltage of the drain of the field effect transistor.

Method and apparatus for driving a transistor operated in saturation

Abstract: A method and apparatus for driving a transistor wherein a control voltage and a cut-off voltage are applied to the base of the transistor to cause the transistor to conduct current and to cut-off, respectively, and wherein, preceding the application of the cut-off voltage, a further voltage is applied to the base of the transistor for a predetermined desaturation time interval Δt which depends upon the storage or delay time of the transistor. In accord with the invention, the aforesaid further voltage corresponds to the voltage at which the current at the base of the transistor is approximately zero.

Floating gate solid-state storage device

Abstract: A floating gate semiconductor device is described wherein the floating gate member does not extend completely across the channel region and thus avoids alignment with the edges of the source and drain regions. The lateral displacement of the edge of the floating gate from the drain region permits stored charge on the drain to be undisturbed in the event avalanche breakdown occurs at the channel-drain junction.

Field effect transistor having a linear attenuation characteristic and an improved distortion factor with multiple gate drain contacts

Abstract: A field effect transistor having two electrodes and distributed resistance therebetween is disclosed. This device is used as an attenuator when a main signal is applied across one drain electrode and a source and a control voltage is applied between a gate and the source. The output is derived from the other drain electrode.

Drain-voltage dependence of IGFET turn-on voltage

Abstract: The turn-on voltage (or threshold voltage) characteristic of an enhancement-type insulated-gate field-effect transistor (IGFET) in its pentode operation region, is analyzed based on a simple model. A new definition for the turn-on voltage at just-saturated state is given and a new simple formula for the turn-on voltage shift in IGFETs pentode operation region, is deduced. This assumes a reduction of gate-induced bulk charge under the influence of the drain voltage. Agreement of the theory with experiment is good.

Self-excited mixer circuit using field effect transistor

Abstract: A self-excited mixer circuit using a dual gate type field effect transistor, in which an inductive impedance element inductive with respect to a local oscillation frequency, a first capacitive element and a second capacitive element are connected across the drain and the second gate, across the drain and the source, and across the second gate and the source, respectively, of field effect transistor to constitute an oscillation circuit across the drain and the second gate of transistor, so as to derive an intermediate frequency signal from the drain of the transistor in response to the application of the radio frequency signal to the first gate of transistor.

Short-channel V-groove complementary MOS device

Abstract: An improved short-channel complementary MOS transistor structure is provided. The problems of low punch-through voltage breakdown, and "short-channel effects" are particularly addressed and solved. Accurate and precise field protection of all area surrounding the channel, source and drain regions of both the p-channel MOS transistor device and the n-channel transistor device is simply and effectively accomplished. The threshold voltage of the n-channel MOS transistor device is precisely controlled by a boron implantation. The method of manufacturing such device is disclosed.

Composite channel field effect transistor and method of fabrication

Abstract: An improved composite channel field effect transistor and method of fabrication, which exhibits high density characteristics and yields high performance with less sensivity to threshold shift due to hot electrons when operated at high source to drain voltage levels.

Junction field effect transistor having unsaturated drain current characteristic with lightly doped drain region

Abstract: A field effect transistor has the property that the product of its series resistance and its true transconductance is less than one throughout the entire range of drain voltage in the operative state of the transistor, the series resistance being the sum of the resistance from source to channel and the resistance of this channel. In order to prevent an excessive increase in the active resistance of the channel, the channel is made to have an impurity concentration as low as less than 1015 atoms/cm3, preferably less than 1014 atoms/cm3, so that the depletion layers extending from the gates grow extensively to become contiguous in response to a small increase in the reverse gate voltage applied. As a result, the field effect transistor of this invention has an unsaturated drain current versus drain voltage characteristic.

Damage Introduced by Second Breakdown in N -Channel MOS Devices

Abstract: Failures in an N-channel MOS device as a result of electrical overstress are discussed in terms of "second breakdown transition".1,2) In the second breakdown state, large power, as much as 500–5,000 mW, is dissipated in the drain depletion layer. The power dissipation leads either to aluminum migration from the gate electrode to the substrate through the gate oxide or to the degradation of transistor properties. Most of the aluminum migration occurs in a localized area of the substrate surface, where the depletion layer of the drain region extends widely. The second breakdown transition in an N-channel MOS device is attributable to minority carrier injection from the source region to the substrate and to an increase in the impact ionization current in the drain depletion layer. The critical drain voltage of the second breakdown transition depends on the source-substrate bias, the substrate resistivity, the channel length and the gate voltage.

The early voltage of a bipolar transistor

Abstract: A simple concentration profile is assumed and the Early voltage of a p-n-p transistor is calculated. The base gradient, the current gain, and the collector resistivity appear as parameters in the final equation for the Early voltage. Experimental results are presented.

Epitaxial process for the fabrication of a field effect transistor having improved threshold stability

Abstract: An improved field effect transistor device in a monocrystalline semiconductor body provided with source and drain regions and a gate electrode disposed over the channel between the source and drain regions wherein at least the drain region is formed of a first region where the impurity concentration increases with depth with the peak concentration being spaced inwardly from the major surface, and a second region located within the first region having a peak impurity concentration at the major surface. The drain region structure in operation promotes the current flow between the source and drain to flow deeper in the channel region and spaced from the gate dielectric layer. In the method for forming the field effect transistor, an impurity is introduced into the semiconductor body underlying at least the ultimate drain region, an epitaxial semiconductor layer deposited, and a second impurity region formed over the first region to form the drain contact. In an alternate embodiment of the method for forming a field effect transistor, a first ion implantation is formed in the drain region, such that the peak impurity concentration is located well within the body spaced from the surface thereof, and a second ion implantation, or diffusion, performed forming the source and also the ohmic contact for the drain which is located over the first region and within the first implanted region.

CCD output circuit using thin film transistor

Abstract: Compact, low-capacitance output circuit for charge coupled device (CCD). The circuit includes a semiconductor electrode which is doped at opposite edges thereof to form the source and drain regions, respectively, of a thin film transistor. The conduction channel of the transistor is the region of the semiconductor electrode between the source and drain regions. The gate electrode of the transistor is the region of the substrate adjacent to the conduction channel and the input signals comprise the packets of charge shifted to this substrate region by the multiple phase voltages which operate the CCD.

Temperature compensated constant current MOS field effective transistor circuit

Abstract: There is provided a MOS field effect transistor circuit comprising a negative power terminal, an N-channel type field effect transistor with the substrate coupled to the negative power terminal, a diode coupled in the forward direction between the negative power terminal and the gate of the N-channel type field effect transistor, and a high-resistance resistor coupled between the junction of the diode and the gate of the N-channel type field effect transistor and an earth terminal. The variation in the threshold voltage of the N-channel type field effect transistor owing to temperature change is compensated by variation in the forward voltage of diode with the temperature change to keep constant the voltage applied to the gate of the field effect transistor, thereby securing the constant current property of the field effect transistor for temperature change.

A one-dimensional theory on the effects of diffusion current and carrier velocity saturation on E-type IGFET current-voltage characteristics

Abstract: Current-voltage characteristics of an enhancement-type insulated gate field-effect transistor (E-type IGFET) are analyzed based on a one-dimensional model, taking account also of the diffusion current component. Explicit formulae for the entire I-V characteristic curve are given. The solution for the triode characteristic shows considerable deviation from “drift current theory” in terms of turn-on voltage (or threshold voltage) and drain voltage at just saturation. The solution for the pentode characteristic taking account of carrier's saturation velocity, shows that the increase in drain current per unit drain voltage is larger in short-channel devices than in long-channel devices. Agreement with experiment is very good.

Constant current semiconductor circuit arrangement

Abstract: A constant current source is provided by a circuit of two metal oxide semiconductor field effect transistors (MOSFET) of the enhancement type having opposite conductivities. One transistor constitutes an input transistor. The other transistor is the output transistor. The drain terminals are connected to the respective polarities of an operating voltage source. The gate terminal of the input transistor is connected to a control voltage source. The source terminals are interconnected and grounded through a resistor. The constant current is available at the drain electrode of the output transistor. If it is desired to produce constant output currents of alternating directions, two such circuits may be interconnected in mirror symmetrical fashion.

Bucket brigade device and process

Abstract: The invention is the structure and process for making a bucket brigade device which comprises the merger of an MOS capacitor with an MOSFET device to form the charge transfer cell. A thin n-type region is implanted in a portion of the p-type channel region of an FET device adjacent to the drain diffusion. This structure increases the charge transfer efficiency for the cell and reduces its sensitivity of the threshold voltage to the source-drain voltage. The gate for the device has a substantial overlap over the drain and a minimal overlap over the source and the gate to drain capacitance per unit area is maximized by maintaining a uniformly thin oxide layer across the gate region.

Depletion/enhancement mode FET logic circuit

Abstract: Disclosed is a field effect transistor (FET) logic circuit which advantageously combines enhancement and depletion mode field effect transistors. A depletion mode input transistor is connected between an input node and an intermediate node and has its gating electrode connected to a fixed potential such as ground. A self-biased depletion mode field effect load transistor is connected between a positive potential and the same intermediate node to which the gating electrode of one or more enhancement mode field effect transistors are also connected. The source electrodes of the enhancement mode field effect transistors are connected to a fixed source of potential such as ground while the drain electrodes of the enhancement mode field effect transistors provide open drain outputs to similarly constructed subsequent logic stages. A number of these open drain logic outputs may be connected together to form DOT logic configurations and the potential swing at these open drain outputs, being a function of the threshold voltage of the subsequent stage input device, is substantially less than the potential difference between the fixed positive and ground supply potentials.

A short channel MOSFET model

Abstract: The MOSFET equivalent circuit model described incorporates short channel and temperature effects. It includes expressions for the device current in the subthreshold, triode and saturation regions and uses a field dependent mobility and a drain voltage dependent threshold voltage. The drain current-voltage characteristic and its first derivative are continuous in all regions. Relationships for the gate-source and gate-drain capacitances are derived as a function of the device potentials using a field dependent mobility. Using the closed form expressions of this model, simulations were performed for micron long devices having uniform and ion-implanted channel profiles and compared with data at room, above room and liquid nitrogen temperature.

Signal mixer including resistive and normal gate field-effect transistor

Abstract: A mixer comprises a MOS transistor having an ideal quadratic characteristic The transistor is of the D-MOST type and comprises a resistive gate across which a voltage drop is applied transversely to the longitudinal direction of the channel The adjustment point of the transistor is chosen to be so that the range of the gate voltages between the threshold voltage and the voltage at which the slope reaches the saturation value is always situated during operation within the voltage drop across the gate electrode The signals to be mixed are introduced capacitively via a second gate electrode situated above the resistive gate electrode and capacitively coupled therewith

Junction type field effect transistor

Abstract: A junction type field effect transistor comprises a source region and a drain region extending into a semiconductor body further than the channel region and a gate region located entirely within the channel region between the source and drain regions, leaving an exposed external surface. The invention also includes a method of making such a transistor.

Narrow channel field effect transistor

Abstract: a field effect transistor having a channel width of such small dimension that threshold voltage becomes inversely related to channel width allowing the fabrication of field effect transistors of differing threshold voltages while using the same process steps. Reduced threshold voltage due to prior art "short channel length" effect may be offset by the presently disclosed narrow channel width effect. Desired chanel impedance values are achieved independently of threshold voltage influence due to narrow channel width effect by the provision of parallel-connected field effect transistors of the same channel length whose total channel widths yield a desired net width-to-length ratio.