Showing papers on "Drain-induced barrier lowering published in 1978"

A charge-sheet model of the MOSFET

Abstract: Intuition, device evolution, and even efficient computation require simple MOSFET (metal-oxide-semiconductor field-effect transistor) models. Among these simple models are charge-sheet models which compress the inversion layer into a conducting plane of zero thickness. It is the purpose of this paper to test one such charge sheet model to see whether this approximation is too severe. This particular model includes diffusion which is expected to be important in the subthreshold and saturation regions. As a test the charge sheet model is applied to long-channel devices. Long-channel MOSFET behavior has been thoroughly studied, and is very well explained by the Pao-Sah double-integral formula for the current. Hence, a clear-cut test is a comparison of the charge sheet model with the Pao-Sah model. We find the charge sheet model has two advantages over the Pao-Sah model. (1) It leads to a very simple algebraic formula for the current of long-channel devices. The same formula applies in all regimes from subthreshold to saturation. Neither splicing nor parameter changes are needed. No discontinuities occur in either the current or the small-signal parameters, or in the derivatives of the small-signal parameters. (2) It is simpler to extend the charge sheet model to two or three dimensions than the Pao-Sah model. This simplification is a result of dropping the details of the inversion layer charge distribution. An important aspect of the gradual channel approximation is brought out by the analysis. Suppose the boundary condition relating the quasi-fermi level at the drain, φfL, to that at the source, φfo, namely φ ƒL =φ ƒ0 +V D where VD is the drain voltage, is applied in all bias regimes. Then it is shown that this means the potential at the drain end of the channel, φsL is not related to the potential at the source end of the channel, φso, by φ sL =φ s0 +V D Instead, φsL is computed, not imposed as a boundary condition. It is suggested that this failure of the potential to satisfy the boundary condition at the drain is justifiable. That is, φsL should be reinterpreted as the potential at the point in the channel where the gradual channel approximation fails. Hence, (2) may be relaxed. However, the “channel length” in the gradual-channel approximation now becomes a fitting parameter and is not the metallurgical source-to-drain separation. In addition several aspects of the long-channel MOSFET are brought out: (1) Pinch-off is achieved only asymptotically as the drain voltage tends to infinity. This is in marked contrast to the often-stated, textbook view that pinch-off is achieved for some finite drain voltage, the saturation voltage. (2) The channel or drain conductance approaches zero only asymptotically. (3) The transconductance saturates only asymptotically. Figures comparing the simple charge-sheet model formulas with the usual textbook formulas are included for direct-current vs drain voltage, channel conductance vs drain voltage, and transconductance vs drain voltage. The charge-sheet model agrees with the original Pao-Sah double-integral formula for the current at all gate and drain voltages, and possesses the correct subthreshold behavior. The textbook formulas do not.

Subthreshold conduction in MOSFET's

Abstract: The dependence of channel current in subthreshold operation upon drain, gate, and substrate voltages is formulated in terms of a simple model. The basic results are consistent with earlier approaches for long-channel devices. For short-channel devices, the variation of current with drain voltage up to the punch-through voltage is accurately described. The threshold voltage of a short-channel device as a function of applied voltages follows as a natural result of the derivation. Results are presented which confirm the theory over a wide range of drain and gate voltages. With the application of substrate bias it is concluded from the data and the theory that two-dimensional effects can cause dramatic increases in the drain conductance.

Light emission and burnout characteristics of GaAs power MESFET's

Abstract: In order to obtain information on the field distributions and weak places of GaAs power MESFET's, the light emission and pulse burnout characteristics were investigated. Their dependence on the drain structure was also studied. The light emission occurs at the drain edge of the active region when the gate bias is zero volt, slightly changing its place depending on the drain structure. The drain edge of the epitaxial layer was also damaged by the pulse burnout experiments at zero gate bias. When the gate bias is increased, the light emission at the drain edge decreases rapidly until the gate Schottky breaks down and begins to give the light emission at the gate edge. The pulse burnout experiments suggest that the burnout initiates inside of the active or buffer epitaxial layer when the gate bias is near the pinchoff voltage.

Optimization of nonplanar power MOS transistors

Abstract: Analysis of fundamental MOSFET parameters predicts device limits in high-voltage high-speed operation that exceed the performance of bipolar devices. The optimization of voltage, speed, and "on" resistance parameters for power MOSFET's suggests a vertical three-terminal device design with short, wide channels; a wide, lightly doped drain region; and field terminator rings at the device perimeter. Utilizing this design philosophy, VMOS transistors have been produced with source-drain breakdown voltage greater than 450 V, and 5.5-Ω "on" resistance for 2.0-mm2active area. With a high channel width packing density design and 2.5-mm2active area, a 30-V transistor has also been produced having only 0.060-Ω "on" resistance. The breakdown voltage and "on" resistance of these devices exceed the performance of other power MOSFET's currently available. Also, the switching speed of these devices (better than 15 ns) far exceeds the performance of high-voltage bipolar transistors. Measurements of drain leakage current at 200-V drain potential show a resistance ratio R_{off}/R_{on} of approximately 1010for a 20-V variation in gate-to-source voltage.

Method for fabricating transistor structures having very short effective channels

Abstract: A method, including a sequence of process steps, for fabricating insulated gate field effect transistors having very short effective channel lengths. In a first version of the method, the source and drain regions of the device are opened in one process step and self-alignment of the source and the drain to the gate is achieved in one masking step. The drain region is then masked and the source side of the channel is implanted to adjust the threshold voltage of the high threshold voltage channel region. In a second version of the method, the source region is opened and self-aligned with the gate prior to the opening of drain region. Implantation to adjust the threshold voltage of the high threshold voltage channel region takes place before the drain region is opened, and then the drain region is opened and self-aligned with the gate in a further masking step. In either version, the threshold voltage is adjustable and the channel length is controlled to be a small value.

Insulated-gate field-effect transistor with self-aligned contact hole to source or drain

Abstract: An oxide dielectric layer is interposed between the polysilicon gate and the contact hole to the source or drain of an insulated-gate field-effect transistor to prevent electrical shorts between the gate and metal contact to the source or drain. The oxide dielectric layer enables the contact hole to be extremely close to the polysilicon gate without electrical shorts occurring therebetween, thereby eliminating the need for a minimum separation between the gate and contact hole.

Static induction transistor

Abstract: In a static induction transistor of the type wherein carriers are injected from a source region to a drain region across a potential barrier induced in a current channel, and wherein the height of the potential barrier can be varied in response to a gate bias voltage applied to a gate to thereby control the magnitude of a drain current of the transistor. The product of the channel resistance R c and the true transconductance (G m ) of the transistor is maintained less than one and the product of the true transconductance and the series resistance R s of the transistor is maintained greater than or equal to one in the main operative state of the transistor. The series resistance R s is the sum of a resistance of the source, a resistance from the source to the current channel, and the channel resistance from the entrance of the current channel to the position of maximum value (extrema point) of the potential barrier in the current channel. This static induction transistor has the advantage that the current-voltage characteristic curve is nearly linear over a very wide range of drain current including the low drain current region.

Junction field effect transistor for use in integrated circuits

Abstract: A junction field effect transistor is incorporated into a conventional monolithic bipolar integrated circuit using compatible processing steps. The transistor source and drain regions are produced during IC base diffusion and the gate contact during IC emitter diffusion. A channel is ion implanted in the region between source and drain. A second, shallower, opposite conductivity ion implant is applied over the channel so as to overlap and cover. Thus, a subsurface channel is created. A third ion implant of slightly deeper character and to a much heavier dosage is created in the region between and separated from the source and drain using an impurity of the same conductivity type as the second ion implant. This third ion implant is designed to span the channel without contacting either the source or drain, thus creating a top gate ohmically connected to the bottom gate.

VMOS Floating gate memory with breakdown voltage lowering region

Abstract: A semiconductor electrically programmable read only memory device (EPROM) utilizes an array of memory cells each in the form of a single V-type MOSFET which achieves the normal AND function (Data-Word Address) using a capacitance coupled version of threshold logic. Each MOSFET is formed by a V-shaped recess at the intersection of each bit line and word line that extends across the diffused bit line, (which serves as the transistor drain) and into the substrate (which serves as the source and ground plane of the device). A similarly V-shaped floating gate is isolated below and above the crossing bit and word lines by thin oxide layers. A ring of P-type conductive material around the upper end of each V-shaped recess and adjacent its surrounding N-type drain region serves to lower the required programming voltage without increasing the device threshold voltage.

Stepped oxide, high voltage MOS transistor with near intrinsic channel regions of different doping levels

Abstract: A Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) is described wherein a body of semiconductor material is provided with source, drain and channel regions and a gate structure located over the interstitial channel portion of the semiconductor body, between the source and drain regions. A stepped or dual thickness oxide layer, having one portion of minimum thickness formed over only a portion of the channel region and another portion of maximum thickness formed over the remaining portion of the channel region. This stepped oxide layer, together with the gate electrode, forms the gate structure. That portion of the channel region covered by the portion of minimum thickness oxide is separated from the drain region, and the portion of maximum thickness oxide is also located over both a portion of the drain region and that portion of the channel region adjacent the drain region.

Insulated gate type field effect semiconductor device and a circuit employing the device

Abstract: An insulated gate type field effect transistor for high power which has a low conductivity region surrounding a drain region and an offset gate region having a further lower conductivity adjoined thereto, wherein the length and impurity concentration are designed according to the electric characteristics of the transistor. A combination of P channel and N channel type transistors having substantially the same electric characteristics and an audio amplifying circuit using the combination are also disclosed.

Characterization of the MOSFET Operating in Weak Inversion

Abstract: Publisher Summary This chapter describes the physical properties of the interface between silicon and silicon dioxide in metal-isolator semiconductor transistors and of their influence on the channel current of a MOS transistor, particularly in weak inversion. The channel current consequently, is several orders of magnitude smaller than in the normal operating region and is easily influenced by the nonuniformities in the vicinity of the interface. In order to be able to derive the properties of the interface from the measured weak-inversion current, one has to calculate the theoretical current flowing through the corresponding ideal transistor. To that end, it is necessary to characterize the experimental transistor as accurately as possible. This is done by means of three-terminal capacitance measurements that yield the channel length and the capacitances between different parts of the MOS transistor. The chapter discusses the accurate model for the drain current in a MOSFET, determination of the surface state density from the drain current versus drain voltage measurements in weak inversion, and influence of potential fluctuations on the mobility in weak inversion.

Short channel MOS devices and the method of manufacturing same

Abstract: A short channel MOS transistor and the method for fabricating same is described wherein the dopant concentrations of the source and drain regions are maintained at different levels of conductivity modifiers. The method described teaches first doping the source region while maintaining the drain region masked and then doping both the source and drain regions.

Entirely diffused vertical channel jfet: theory and experiment

Abstract: The experimental electrical properties of a vertical channel JFET fabricated by a double diffusion technique are presented. A table showing its principal characteristics for different values of the diffusion depths is included. The analysis of the “triode-like” operation revealed by the output characteristics is based on a two-dimensional numerical simulation of the device. At high drain currents ID is proportional to VDSα (α<1). This behaviour can be attributed mainly to the effect of channel length modulation by the drain voltage. At low drain currents, the potential barrier between the source and the drain determines the current magnitude. This is an exponential function of the barrier height which increases almost linearly when VGS increases and decreases non-linearly when VDS increases.

MIS Field effect transistor for high source-drain voltages

Abstract: A MIS field effect transistor of the depletion type having source, drain and channel regions of a first conductivity type formed in a substrate of the second conductivity type. A gate electrode is formed on an insulating layer above the channel. The spacing between the channel and the gate electrode increases between the source and the drain. This increase in spacing may be a continuous increase in the direction of the drain or may be a series of steps. A circuit arrangement is described where a plurality of these depletion MIS field effect transistors of the above type are serially connected with the source of the first of these depletion type transistors, connected to the drain of a preceding enhancement type MIS field effect transistor.

Complementary MOS inverter structure

Abstract: A complementary MOS inverter includes transistors each of which has a dual gate structure with the threshold voltage of the channel nearest the drain of each transistor arranged to be lower than that of the channel nearest the source of each transistor. This arrangement provides the cascode characteristics of dual gate structure, i.e., high breakdown voltage, high voltage gain, low drain output conductance, and relatively fast frequency response, but allows all four gate electrodes of the transistors to be connected in common, thus enabling relatively simple layout.

Referential voltage generator and its application

Abstract: PURPOSE: To obtain a referential voltage having reduced temperature fluctuation, by taking out the voltage approximately same with the energy gap of the semiconductor as the referential voltage CONSTITUTION: When taking out the difference between the threshold voltages Vth1, Vth2 of MOS transistor T 1 T 2 having commonly connected drain and gate, the current IO from the constant current source is such as I 0 = 1/2B(V 1 -Vth1) = 1/2B(V 2 -Vth2) 2 where VI 1 , V 2 are the drain voltages of each MOS transistor, B is the mutual conductance, thereby the difference of the threshold voltages Vth1-Vth2 can be taken out by taking out the difference of drain voltages When employing N gate and P gate MOS for MOS transistor T 1 , T 2 in such circuit, the difference of Fermi level of n-type and p-type semiconductors approximately same with the difference of the threshold voltages can be taken out COPYRIGHT: (C)1979,JPO&Japio

High voltage CMOS circuit

Abstract: A CMOS circuit having high voltage capability is provided. At least one P channel transistor is coupled between a first voltage node and an output of the circuit. At least two N channel transistors are coupled in series between the output of the circuit and a second voltage node. The at least two N channel transistors each have a separate tub which is connected to the source of each respective N channel transistor. This arrangement of the N channel transistors provides at least one tub which is isolated from the voltage nodes when the output of the circuit is at a potential substantially equal to a voltage present at the first voltage node.

Multidrain metal-oxide-semiconductor field-effect

Abstract: A metal-oxide-semiconductor field-effect device for constituting a single logic inverter stage. It includes a multidrain transistor operating in enhancement mode and a load transistor, both of monochannel metal-oxide-semiconductor structure. The inverter transistor comprises a single gate region and several drain regions. The single gate region and the single channel region of the inverter multidrain transistor are superimposed on both implantation planes separated by a thin insulating layer, entirely surround each drain region of the inverter multidrain transistor and are entirely surrounded by the single source region of the inverter multidrain transistor.

Avoidance of hot electron operation of voltage stressed bootstrap drivers

Abstract: An improved field effect transistor circuit adapted to operate at high switching speeds and to avoid hot electron operation of voltage stressed FET bootstrap drivers. The circuit comprises a voltage control means adapted to maintain a simultaneous gate and drain to source voltage of FET devices within a characteristic hot electron operational voltage range. The voltage control means is adapted to reduce FET drain to source voltage by connecting a plurality of FET devices in series to reduce the drain to source voltage drop across each device. The drain to source voltage is further defined by connecting the common nodes of successive series connected devices to a specified voltage source that is less than a characteristic hot electron drain to source voltage. The voltage control means also includes a gate voltage clamping FET that is adapted to hold down the gate of a device when the drain to source voltage of the device rises above a particular hot electron voltage. The voltage control means further comprises a plurality of timing pulses that define particular combinations of gate and drain to source device voltages that are less than characteristic combined hot electron voltages. The voltage control means further includes devices with width to length ratios adapted to provide close voltage tracking between input drain voltages and output source voltages to maintain a minimum drain to source voltage drop. The operation of the hot electron voltage control means is particularly described with respect to embodiments using voltage stressed bootstrap driver FETs to generate on chip clock phases.

Constant voltage threshold device

Abstract: Disclosed is a constant voltage threshold device for providing a substantially constant voltage across a pair of terminals. The threshold device includes a field effect device having source and drain regions formed into an isolated semiconductor region which, in turn, is formed into a substrate. The distance between the drain region of the field effect device and the substrate is directly related to the threshold voltage of the threshold device. The threshold voltage is also determined by the relative doping levels of the various semiconductor regions and the value of various fixed biasing potentials applied to the various electrodes of the threshold device.

Piezo-electric oscillators with automatic gain control

Abstract: A field effect transistor is used in the bias circuit of an oscillation transistor of a piezo-electric oscillator, and a diode is connected between the gate electrode of the field effect transistor and the base electrode of the oscillation transistor with a polarity to pass current from the gate electrode to the base electrode. The source electrode of the field effect transistor is connected to the base electrode of the oscillation transistor and the drain electrode of the field effect transistor is connected to a power source.

Dual field effect transistor structure for compensating effects of threshold voltage

Abstract: A dual field effect transistor structure for reducing the effects of threshold voltage of one of the field effect transistors as reflected to a signal source device which is coupled thereto is disclosed. More specifically, a p-channel enhancement mode field effect transistor having a surface conduction channel and an n-channel depletion mode field effect transistor having a buried conduction channel are formed in a semiconductor structure such that both transistors have a common gate. A voltage potential is applied to the common gate to affect the first and second depletion regions in the semiconductor structure respectively associated with the enhancement mode and depletion mode transistors to render a quiescent threshold voltage of the enhancement mode transistor which is reflected to the measuring device. The semiconductor structure is initially electrically biased in conjunction with the voltage potential applied to the common gate to cause the first and second depletion regions to pinch off the buried conduction channel substantially eliminating current flow therethrough. The signal source device may be coupled to the source of the enhancement mode transistor to conduct a first current through the surface conduction channel. This first current screens the electric field lines which are produced by the voltage potential applied to the gate to cause a modulation of the first depletion region. This modulation effects a second current in the buried conduction channel of the depletion mode transistor. A resistor network which is coupled between the drain of the depletion mode transistor and the common gate is utilized to detect the second current and accordingly control the value of the gate voltage potential in a sense which causes the first and second depletion regions to substantially pinch off the buried conduction channel or reduce the second current being conducted therethrough. In this manner, the gate voltage potential is adjusted to substantially maintain the quiscent threshold voltage.

Anomalous drain current in n-MOSFET's and its suppression by deep ion implantation

Abstract: Effects of the deep ion implantation on the characteristics of the short channel n-MOSFET have been investigated by two-dimensional numerical analysis and verified experimentally. By the analysis, it has been found that the anomalous drain current which flows in the relatively deep region between the source and the drain has been effectively suppressed by the deep ion implantation of acceptor impurities into the channel region. Structure of short channel n-MOSFET with deep ion-implanted layer has been optimized by computer simulation to suppress the anomalous drain current. Experimentally, the low and steep subthreshold current characteristics have been obtained by deep ion implantation for short channel n-MOSFETs with L EFF = 1.2µm. Furthermore, the back gate bias dependence of the threshold voltage of the implanted short channel device can be made almost likely to that of the unimplanted long channel device.

Threshold voltage model of ESFI-SOS-MOS transistors

Abstract: A threshold voltage model for ESFI-SOS transistors is presented accounting for the thin-film structure and the existence of the silicon-sapphire interface. The model uses simplifying assumptions in order to obtain analytical expressions. In most practical cases the charge at the silicon-sapphire interface is sufficiently high to accomplish a saturation effect of the value of the threshold voltage. Consequently, the exact value of the interface charge must not be known in order to calculate the value of the threshold voltage; the sign of the interface charge, however, has a drastic effect. Experimental results are in good agreement with calculated values. The threshold voltage can be reproducibly controlled to the extent that the ESFI-SOS technique can be utilized for low-voltage applications as well.

Stabiliser for supply voltage - has series transistor controlled by two other transistors in accordance with input voltage

Abstract: The stabiliser has a sereis transistor and an input voltage divider with a resistor and a Zener diode. Its tapping is connected with the series transistor base. A switching transistor (18) is conducting when an input voltage is above a lower limit, and blocked when it is below this limit. When blocked, it makes conducting a second switching transistor (19), which then blocks the series transistor (14), so that the output voltage is at least approx. zero.

Process of making field effect transistor having improved threshold stability by ion-implantation

Abstract: An improved field effect transistor device in a monocrystalline semiconductor body provided with source and drain regions and a gate electrode disposed over the channel between the source and drain regions wherein at least the drain region is formed of a first region where the impurity concentration increases with depth with the peak concentration being spaced inwardly from the major surface, and a second region located within the first region having a peak impurity concentration at the major surface. The drain region structure in operation promotes the current flow between the source and drain to flow deeper in the channel region and spaced from the gate dielectric layer. In the method for forming the field effect transistor, an impurity is introduced into the semiconductor body underlying at least the ultimate drain region, an epitaxial semiconductor layer deposited, and a second impurity region formed over the first region to form the drain contact. In an alternate embodiment of the method for forming a field effect transistor, a first ion implantation is formed in the drain region, such that the peak impurity concentration is located well within the body spaced from the surface thereof, and a second ion implantation, or diffusion, performed forming the source and also the ohmic contact for the drain which is located over the first region and within the first implanted region.

A DSA-type Non-Volatile Memory Transistor with Self-Aligned Gates

Abstract: A new structure n-channel stacked-gate type non-volatile memory transistor for both EP ROM and EEP ROM devices is presented. In this memory transistor, the P+ -region of high impurity concentration is diffusion-self-aligned (DSA) with the drain and the floating gate is.defined, also self-aligned with the control gate. Experimental results of various characteristics are presented and discussed with some analytical consideration. This memory transistor can be characterized by the ease of channel electron injection, fast ultraviolet light erasure and the electrical erasure with single positive applied voltage using surface avalanche hole injection.

High power static induction transistor

Abstract: SIT is usually constructed as vertical and multi-channel structure, resulting in a realization of large area device, i.e., high current operation, where temperature dependence of SIT enhances its large area characteristics without accompanying thermal runaway, because the temperature coefficient of drain current is negative in high current region. An introduction of high resistivity region between gate and drain increases its breakdown voltage and decreases gate to drain capacitance, resulting in an improvement of handling power and frequency characteristic. High power SIT having a cell size of 12.8 × 12.8 mm2has been fabricated to obtain killowatts operation in radio frequencies, which is characterized by burried gate and extremely long stripe channel structure. Gate to drain breakdown voltage is higher than at least 800 V and maximum drain current is up to 60 A. Ultrasonic wave generator using two high power SITs in push-pull configuration exhibits 3 KW output operation at an efficiency higher than 85 % at a frequency of 28 KHz, where the driving power of SIT is Iess than 5W. 100 KHz switching regulator has been realized and exhibits 300 W output at an efficiency of 70 %. This efficiency is limited by properties of ferrite core. SIT has been confirmed experimentally very promising to high power transisters in high frequencies.