Showing papers on "Drain-induced barrier lowering published in 1979"

VLSI limitations from drain-induced barrier lowering

Abstract: Drain-induced barrier lowering (DIBL) determines the ultimate proximity of surface diffusions and qualifies as one of the fundamental electrical limitations for VLSI. The important design parameters relating to DIBL are investigated using a numerical two-dimensional model, and a simple conceptual model is introduced as an aid for understanding the results. Under normal operating conditions of an IGFET, DIBL produces surface (rather than bulk) injection at the source. Comparison of a base case with a scaled design reveals that simple linear scaling by itself is insufficient for holding DIBL to a tolerable amount.

VLSI limitations from drain-induced barrier lowering

Abstract: Drain-induced barrier lowering (DIBL) determines the ultimate proximity of surface diffusions and qualifies as one of the fundamental electrical limitations for VLSI. The important design parameters relating to DIBL are investigated using a numerical two-dimensional model, and a simple conceptual model is introduced as an aid for understanding the results. Under normal operating conditions of an IGFET, DIBL produces surface (rather than bulk) injection at the source. Comparison of a base case with a scaled design reveals that simple linear scaling by itself is insufficient for holding DIBL to a tolerable amount.

Characteristics and limitation of scaled-down MOSFET's due to two-dimensional field effect

Abstract: Practical limitations of minimum-size MOS-LSI devices are investigated through measurement of experimental devices. It is assumed that scaled-down MOSFET's are limited by three physical phenomena. These are 1) poor threshold control which is caused by drain electric field, 2) reduced drain breakdown voltage due to lateral bipolar effects, and 3) hot-electron injection into the gate oxide film which yields performance variations during device operation. Experimental models of these phenomena are proposed and the smallest possible MOSFET structure, for a given supply voltage, is considered. It is concluded that the smallest feasible device has a channel length of 0.52 µm and a gate oxide thickness of 9.4 nm when the supply voltage is 1.5 V. Reliable threshold control is most difficult to realize in an MOS-LSI with the smallest devices.

Method of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations

Abstract: A MOSFET device structure is disclosed where the channel region has formed therein a buried layer of dopant of the same conductivity type as the source and drain, so that the depletion layers for the PN junctions at the upper and lower boundaries thereof intersect in the middle of the implanted region, effectively forming a buried insulator layer between the source and drain. The presence of this layer increases the distance between the mirrored electrostatic charges in the gate and in the bulk of the substrate beneath the MOSFET, thereby reducing the sensitivity of the threshold voltage of the device to variations in the source to substrate voltage.

Analytical models of threshold voltage and breakdown voltage of short-channel MOSFETs derived from two-dimensional analysis

Abstract: An approximate analytical solution for the surface potential is used to derive the threshold voltage. It is shown that the surface potential depends exponentially on the distance from the drain, and this causes the threshold voltage to decrease exponentially with decreasing channel length. The analytical dependence of threshold voltage on device dimensions, doping, and operating conditions is verified by accurate two-dimensional calculations, and the accuracy of the model is attained by slight modification. The breakdown voltage of a short-channel n-MOSFET is lowered by a positive feedback effect of excess substrate current. From two-dimensional analysis of this mechanism, a simple expression of the breakdown voltage is derived. Using this model, the scaling down of MOSFETs is discussed. The simple models of threshold and breakdown voltage of short-channel MOSFETs are helpful both for circuit-oriented analysis and process diagnosis where statistical use of the model is often needed.

The effects of two-dimensional charge sharing on the above-threshold characteristics of short-channel IGFETS

Abstract: In a short-channel Insulated Gate Field Effect Transistor (IGFET), a significant fraction of the electric field lines associated with the depleted region under the gate are terminated on the source and drain junctions. In this situation the two-dimensional sharing of the depleted substrate charge between the source, drain and gate terminals, has a dramatic effect on the device behaviour. A model is presented to describe the above-threshold characteristics of short-channel IGFETS when they are affected by the proximity of the source and drain junctions. The analytical forms allow a continuous description of the drain current from subthreshold to above threshold conduction. The model takes into account the fact that the device may be turned on by the drain voltage rather than by the gate voltage; in addition, it describes naturally the enhanced drain conductance commonly encountered in short-channel devices. The description includes both the linear and saturation regions over the complete range of drain and substrate voltages and for gate voltages below the value where channel-drain junction interactions become important or velocity saturation sets in. The model therefore provides an analytical description for a short-channel IGFET in the voltage regime where high-field effects in the channel do not significantly effect the current flow. The results indicate that the dominant effects for this region of operation in a short-channel device may be represented by the use of a drain-voltage and geometry-dependent threshold voltage. In the saturation region, the effects of the threshold variations are reflected in the parameter VSAT, the saturation voltage. The principle features of the model are verified by a detailed comparison with short-channel devices.

Circuit for switching and transmitting alternating voltages

Abstract: A circuit for switching and transmitting alternating voltages comprise an MOS transistor, the pn-junctions which surround the source and drain regions being biased in a blocking direction in the driven condition of the transistor, correspondence between the potential difference between gate and alternating voltages and the required drive voltage of the transistor being achieved by a circuit which largely synchronizes gate voltage changes with the alternating voltage to be transmitted.

Computer analysis of punch-through in MOSFETs

Abstract: A two-dimensional numerical analysis is made for MOSFETs having short channel lengths. The short channel MOSFET is especially characterized by the existence of the punch-through current which cannot be explained by the one-dimensional MOSFET models. The two-dimensional analysis makes clear the following facts relating about the punch-through mechanism. The punch-through is a condition in which the depletion layers of the source and the drain connect mutually at the deep region in the substrate even in equilibrium. The punch-through current is injected through the saddle point of the intrinsic potential into the drain region by the electric field from the drain, at the low gate voltages.

CMOS Transistor pair with reverse biased substrate to prevent latch-up

Abstract: A complementary type MOS transistor device is disclosed including a p-channel type MOS transistor having source, drain and gate regions formed in the n-well region which is formed in the surface area of a p-type semiconductor layer and an n-channel MOS transistor having source, drain and gate regions formed in said semiconductor layer. The semiconductor layer is formed on an n-type semiconductor body and a reverse bias voltage is applied between the semiconductor layer and the semiconductor substrate.

Microwave-Rectification RFI Response in Field-Effect Transistors

Abstract: This paper discusses the rectification of microwave energy in low-medium frequency feld-effect transistors (FET's) and develops a small-signal model for RHI noise analysis in low-frequency linear circuitry. The modeling procedure centers on a Taylor series expansion of the gate voltage-drain current characteristic which shows a small increase in drain current due to a nicrowave voltage at the gate. The increase in drain current is proportional to the variation in transconductance with gate voltage, and the square of the microwave voltage. Analysis of the microwave power in the transistor shows that critical parameters in determnination of the sensitivity are the gate capacitance and the real part ofthe device input impedance, which ultimately is limited by the parasitic resistance between the active channel and contacts.

Open base bipolar transistor protective device

Abstract: A transistor, used in the switching of current in an inductive load, is protected by a similar transistor connected between collector and base The protective transistor has a lower breakdown voltage than the transistor being protected When the inductive load produces a voltage surge, the protective transistor breaks down first and turns the protected transistor on so that the surge is absorbed in an active transistor not in breakdown and therefore capable of dissipating the surge without damage Since the surge is arrested at high voltage the time required to complete the arrest is shortened

Threshold voltage theory for a short-channel MOSFET using a surface-potential distribution model

Abstract: A detailed expression of the threshold voltage for a short-channel MOSFET is derived from a model of surface-potential distribution under the gate using a relationship of surface-channel charge neutrality. The theory is compared with the measured threshold voltages. The theoretical curves for threshold voltage over a wide range of drain and backgate voltage are in good agreement with experimental results. It is shown for a MOSFET having a channel length less than 2 μm that the body-bias constant increases as the drain voltage increases. The theory also predicts that the increase in backgate voltage leads to the reduction in short-channel effect for the shorter-channel case.

Insulated gate type semiconductor device

Abstract: In an insulated-gate type static induction transistor having a source region for supplying charge carriers, a channel region through which said carriers travel, an insulated electrode type gate structure to which is inputted a gate voltage for controlling the travel of those carriers. A sharp build-up and non-saturating current vs. voltage characteristic, a high transconductance, and a small inter-electrode capacitance for high-speed operation are achieved by either reducing the channel length, or by reducing the depth of the source region smaller than that of the drain region, or by forming adjacent to the source region a blocking region of high impurity concentration relative to the channel region, or by arranging the effective channel close to the insulated gate.

Floating gate vertical FET

Abstract: A planar field effect transistor (FET) includes a plurality of spaced-apart, floating Schottky barrier, epitaxial metal gate electrodes which are embedded within a semiconductor body. A drain electrode and a gate control electrode are formed on one major surface of the body whereas a source electrode, typically grounded, is formed on an opposite major surface of the body. The FET channel extends vertically between the source and drain, and current flow therein is controlled by application of suitable gate voltage. Two modes of operation are possible: (1) the depletion regions of the control gates and the floating gates pinch off the channel so that with zero control gate voltage no current flows from source to drain; then, forward biasing the control gate opens the channel; and (2) the depletion regions of the control gates and the floating gates do not pinch off the channel, but reverse biasing the control gate produces pinch off. Specifically described is a GaAs FET in which the floating gate electrodes are Al epitaxial layers grown by molecular beam epitaxy.

Stable field effect transistor voltage reference

Abstract: A temperature stable voltage reference utilizes an enhancement field effect transistor and a depletion field effect transistor each connected in series with a current source. A differential amplifier has its input terminals separately connected between each of the field effect transistors and their respective current supplies. An input terminal of the field effect transistor is utilized as the reference voltage and is also connected to the gate of one of the field effect transistors, the gate of the other field effect transistor being connected to a reference potential.

Self-pulsed microwave power amplifier

Abstract: A pulsed microwave power amplifier for radar transmitters having a class B operated first stage field effect amplifying transistor, which is gate biased to pinch-off in the absence of an input pulse is disclosed. The drain current pulse induced in response to the input RF signal appears as a voltage, which is stepped up through a Ruthroff transformer to turn on a bipolar transistor which switches a gate of a second stage field effect transistor from pinch-off voltage to a voltage corresponding to the drain current substantially equalling 1/2 I DSS to operate class A for the second stage of amplification. A third stage of amplification may be utilized, wherein its field effect transistor, which is also biased to pinch-off is operated in response to the amplified signal.

Field effect transistor with insulated gate electrode

Abstract: A field effect transistor of the V-MOST type in which the channel region comprises a more highly doped part which adjoins the source zone and a lower doped part which surrounds said region, said channel region adjoining the surface and surrounded by an insulation diffusion. The lower-doped part is depleted from the pn junction with the low-doped drain region up to the surface at a voltage which is lower than the breakdown voltage.

Drain noise in MOSFETs at zero drain bias as a function of temperature

Abstract: The noise in MOSFETs at zero drain bias is found to be somewhat larger than the thermal noise of the output conductance gdo at that bias The effect is most pronounced at 300°K and has practically disappeared at 77°K The effect is attributed to the large transverse field at the surface of the channel; the temperature dependence of the effect is as yet unexplained

A high voltage offset-gate SOS/MOS transistor

Abstract: A high voltage SOS/MOS transistor with a new offset-gate structure is proposed and verified experimentally to realize completely dielectrically isolated high voltage CMOS ICs. Since its offset-gate region, consisting of a pinched resistor and an underlying substrate layer, is designed to deplete vertically throughout the silicon epi-layer at above the drain voltage equal to the offset-gate pinched-off voltage, the proposed transistor shows a high drain breakdown voltage characteristic that is not limited by the substrate doping level, but depends only on the offset-gate length. The offset-gate PMOS and NMOS transistors were successfully fabricated on the same intrinsic SOS wafer by ion implantation substrate doping and resulted in drain breakdown voltages of up to 950V and 1100V, respectively, at 100 µm offset-gate length.

Solidstate alternating current switch

Abstract: PURPOSE:To reduce the series equivalent input capacitance at switched end, by restricting the drain capacitance of the field effect transistor with the capacitance of the diode constituting the diode bridge. CONSTITUTION:Pulsive drive voltage applied via the capacitors 6, 7 is rectified and smoothed with the diode 10 and the resistor 12 to make conductive the field effect transistor 1. The field effect transistor 1 is mounted in the bridge consisting of the diodes 13-16 to turn on and off the bidirectional signal. When the transistor 1 is OFF, the cross points 17, 18 of the transistor 1 and the diodes are DC-biased to a given point to the switched AC input signal of a constant amplitude, and the drain capacitance of the transistor 1 is not operated to the signal more than a given point. As a result, the series equivalent resistor of the switch is only the capacitance of the diodes. Accordingly, the switching performance to high frequency signal is increased.

V-MOS Field effect transistor for a dynamic memory cell having improved capacitance

Abstract: This disclosure relates to a V-MOS field effect transistor which is provided with enhanced source capacitance to provide a single transistor dynamic memory cell. The formation of the source area is achieved by masking the silicon substrate, opening an aperture in the mask and then etching the silicon substrate in such a manner as to undercut the mask so that the mask provides a shield to subsequent ion implanting of the source area. Both P and N type dopants can be separately implanted with different energy levels so as to form an enhanced PN junction capacitance for the device. Such a field effect transistor can be achieved without the formation of a graded dopant concentration in the channel between the source and drain areas of the transistor.

Integrated junction field effect transistor and method for making same

Abstract: 1. Integrated barrier layer field effect transistor which with respect to its design and production is arranged compatible with bipolar transistors on the same semiconductor wafer, where in a semiconductor zone (40A, 44) of a first conductivity type which usually is provided as the collector region of a lateral bipolar transistor a source region (54) and laterally thereto a drain region (56) of the opposite second conductivity type are arranged and where a channel region (80) of the second conductivity type connecting the source and drain regions (54, 56) is implanted in the semiconductor zone (40) of the first conductivity type which serves as the gate region of the barrier layer field effect transistor, characterized in that the semiconductor region (40) of the first conductivity type serves either as a base region of a vertical, or as a collector region of a lateral bipolar transistor, and in that the drain region (36, 56, 70; 56, 38) permeates this semiconductor region (40), dividing it in the manner of an insulation into a first (40) zone containing the barrier layer field effect transistor, and into a second (44) zone containing the bipolar transistor.

Threshold circuit using complementary field effect transistors

Abstract: A threshold arrangement includes two complementary transistors whose channels are situated in series between two supply terminals. In order to obtain a substantially square-wave relationship between the output voltage on the common drain electrodes and the input voltage on the interconnected gate electrodes, a direct voltage source is included between the two gate electrodes, which source has a voltage which is preferable substantially equal to the supply voltage minus the sum of the threshold voltages of the two complementary transistors.

Electrical characteristics of a DSA MOS transistor with a fine structure

Abstract: Fabrication technologies and electrical characteristics of a diffusion self-aligned MOS transistor (DSA MOST) or a double-diffused MOS transistor (DMOST) are discussed in comparison with a conventional short-channel MOS transistor as a fundamental device for a VLSI. The symmetrical DSA MOS LSI with enhancement depletion configurations requires six photolithographic steps and the number of the steps is the same as that of an NMOS LSI with small physical dimensions. The only difference is the step orders of the enhancement channel doping in these devices. The lowering effects of the threshold voltage and the source drain breakdown voltage are smaller in the DSA MOST than in the conventional MOS transistor. The drain current I D of the symmetrical DSA MOS transistor is, respectively, 1.13 (in the nonsaturation region) and 1.33 (in the saturation region) times larger than that of the conventional short-channel NMOS transistor at the effective gate voltage of 3.0 V. The improvement of the short-channel effect, the current voltage characteristics, and the power-delay product are obtained by the scaling of the DSA MOS transistor.

Power static induction transistor technology

Abstract: Static induction transistor (SIT) is characterized by short channel structure and the relatively low impurity concentration in the channel, so that the potential profile near the source region is effectively controlled by the drain voltage as well as the gate voltage. Majority carriers in the source region are directly injected into the channel and their amount continuously increases with increasing the drain voltage, thus establishing the non-saturating current-voltage characteristic in the SIT. The SIT, which is usually constructed as a vertical multichannel structure, exhibits features such as high input impedance, small gate capacitance, small gate resistance and negative temperature coefficient of drain current, thus offering a thermally stable operation of large area devices without ballasting resistor. An introduction of high resistivity region between gate and drain increases its breakdown voltage and decreases gate to drain capacitance, leading to an improvement of handling power and frequency characteristic.

Transistor amplifying circuit for preventing the operation of an amplifying transistor in the quasi-saturation region

Abstract: The cut-off frequency of a transistor drops remarkably when the collector-emitter voltage of the transistor is driven into the quasi-saturation region of about 1 V. To prevent this problem, the collector-emitter voltage of the transistor is detected and compared with a predetermined reference voltage by comparison-limiting means. The comparison-limiting means limits the base current of the transistor and thus restricts the drop in the collector-emitter voltage. Limiting the voltage drop in this manner prevents the transistor from being driven into the quasi-saturation region. The reference voltage is set to the p-n junction voltage in the forward direction. Hence, the drop in the collector-emitter voltage is limited to a value near this reference voltage.

Method for making a closed gate MOS transistor with self-aligned contacts

Abstract: A method of manufacturing a closed gate MOS transistor having a self-aligned drain contact is presented which insures that the drain contact will have the minimum required geometry. The method employs a self-aligned procedure which insures that the drain contact will have the minimum dimensions to insure a high speed device.

Output circuit for bucket-brigade devices

Abstract: To reduce the D.C drift of bucket-brigade devices having common output circuits (emitter follower), an output circuit is provided having an additional transistor and an additional capacitor. The terminal on the gate side of the capacitor associated with the last delaying transistor is not connected to the gate terminal but to the source terminal of the output transistor, the gate terminal of the terminating transistor is applied via the additional capacitor to that particular clock signal to which the penultimate delaying transistor is applied, and the drain terminal of the terminating transistor, via an enhancement-type transistor of the same conductivity, connected as a diode by directly connecting both the drain and the gate terminals, is connected to the gate terminal thereof.

Field effect transistor multivibrator

Abstract: A monostable, constructed of field effect transistors multivibrator delivers unaffected by transistor threshold changes pulses with a defined pulse width and steep pulse edges. It consists essentially of two cross-coupled field effect transistor stages together. Here, the first (T3) of the cross-coupled transistors having a gate directly connected to the drain of the second transistor (T7) is connected, which forms the output (0) of the multivibrator simultaneously. The cross-coupling path between the drain of the first transistor (T3) and the gate of the second transistor (T7) comprising the series connection of a capacitor (C1) and the source-drain path of a further field effect transistor (T6), in contrast to the other transistors the depletion type belongs and whose gate is connected to a reference potential. At this reference potential, the source of the first and second transistors (T3, T7) is applied. Finally, the connection point between the capacitance (C1) and the transistor (T6) is connected to the reference potential via a resistor element forming a transistor (T8). The lying in the path of a cross-coupling transistors (T6, T8) form a level shift stage, which causes the output pulses of the multivibrator with short rise and fall times to supply a trigger pulse. The pulse width of the output pulses is determined by the size of that are available in this cross-coupling path capacitance (C1) determined. two through a suitable link as described and constructed in each case at the output of an inverter stage Expanded multivibrators an astable multivibrator is formed.

V-groove semiconductor device with buried channel stop

Abstract: An insulated gate field effect transistor has channel stop regions which are separated from the heavily doped drain region so that the sidewall or drain/source to channel stop capacitance is reduced. This is accomplished by a buried outdiffused channel region which also functions as the channel stop in a VMOS transistor.