Showing papers on "Drain-induced barrier lowering published in 1982"

Short-channel MOST threshold voltage model

Abstract: A new short-channel threshold voltage model based on an analytic solution of the two-dimensional Poisson equation in the depletion region under the gate of an MOS transistor (MOSTs) is presented. A simple closed-form expression for the variation of threshold voltage as a function of drain voltage, substrate bias, channel length, oxide thickness, and channel doping is derived. An exponential dependence on channel length and a linear dependence on drain and substrate biases is prediced for the reduction in the short-channel threshold voltage. These results are in qualitative and quantitative agreement with simulated and experimental results reported in literature. The predictions for the threshold voltage and subthreshold drain current are in close agreement with measured characteristics of MOS transistors down to submicron dimensions. The closed-form expressions for the threshold voltage and subthreshold drain current are well suited for circuit simulation and for determining performance limits of MOSTs.

Titanium disilicide self-aligned source/drain + gate technology

Abstract: Silicides have been used to lower the resistance of gate level interconnects. Recently silicidation of source/drain diffusions have also been reported. In scaled CMOS devices, silicidation of source/drains is particularly important in reducing the sheet resistance of p+ source/drain diffusions. In this paper, a novel technique is described in which TiSi 2 is formed self-aligned to both source/drain and gate regions. Both n and p-channel MOSFETs Silicided with self-aligned TiSi 2 on source/drains gates have been fabricated using this technique. Sheet resistances below 5 Ω/□ on both gate and source/drain levels have been achieved and thus represent at least a 10X reduction in the resistance of p+diffusions. Diode leakage, subthreshold leakage, and threshold voltage measurements on silicided devices are comparable to that of control devices without silicidation, CMOS circuit applications of this TiSi 2 self-aligned source/drain and gate technology are discussed.

Junction field-effect transistor controlled by merged depletion regions

Abstract: A new method of semiconductor operation has been conceived, developed and applied to produce a revolutionary new semiconductor design. The method is that of merging depletion regions for purposes of operation, isolation and control of channel current in a junction field-effect transistor. Using this method depletion regions are made to merge with suitable biasing in an intervening layer interposed between the gate and channel of a junction field-effect device and the interaction of the depletion regions is used for isolation and coupling to alter the associated depletion region in the channel of the junction field-effect device. A number of embodiments are disclosed of the new junction field-effect transistor controlled by merged depletion regions. In each embodiment a channel of one conductivity type material is formed in a semiconductor body of opposite type material. A gate region of the same conductivity type material as the channel is placed near enough to the channel so that when the gate junction is reversed bias, the gate depletion region merges with the channel junction depletion region in the intervening layer. When the two depletion regions have merged, the gate controls the channel current in a manner similar to conventional devices. Because the output and input and control connections are of the same conductivity type material, no metal contacts or interconnections are required. The lack of need for metal interconnects makes the device better suited to integrated circuits than any other device. In addition, the depletion regions surrounding the gate and channel isolate the gate and channel from other semiconductor regions of the same conductivity type and thus isolation regions are not required for the junction field-effect transistor controlled by mergers depletion regions. Consequently, use of the invention can result in the densest form of logic available today. Such devices hold the promise of improved performance in almost every semiconductor device application and can be used in almost every application where MOS and junction field-effect devices are now used.

Gate-drain avalanche breakdown in GaAs power MESFET's

Abstract: The voltage breakdown behavior of a number of different MESFET structures has been investigated using a two-dimensional numerical model. The site of the avalanche is found to be under the drain edge of the gate in recessed devices under all bias conditions, but moves towards the drain contact in planar structures when the channel is not pinched off. The dependence of the breakdown voltage on a variety of geometrical and physical variables has been studied. In particular the surface is shown to play an important part in determining the breakdown voltage.

Stacked MOS transistor

Abstract: In a stacked metal-oxide-semiconductor (SMOS) transistor, the transistor source, drain and channel each have a lower part (18, 20, 22) formed in a silicon substrate (12) and an upper part (30, 32, 26) composed of recrystallized polysilicon. The device gate (24) is located between the upper and lower channel parts. By vertically integrating a MOS transistor, performance limitations imposed by the direct scaling approach to device miniaturization are avoided.

Subthreshold behavior of silicon MOSFETs at 4.2 K

Abstract: The subthreshold behavior of Si MOSFETs has been studied at 300, 77 and 4.2 K. At 300 and 77 K satisfactory agreement between theory and experiment was obtained, showing that the gate voltage swing needed to change the drain current by one decade reduces proportionally with temperature. At 4.2 K, however, the conventional subthreshold behavior was not observed down to drain current of 10−13 A. To achieve better circuit performance, there seems to be no advantage in lowering the temperature below 77 K.

Process and device design of a 1000-V MOS IC

Abstract: High-voltage MOS devices and logic N-MOS circuits have been integrated on the same chip by using a silicon-gate isoplanar process that is compatible with present N-MOS LSI technology. The electrical characteristics of high-voltage MOS devices are modeled and characterized in terms of channel length, drift-layer length, drift-layer ion dose, and extended source field-plate effect. The theoretical calculations of on-resistanee, saturation drain current, and pinchoff voltage agree well with the experimental results. Based on the experimental and theoretical results, the device structure and the process parameters are optimized to obtain maximum drain saturation current with a low on-resistance and a drain breakdown of 1000 V. The optimized high-voltage MOS device can perform with a saturation drain current as high as 84 mA with an on-resistance as low as 300 Ω within an area of 520 µm × 1320 µm while maintaining a drain breakdown of 1000 V.

Process for forming self-aligned complementary source/drain regions for MOS transistors

Abstract: Improved CMOS processing steps for forming p-type and n-type source and drain regions. A photoresist mask is used to expose one transistor type to allow the formation of source and drain regions of a first conductivity type. Then an oxidation step is used to grow an oxide over the substrate; this oxide grows more quickly over the doped source and drain regions. Ion implantation is used to implant ions of the second conductivity type through the thin oxide while the thicker oxide blocks these ions. Thus, the complementary source and drain regions are formed with a single masking step and without counter doping.

Ionizing Radiation Effects on Power MOSFETS during High Speed Switching

Abstract: Data on the effects of gamma radiation on the electrical characteristics of power VDMOS transistors are presented. The devices were exposed to radiation while the gate voltage was switching at 100 kHz or while held at a dc voltage. Several drain voltage configurations were also explored. The threshold voltage shifts observed begin to saturate at relatively low doses (~0.1 Mrad(Si)) for all but the worst case bias (VG = +10 V). The threshold voltage shifts do not show significant dependence on drain voltage. The devices studied appear to be approximately an order of magnitude more efficient in trapping radiation generated holes than would be expected in a state-of-the-art radiation hardened planar MOSFET.

MOS transistor circuits having matched channel width and length dimensions

Abstract: The voltage gain of an MOS transistor inverter stage is made independent of the device threshold voltages and of channel lengths by making the length and width of the channel region of the upper load transistor equal to the length and width of the channel region of the lower driver transistor.

Method of making a self-aligned Schottky metal semi-conductor field effect transistor with buried source and drain

Abstract: A semi-conductor structure and particulrly a high speed VLSI Self-Aligned Schottky Metal Semi-Conductor Field Effect Transistor with buried source and drain, fabricated by the ion implantation of source and drain areas at a predetermined range of depths followed by very localized laser annealing to electrically reactivate the amorphous buried source and drain areas thereby providing effective vertical separation of the channel from the buried source and drain respectively Accordingly, spatial separations between the self-aligned gate-to-drain, and gate-to-source can be relatively very closely controlled by varying the doping intensity and duration of the implantation thereby reducing the series resistance and increasing the operating speed

Drain-current distortion in CdSe thin-film transistors

Abstract: CdSe thin-film transistors (TFT's) fabricated with the lift-off process were susceptible to reversible degradation during operation. In particular, when the drain voltage exceeded ∼ 10 V, the I - V characteristics distorted. Current at low drain voltages was depressed, but current at high drain voltages was not. While the TFT was in the distorted state, it was possible by means of pulsed drive on the gate to observe negative differential conductivity. This distortion phenomenon was studied, and its source speculated upon. Factors believed to play a role are formation of deep traps, trapping of hot electrons in the gate insulator, depletion of carriers near the drain electrode, and tunneling of carriers through the depleted region at high drain voltages. Recovery occurs when the trapped electrons in the insulator are released. It is believed that residues of the lift-off process play a role in formation of these traps.

A simple model for short-channel effects of a buried-channel MOSFET on the buried insulator

Abstract: A majority-carrier distribution model and a channel potential-profile model, in which the barrier-lowering effect is taken into account, are proposed for a buried-channel MOSFET (BC-MOSFET/ SOI). Simple expressions for threshold voltage and drain breakdown voltage were derived from the models for a short-channel BC-MOSFET/ SOI. The comparison between theory and experimental results shows reasonable agreement. The drain-bias coefficient γ of threshold voltage for BC-MOSFET's/ SOI is approximately proportional to TN D -1L eff -2, where T, N D , and L eff are the temperature, the doping concentration in the channel region, and the channel length, respectively. The coefficient γ depends slightly on the drain bias. BC-MOSFET's/SOI are able to be more miniaturized than surface-channel MOSFET's (SC-MOSFET's) at the small power source voltage, and SC-MOSFET's are able to be more miniaturized than BC-MOSFET's/SOI at the large drain bias. It is shown that the conventional, simple scaling scheme, which holds the constant electric field, is not applicable to BC-MOSFET's/SOI. The power source voltage has to be fixed when dimensions and doping concentrations are scaled down. On the other hand, only the channel region thickness has to be fixed when the power source voltage is scaled down.

A geometrical model of the threshold voltage of short and narrow channel MOSFETs

Abstract: A simple geometrical model allows the calculation of the threshold voltage of short and narrow channel MOSFETs as a function of gate length, gate width, source and drain depth, substrate voltage and source drain voltage. Input parameters of the program are the customary values such as oxide thickness and, furthermore, an effective impurity concentration in the field region. The flat band voltage and the effective impurity concentration in the channel region can be calculated by a modified SUPREM program.

Semiconductor device having a safety device

Abstract: Semiconductor device having a safety device (4) comprising an improved lateral bipolar transistor structure (5). The improvement is obtained by incorporating an auxiliary field effect transistor (6) which has the emitter (8) as source zone and the collector (9) as drain zone and in which the threshold voltage of the auxiliary field effect transistor is lower than the avalanche breakdown voltage of the collector- base junction of the lateral transistor. As a result of this the lateral transistor switches sooner, at a lower voltage, to the readily conductive on-state.

The Effect of Operating Conditions on the Radiation Resistance of VDMOS Power FETs

Abstract: The effect of gamma radiation on the threshold voltage, "On" resistance, and breakdown voltage of VDMOS Field Effect Transistors operating under various bias conditions is presented. The drain-source breakdown voltage and the "On" resistance of these devices have been found to be unaffected by irradiating the devices to a total dose of 4×104 rads. The electrical parameter affected by irradiation is the gate threshold voltage. The threshold voltage shift at a particular radiation level for devices biased with both gate and drain voltage has been determined to be dependent only on the magnitude of the gate voltage during irradiation. This shift has been found to be independent of the drain-source voltage (30-80 volt range) and operating frequency (10-50kHz range). Practically no annealing occurs at room temperature. However, these devices have been found to recover to within 10% of their initial threshold voltage after annealing at 200°C under gate bias of 18 volts for 22 hours.

Integrated high and low voltage CMOS technology

Abstract: Novel, complementary high- and low-voltage MOS transistors are described. The high-voltage CMOS transistors were designed and fabricated using the same shallow well as that of low-voltage CMOS transistors, thus enabling integration of the devices without the use of dielectric isolation. The high voltage p-channel transistor is built inside of the n-type well and the p-type offset channel is used to separate the drain area from the gate, which has the same oxide thickness and threshold voltage as a low-voltage p-channel transistor. The high-voltage n-channel devices are built in the high resistivity p-type substrate, using an n-type offset channel to separate the N+-drain and the gate. The high- and low-voltage CMOS transistors were fabricated using 55-75 ohmcm, p-type substrate with a minimum channel length of 8 microns for the high-voltage and 2 microns for the low-voltage transistors. Drain to source breakdown voltages above 250V and above 25V have been demonstrated for the high-voltage and low-voltage transistors respectively.

Parasitic effect-free, high voltage MOS ICs with shielded source structure

Abstract: A shielded source structure is proposed for complete elimination of both "parasitic bipolar effect" in high voltage NMOS transistors and "latch up effect" in low voltage CMOS logic circuits, that strictly limit the area of safety operation (ASO) and noise margin for high voltage MOS ICs. The proposed structure, characterized by a p+ground layer formed under an n+source layer, prevents forward-biasing of the source junction and, in consequence, parasitic bipolar transistor or SCR turn-on, even at the drain avalanche breakdown condition. To verify these advantages, a 4 bit, 80 µm long offset-gate high voltage NMOS transistor array and low voltage n-Well CMOS buffer circuits, both with shielded source structure, were experimentally fabricated on the same chip by the same process. Since high voltage NMOS transistors showed more than 600 V drain breakdown voltage with no secondary breakdown and CMOS logic part was confirmed to withstand "latch up", a truly parasitic effect-free, large noise immunity high voltage MOS IC was realized.

Mis type semiconductor element

Abstract: PURPOSE:To enable to restrain short channel effect without increasing source- drain resistance by using a source and a drain which make ohmic contact with the channel and Schottky contact with a substrate. CONSTITUTION:Since the aluminum source and drain 13 make Schottky contact with the N type Si substrate 10 and ohmic contact with the formed P type channel 15, the defect of small drain current which is found in conventional Schottky source-drain MOS type semiconductor elements is not recognized, and accordingly characteristics of a MOS type semiconductor element wherein a diffused layer is used for the source and drain are obtained. The source-drain resistance can be reduced by using aluminum for the source and drain, and the Schottky channel effect is difficult to generate.

Electronic current overload protection installation

Abstract: An electronic current overload protection device in which an applied voltage is divided into the voltage across the load and the current-proportional voltage drop at an MOS transistor of a circuit that includes the load and the MOS transistor whose resistance is exactly linearly proportional to the current; this voltage drop is applied by way of a delay circuit to a threshold switch that controls the gate input of the MOS transistor by way of a driver stage; the threshold of the threshold circuit is adjustable corresponding to the current to be protected against.

A metal insulator semiconductor transistor

Abstract: An MIS transistor, which is built on an insulating layer (11) has the insulating layer (11) arranged with a thin portion (12) under the channel region (16) of the MIS transistor and a thick portion (13) under the remainder of the device, and has a conducting layer (19) formed beneath the insulating layer (11). Typically the device is a short channel MIS transistor having a channel length of 2.0 µm or less. Such a transistor has the advantage that equipotential lines run generally parallel to the gate electrode (17) and have a reduced drain voltage feedback and an increased trans-conductance and punch-through voltage.

Variable impedance circuit employing an RIS field effect transistor

Abstract: A variable impedance circuit employing an RIS field effect transistor which greatly reduces distortion at low and high frequencies is obtained by providing means for applying voltages to the RIS field effect transistor at values determined by the following equations: ##EQU1## where V BG is the backgate voltage, V D is the voltage applied to the drain, V S is the voltage applied to the source, V BO is the DC component of the voltage applied to the substrate, K is a constant, α 1 is a constant, α 2 is a constant, V GS is the voltage applied to the gate at the end nearest the source, V GD is voltage applied to the gate at the end nearest the drain and V GO is a control voltage.

Switching device and circuit

Abstract: A switching device and circuit comprises a bi-polar transistor (3, 3') and at least two field effect transistors (1, 2, 24, 30) for controlling the bi-polar transistor. A first field effect transistor (1, 30) has its drain and source connected across the collector-base of the bi-polar transistor and a second field effect transistor (2, 24) has its drain and source connected across the base-emitter of the bi-polar transistor. Gates of the first and second field effect transistors are connected in common and applied with a voltage signal. The first field effect transistor (1, 30) is of an enhancement type and the second field effect transistor (2, 24) is of a depletion type.

Method of making self-aligned metal gate field effect transistors

Abstract: A metal gate field effect transistor has its source and drain located on one major surface of a gallium arsenide layer, while its gate electrode forms a Schottky barrier contact to an opposed major surface of the layer in a self-aligned relationship to the source and drain

A closed-form threshold voltage expression for a small-geometry MOSFET

Abstract: An analytical expression is developed to predict the threshold voltage of a small-geometry MOSFET. The expression includes the effects of field doping encroachment at the channel edges, and charge sharing with the source and drain regions.

Multiple-drain mos transistor logic gates

Abstract: of EP00195601. Logic gate constituted by an inverter multidrain transistor (102 ) having an integrated monochannel enhancement mode MOS structure and by a load element (20; 30) having a contact region connected to the gate region (ZG10 ) of the inverter transistor, said gate including a first implantation plane on the surface of a semiconductor substrate of a predetermined conductivity type (1) in which are implanted the single source region (ZS10 ) and each drain region (ZD11 -ZD13 ) of the inverter transistor which are of the opposite conductivity type and are separated by the single channel region (C10 ) of the inverter transistor (102 ), and a second implantation plane constituting at least the gate region (ZG10 ) of the inverter transistor (102 ) that is composed of polycrystalline silicon (5), that is superimposed over said channel region (C10 ) through an insulating layer (3) above the first implantation plane and that is entirely surrounded by the source region (ZS10 ), characterized in that at least a drain region (ZD11 ) is separated from a neighbouring drain region (ZD12 ) through an insulating zone (ZI11-12 ) stretching from the first implantation plane to at least beyond the second implantation plane.

Metal-semiconductor field-effect transistor with a partial p-type drain

Abstract: A metal-semiconductor field-effect transistor (MESFET) is provided with a p-type region adjacent the n-type region under the drain contact. Holes injected from this p-type region compensate the negative space charge region at the channel to substrate interface, thus minimizing considerable substrate effects.

Field effect transistor with improved withstand voltage characteristic

Abstract: A field effect transistor comprises a source region (42) annularly formed to encompass and spaced apart from a drain region (41), whereby a second channel region is formed between the drain region and the source region in the vicinity of the former, while a first channel region is formed in the remaining area thereof, an annular first gate (43) formed bridging above the first channel region and the source region, a second annular gate (45) formed bridging above the first gate and the drain region, and an isolating film (47) formed contiguous to the source region at the side opposite to the channel region. As a result any region is eliminated where the channel region in the vicinity of the drain side end of the first gate (43) is in contact with the isolating film (47). Accordingly, no withstand voltage is restricted thereby and the withstand voltage of the field effect transistor is considerably enhanced.

Characteristics of short-channel MOSFETs in the breakdown regime

Abstract: When a short-channel MOSFET is driven into the avalanche-induced breakdown region, the drain current increases rapidly and shows a snapback characteristic. Both the substrate current and the current collected by a nearby reverse-biased pn junction also increase with increasing drain current in this region of operation. All of these effects are associated with minority-carrier injection from the source junction into the substrate. A model for the drain I-V characteristics in the snapback region is proposed. Also presented is a related model incorporating conductivity modulation that predicts linear relationships between the substrate and the remote-junction collection currents and the drain current in this region of operation. Experimental results agree well with the models.

A Closed-Form Threshold Voltage Expression for a Small-Geometry MOSFET

Abstract: An analytical expression is developed to predict the threshold voltage of a small-geometry MOSFET. The expression includes the effects of field doping encroachment at the channel edges, and charge sharing with the source and drain regions.