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Showing papers on "Drain-induced barrier lowering published in 1983"


Journal ArticleDOI
TL;DR: In this article, the charge coupling between the front and back gates of thin-film silicon-on-insulator (SOI) MOSFETs is analyzed, and closed-form expressions for the threshold voltage under all possible steady-state conditions are derived.
Abstract: The charge coupling between the front and back gates of thin-film silicon-on-insulator (SOI: e.g,, recrystallized Si on SiO 2 ) MOSFET's is analyzed, and closed-form expressions for the threshold voltage under all possible steady-state conditions are derived. The expressions clearly show the dependence of the linear-region channel conductance on the back-gate bias and on the device parameters, including those of the back silicon-insulator interface. The analysis is supported by current-voltage measurements of laser-recrystallized SOI MOSFET's. The results suggest how the back-gate bias may be used to optimize the performance of the SOI MOSFET in particular applications.

662 citations


Journal ArticleDOI
TL;DR: In this paper, the feasibility of double diffused drain is investigated comparing it with a conventional As drain over a wide range of effective channel length from 0.5 to 5 µm.
Abstract: An As-P(n+-n-) double diffused drain is characterized as one of the most feasible device structures for VLSI's from the overall viewpoint of device design. This device makes good use of both As, suitable for microfabrication, and P, in realizing a graded junction. The feasibility of this double diffused drain is investigated comparing it with a conventional As drain over the wide range of effective channel length from 0.5 to 5 µm. We have also succeeded in directly measuring hot-hole gate current as low as on the order of 10-15A. This current seems to have an important influence on the hot-carrier effects. On the basis of the experiments and simulations using the two-dimensional process/device analysis programs SUPREM and CADDET, it is shown that this device structure provides remarkable improvements, not only in terms of channel hot-electron effects, but also avalanche hot-carrier effects, which are more responsible for hot-carrier related device degradation due to impact ionization at the drain. In addition, this structure has almost the same short channel effect characteristics, for example threshold-voltage lowering as a conventional MOSFET.

88 citations


Journal ArticleDOI
TL;DR: In this paper, the behavior of hot-electron gate and substrate currents in very short channel devices was studied and an empirical relationship between the effective electron temperature and the field was found to be T e = 9.05 × 10-3E.
Abstract: The behaviors of the hot-electron gate and substrate currents in very short channel devices were studied. For a test device with electrical channel length of 0.14 µm, the hot-electron substrate current can be detected at 0.9-V drain voltage which is lower than the silicon band gap. The gate current can be measured at 2.35-V drain voltage, which is lower than the oxide-silicon energy barrier for electrons. These measurements support the quasi-thermal-equilibrium approximation and suggest that the hot-electron-induced problems cannot be eliminated in future VLSI MOSFET's of arbitrarily short channels by reducing the drain bias below some constant critical energies. An empirical relationship between the effective electron temperature and the field is found to be T e = 9.05 × 10-3E.

74 citations


Journal ArticleDOI
TL;DR: In this paper, the effect of minority carrier injection into the substrate by a MOS transistor operating in saturation presents a reliability problem in dynamic memory circuits such as RAM's and CCD's.
Abstract: Minority carrier injection into the substrate by a MOS transistor operating in saturation presents a reliability problem in dynamic memory circuits such as RAM's and CCD's. The effect has been studied by measuring the substrate and drain currents of stressed transistors as a function of gate and drain voltages, firstly by the accumulation of minority carriers in a charge coupled device, and secondly by the direct detection of light from the drain region of a transistor. These results suggest that light emission associated with multiplication in the drain region is more important than the secondary impact ionization mechanism in the generation of minority carriers.

41 citations


Journal ArticleDOI
TL;DR: In this article, a new grooved-gate MOSFET with its drain separated from channel implanted regions (DSC structure) is proposed for the purpose of obtaining higher breakdown voltages: drain sustaining voltage and highest applicable voltage placed by hot-carrier effects.
Abstract: A new grooved-gate MOSFET with its drain separated from channel implanted regions (DSC structure) is proposed for the purpose of obtaining higher breakdown voltages: drain sustaining voltage and highest applicable voltage placed by hot-carrier effects. Nonimplanted regions between channel implanted and source/drain regions are a unique feature of this device structure. The self-aligned nonimplanted region in the channel is obtained by using silicon dioxide and resist overhangs. These overhangs are fabricated by grooving the silicon substrate. The DSC structure helps reduce the electric field at the drain. Characteristics of experimental devices are presented and compared with those of conventional MOSFET's, from the viewpoint of overall VLSI device design. This device structure is shown to provide remarkable improvements, achieving a 3- or 4-V increase in drain sustaining voltage, as well as a 1- or 2-V increase in the highest applicable voltage as limited by hot-electron injection. In addition, the proposed device can alleviate such short-channel effects as V th lowering, and in particular, diminish narrow-channel effects. The influence of nonimplanted length on breakdown voltage is also clarified using the CADDET, two-dimensional analysis program.

41 citations


Patent
22 Apr 1983
TL;DR: In this paper, a nonvolatile semiconductor memory device is provided having a MOS transistor and a floating gate type MOS transistors, where the length of an overlap between a floating-gate and a drain region of the floating-gated MOS-transistor is made smaller than that of overlap between the gate and the drain regions of the mOS transistor.
Abstract: A nonvolatile semiconductor memory device is provided having a MOS transistor and a floating gate type MOS transistor. The length of an overlap between a floating gate and a drain region of the floating gate type MOS transistor is made smaller than that of an overlap between the gate and the drain region of the MOS transistor.

40 citations


Proceedings ArticleDOI
01 Jan 1983
TL;DR: In this paper, the authors examined the performance degradation due to hot-carriers having energies below the Si-SiO 2 energy barrier and found that transconductance degradation is mainly due to an interface state increase caused by drain avalanche hotcarrier injection.
Abstract: Device performance degradation due to hot-carriers having energies below the Si-SiO 2 energy barrier are examined. For a test device with L eff = 0.3 µm and T ox 5 nm, transconductance degradation and/or threshold voltage shift have been detected at a drain voltage of 2.5 V, which is lower than the Si-SiO 2 energy barrier(∼ 3.2 eV). In particular, transconductance degradation, rather than threshold voltage shift, is more noticeable. No sharp cut-off is shown near a drain voltage of 3 V. This transconductance degradation is mainly due to an interface state increase caused by drain avalanche hot-carrier injection. It was also found that the time, τ, that it takes for G_{m} or V_{th} to degrade a certain degree, can be expressed as \tau \propto (1/V_{D}) for a V D range of greater than 2.5 V. This degradation occurs in the same way as for long channel devices at V D > 3 V. Thus, hot carrier-related device degradation may be one of the most stringent problems in submicron MOS FETs, even after the power supply voltage is reduced.

39 citations


Journal ArticleDOI
TL;DR: In this article, a model for the drain I-V characteristics is proposed and a related model incorporating conductivity modulation that predicts linear relationships between the substrate and the collection currents and the drain current in this region of operation.
Abstract: When a short-channel MOSFET is driven into the avalanche-induced breakdown region, the drain current increases rapidly and usually shows a snapback characteristic. Both the substrate current and the current collected by a nearby reverse-biased p-n junction also increases with increasing drain current in this region of operation. All of these effects are associated with minority-carrier injection from the source junction into the substrate. A model for the drain I-V characteristics is proposed. Also presented is a related model incorporating conductivity modulation that predicts linear relationships between the substrate and the collection currents and the drain current in this region of operation. Experimental results agree well with the models.

37 citations


Patent
08 Nov 1983
TL;DR: In this article, a gate electrode having a non-coplanar surface with respect to the substrate and a deposited semiconductor material overlying the gate electrode is used to form a current conductor channel between a source and drain.
Abstract: A new and improved thin film field effect transistor and method provides such a transistor having increased operating frequencies and higher output currents. The transistor includes a gate electrode having a non-coplanar surface with respect to the substrate and a deposited semiconductor material overlying the gate electrode to form a current conductor channel between a source and drain. The length of the current conduction channel is determined by the thickness of the gate electrode which can be accurately controlled. As a result, short channel lengths are possible without high precision photolithography for high output currents and fast operating speeds. Further, a gate insulator is disposed between the gate and the deposited semiconductor. The gate insulator, which can be a gate oxide, can be annealed prior to the deposition of the deposited semiconductor to provide enhanced field effect mobilities. This further increases the transistor output currents and operating speeds.

34 citations


Journal ArticleDOI
TL;DR: In this paper, a model for CAD analysis of small geometry MOSFET's is presented, which includes drain induced barrier lowering phenomena, the narrow channel effect and the hot carrier phenomena.
Abstract: A d.c. model for the CAD analysis of small geometry MOSFET's is presented. It includes the drain induced barrier lowering phenomena, the narrow channel effect and the hot carrier phenomena. A single current expression valid in continuous way over the entire range of operation, including the subthreshold and the saturation regimes, is provided.

32 citations


Patent
Jacob D. Haskell1
25 Nov 1983
TL;DR: In this article, an improved short-channel field effect transistor including a standard tip implant type of source and drain each disposed in the surface of a semiconductor substrate and a gate electrode positioned upon the substrate between the source and the drain was presented.
Abstract: An improved short-channel field effect transistor including a standard tip implant type of source and drain each disposed in the surface of a semiconductor substrate and a gate electrode positioned upon the substrate between the source and drain and control plugs disposed in the substrate and associated with and contiguous to the source and drain for eliminating substrate punch-through currents without substantially increasing the device junction capacitance.

Patent
20 Apr 1983
TL;DR: In this article, the base-emitter voltage of a switching transistor is compared in a comparator with a reference voltage, and a switching-off device for switching off the driving pulses of the switching transistor responds to this signal.
Abstract: A protective circuit for a switching transistor is disclosed in which the base-emitter voltage of the switching transistor is compared in a comparator with a reference voltage. If the collector current of the switching transistor increases, the base-emitter voltage also increases, with the base current remaining constant. As soon as the base-emitter voltage exceeds the reference voltage, a signal is delivered at the output of the comparator. A switching-off device for switching off the driving pulses of the switching transistor responds to this signal so that a switching-on pulse present at the base of the switching transistor is switched off. The reference voltage is fixed so that the switching transistor is protected against overload by excessively large collector currents.

Patent
13 Apr 1983
TL;DR: In this article, a mobility modulation field effect transistor was proposed to increase the response speed of the field effect transistors considerably, which was shown to reduce the channel transit time of the carriers.
Abstract: A field effect transistor includes a conduction channel, the charge carrier mobility of which is modulated by applying a signal voltage to gate electrodes (2, 7). Typically the conduction channel includes more than one region (10, 11) each of different charge carrier mobility and the potential applied to the gate electrodes affects the charge carrier distribution between the two regions (10,11). This eliminates the limit in the response speed of the field effect transistor which is dependent upon the channel transit time of the carriers. A mobility modulation field effect transistor thereby increases the response speed of the field effect transistor considerably.

Patent
16 Sep 1983
TL;DR: An insulated gate transistor as mentioned in this paper is a driver transistor with a gate electrode made of a material having a high potential barrier with respect to the source region, which can be used as a switching transistor in a dynamic RAM memory cell, static RAM memory cells and in a complementary configuration.
Abstract: An insulated gate transistor including a semiconductor substrate, high impurity source and drain regions formed above a channel region of low conductivity, a high impurity concentration region having a conductivity type opposite to that of the source region, a gate insulating layer extending into the channel region farther inwardly of the substrate than the source region, and a gate electrode positioned on the gate insulating layer. The gate electrode is made of a material having a high potential barrier with respect to the source region. The insulated gate transistor may be used as a driver transistor in an integrated circuit, as a switching transistor in a dynamic RAM memory cell, static RAM memory cell and in a complementary configuration.

Patent
16 Nov 1983
TL;DR: In this article, a thin film insulated gate field effect transistor having an opposite conductivity type island in its channel region is described, and the island is electrically shorted to the transistor gate electrode.
Abstract: A thin film insulated gate field effect transistor having an opposite conductivity type island in its channel region. The island is electrically shorted to the transistor gate electrode.

Journal ArticleDOI
TL;DR: In this paper, experimental and theoretical results are presented on a bulk-barrier transistor (BBT), where the charge-carrier transportation is determined by an energy barrier, which is located inside a semiconductor.
Abstract: Experimental and theoretical results are presented on a bulk-barrier transistor (BBT). In this device the charge-carrier transportation is determined by an energy barrier, which is located inside a semiconductor. The barrier is the result of a space-charge region in a three-layered n-p-n or p-n-p structure with a very thin middle layer. The height of the energy barrier, which is adjustable by technological parameters, can be controlled by an external voltage.

Patent
11 Feb 1983
TL;DR: In this paper, a V-shaped groove is formed with an etching solution having high selectivity toward the crystal face in the gate region of a compound semiconductor crystal, and a metal likely to form an alloy type of Schottky junction with the compound semiconductors is vapor-deposited.
Abstract: A process for manufacturing a buried gate field effect transistor having a small effective gate length, which process enables precise control of the threshold voltage. First, a compound semiconductor crystal having a first impurity region as a source region, a second impurity region as a drain region and a channel layer buried inside the compound semiconductor crystal is prepared by a conventional process. A V-shaped groove is then formed with an etching solution having high selectivity toward the crystal face in the gate region of this compound semiconductor crystal. Onto the inner wall surface of the V-shaped groove, a metal likely to form an alloy type of Schottky junction with the compound semiconductor is vapor-deposited. The resultant structure is heated, while measuring the threshold voltage, to form an alloy type of Schottky junction and for use of this junction as a gate electrode.

Patent
18 Jan 1983
TL;DR: In this paper, a self-bias circuit is connected to a source circuit of a field effect transistor (FET) and the source circuit is substantially open-circuited at an oscillation frequency.
Abstract: An FET oscillator wherein a bias circuit is connected to a drain of a field-effect transistor and a source circuit including a transmission line and a self-bias circuit is connected to a source of the transistor, so that the source is substantially open-circuited at an oscillation frequency and the field-effect transistor operates as a two-terminal (the gate and drain) element exhibiting a negative resistance, and wherein a resonant circuit is connected to the gate of the transistor. With the source circuit connected to the transistor source, the oscillator can have a high unloaded Q-value of Qo and a high externally-loaded Q-value of Qext, whereby the oscillation frequency is stable. According to this oscillator, only a single bias circuit for the drain is required without the need of a bias circuit for the gate.

Patent
08 Nov 1983
TL;DR: In this paper, a gate insulator and gate electrode overly at least a portion of the deposited semiconductor adjacent to the source region to form a non-coplanar surface with respect to a substrate.
Abstract: A high performance, small area thin film transistor has a drain region, an insulating layer, and a source region at least portions of the edge of which form a non-coplanar surface with respect to a substrate. The insulative layer is formed in between the source and drain regions. A deposited semiconductor overlies the non-coplanar surface to form a current conduction channel between the drain and source. A gate insulator and gate electrode overly at least a portion of the deposited semiconductor adjacent thereto. The length of the current conduction channel is determined by the thickness of the insulative layer and therefore can be made short without precision photolithography. The non-coplanar surface can be formed by utilizing a dry process to simultaneously etch through several layers in a continuous one-step process. A second dielectric layer may be formed above the three previous layers. This decouples the gate electrode from the source region by creating two capacitances in series, thereby limiting further the capacitance between the gate electrode and the source region.

Journal ArticleDOI
TL;DR: In this article, a 2D finite-difference program for narrow gate MOSFETs and an accurate and efficient new finitedifference boundary equation at the oxide-semiconductor interface were used to compute the external threshold voltage and channel width as a function of the applied dc gate and substrate voltages.
Abstract: Lateral variation of the local threshold voltage causes non-linearity in the drain conductance-gate voltage characteristics, resulting in a nonunique external threshold voltage which varies with gate voltage. Using a 16-bit minicomputer, a two-dimensional (2-D) finite-difference program for narrow gate MOSFET (NAROMOS), and an accurate and efficient new finite-difference boundary equation at the oxide-semiconductor interface, computations are carried out for the external threshold voltage and a measurable electrical channel width as a function of the applied dc gate and substrate voltages. The depletion approximation is employed in order to compare the 2-D results with the 1-D analytical solution of the depletion model. Computed curves are presented for the lateral variations of the depletion layer thickness, surface potential, normal surface electric field, local as well as external threshold voltages, and electrical channel width as a function of the device structure, material parameters, and bias voltages. Based on the 2-D results and device physics, an analytical approximation of the threshold voltage versus the gate width, simple enough for CAD of VLSI, is derived whose parameters may be determined from either a 2-D computation or experimental measurements on one test device of a known gate width. The computed increase of the external threshold voltage with decreasing gate width compares well with published experimental data.

Patent
24 Feb 1983
TL;DR: In this paper, the authors describe the process of fabricating a dielectrically isolated junction field effect transistor and a PNP transistor on a common substrate, in which an epitaxially layer is deposited on the base substrate to form the channel region of the junction FET, and impurities for the source and drain of the FET are diffused into the epitaxial layer.
Abstract: The process of fabricating a dielectrically isolated junction field effect transistor and a PNP transistor on a common substrate. An epitaxially layer is deposited on the base substrate to form the channel region of the junction field effect transistor. Impurities for the source and drain of the field effect transistor are diffused into the epitaxial layer. Impurities to form the gate are diffused into the epitaxially layer between the source and gate regions but separated therefrom. The PNP transistor which is dielectrically isolated from the field effect transistor by grooves, is formed by the diffusion into the base substrate of the respective impurities that form the base, collector and emitter regions of the PNP transistor.

Patent
12 Oct 1983
TL;DR: In this article, the authors proposed to increase the ON/OFF ratio by providing a gate electrode through a gate insulator even under a thin semiconductor film, and applying the specific voltage, thereby reducing the OFF current and increasing the ON current.
Abstract: PURPOSE:To largely increase the ON/OFF ratio by providing a gate electrode through a gate insulator even under a thin semiconductor film, and applying the specific voltage, thereby reducing the OFF current and increasing the ON current. CONSTITUTION:A thin film transistor has an insulating transparent substrate 38, a substrate insulating film 39, a lower gate insulating film 40, a lower gate electrode 41, a thin semiconductor film 42, a source region 43, a drain region 44, an upper gate insulating film 45, an upper gate electrode 45, an interlayer insulating film 47, a source electrode 48, and a drain electrode 49. In order to decrease the OFF current, when the transistor is OFF, the voltage near the flat band voltage of the lower boundary is applied to the electrode 41, while to increase the ON current, when the transistor is ON, a voltage higher than a threshold voltage is applied to the electrode 41.

Proceedings ArticleDOI
01 Jan 1983
TL;DR: In this paper, a 0.5 micron triple diffused (LD3) NMOS transistor with a maximum operating voltage of 10 volts has been designed and fabricated, which is a low doped drain type with an additional boron region (halo) around the source/drain junctions.
Abstract: A 0.5 micron triple diffused (LD3) NMOS transistor with a maximum operating voltage of 10 volts has been designed and fabricated. The transistor is a low doped drain type (1,3,6) with an additional boron region (halo) around the source/drain junctions. By properly tailoring this boron profile, long channel behavior can be maintained down to the sub-micron level.

Patent
15 Jul 1983
TL;DR: In this paper, the authors proposed to improve high-frequency properties fT, saturation properties and etc, by forming a thick oxide film between a drain terminal and a gate electrode by high-pressure oxidation and by forming the p type region of the same conductive type as the substrate right under the channel part.
Abstract: PURPOSE:To improve high-frequency properties fT, saturation properties and etc, by forming a thick oxide film between a drain terminal and a gate electrode by high-pressure oxidation and by forming the p type region of the same conductive type as the substrate right under the channel part. CONSTITUTION:By forming a thick insulating film 8 of about 1mum thick between source and drain terminals and a gate electrode 5 by selective oxidation, the capacitance of the gate and drain CGD is reduced thereby improving fT. Furthermore, by forming the p type buried region 9 of higher concentration than that of the substrate's conductive type in the p type semiconductor substrate right under the channel part by ion implantation, e.g. of boron, a depletion layer 7 extends as shown by the broken line when a gate voltage VG is applied, so as to restrain a punch-through and to reduce the saturation properties which is peculiar to a short channel. At this time, the source and drain current flows in ID direction designated by the arrow through the channel part into the drain.

Journal ArticleDOI
TL;DR: Small-geometry buried-channel depletion MOSFETs (BCD-MOSFets) are characterized based on an analytical model that includes short-channel, narrow- channel, and carrier-velocity saturation effects andoretical results on drain current are in good agreement with experimental results.
Abstract: Small-geometry buried-channel depletion MOSFETs (BCD-MOSFETs) are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity saturation effects. The drain current is calculated based on the surface electrons induced by the gate-bias voltage and the buried-channel junction FET. The narrow-channel effect is modeled not only by the additional depletion-layer charges created by a fringing-field effect in the field region, but also by the effective channel width as a function of gate-bias voltage. Surface-electron mobility is modeled as a function of the vertical and lateral electrical fields created by the gate-bias and drain voltages, while bulk-electron mobility is described as a function of the lateral electric field due to the drain voltage. Theoretical results on drain current are in good agreement with experimental results.

Journal ArticleDOI
TL;DR: In this paper, thermal noise in HEMT devices is evaluated for arbitrary drain voltages including saturation, and the consequences of hot electron effects are indicated, and effects due to feedback via the series resistance Rs on the source side of the channel are evaluated.
Abstract: Thermal noise in HEMT devices is evaluated for arbitrary drain voltages including saturation. The results closely resemble those for MOSFETS. The consequences of hot electron effects are indicated, and the effects due to feedback via the series resistance Rs on the source side of the channel are evaluated. For very short channels the noise resistance Rn can be relatively large because the transconductance gmax at saturation is so much smaller than the drain conductance gd0 at zero drain bias.

Journal ArticleDOI
TL;DR: In this paper, closed form analytical expressions are developed to predict the threshold voltage of a small geometry MOSFET with a nonzero drain voltage, and two expressions are derived for abrupt oxide transition from the thin gate to thick field oxide with uniform doping and the effects of a tapered recessed field oxide.
Abstract: Closed form analytical expressions are developed to predict the threshold voltage of a small geometry MOSFET with a nonzero drain voltage. Two expressions are developed. The first expression is for an abrupt oxide transition from the thin gate to thick field oxide with uniform doping and the second expression includes the effects of a tapered recessed field oxide, and field doping encroachment at the channel edges. The theory is compared with experimental results obtained from n -channel small geometry MOSFETs.

Journal ArticleDOI
TL;DR: In this paper, the authors explain the number fluctuation noise in ion-implanted MOSFETs as a transition from surface channel flow at low drain bias to buried channel flow near the drain at elevated drain bias.
Abstract: 1 f noise in ion-implanted MOSFETs is not explained in terms of mobility fluctuation noise but as number fluctuation noise governed by a transition from surface channel flow at low drain bias to buried channel flow near the drain at elevated drain bias.

Journal ArticleDOI
TL;DR: In this article, the drift and diffusion components of the drain current in an MOST can be derived by taking into account the current-continuity equation, and analytical expressions for both the drift component and diffusion component are derived.
Abstract: It is shown that, by taking into account the current-continuity equation, analytical expressions for both the drift and the diffusion components of the drain current in an MOST can be derived. Also, these current components, which can be expressed as a function of the surface potential values at the source and at the drain ends of the channel, are reported against the voltages applied to the device.

Patent
Kevin J. O'Connor1
17 Feb 1983
TL;DR: In this article, a field effect transistor inverter-level shifter circuit which accepts TTL input level signals and generates MOS output level signals consists of the series combination of a load device, an enhancement mode transistor, and a depletion mode transistor.
Abstract: A field effect transistor inverter-level shifter circuit which accepts TTL input level signals and generates MOS output level signals consists of the series combination of a load device, an enhancement mode transistor, and a depletion mode transistor. The gates of the enhancement and depletion mode transistors are connected to an input terminal. The source of the enhancement transistor is connected to the drain of the depletion transistor. The depletion transistor acts to control the potential of the source of the enhancement transistor so as to allow it to tolerate worse case TTL input potential "0" levels while not becoming more than only weakly biased on.