Showing papers on "Drain-induced barrier lowering published in 1989"

MIS transistor structure for increasing conductance between source and drain regions

Abstract: A metal-insulator-semiconductor transistor comprises an insulator layer, a semiconductor body provided on the insulator layer and comprising a source region, a drain region and a channel region extending in a first direction between and interconnecting the source region and the drain region, a gate insulator film provided on the semiconductor body so as to cover the channel region except for the part of the channel region in contact with the insulator layer, and a gate electrode of a conductive material provided in contact with the gate insulator film so as to cover the channel region underneath the gate insulator film except for the part of the channel region in contact with the insulator layer. The channel region has a width substantially smaller than twice the maximum extension of the depletion region formed in the channel region.

A new asymmetrical halo source GOLD drain (HS-GOLD) deep sub-half-micrometer n-MOSFET design for reliability and performance

Abstract: A novel asymmetrical n-MOSFET device structure has been developed which is suitable, in terms of reliability and performance, for scaling down to the sub-quarter-micron level, without reduction of the supply voltage below 3.5 V. In this structure (HS-GOLD), large-tilt implantation is used to form the gate-overlapped lightly doped drain (GOLD) region at the drain electrode only. A halo (punch-through stopper) is used at the source, but not at the drain. Superior hot-carrier reliability and high punch-through resistance are obtained using this device structure. A reliability-limited supply voltage at 4.2 V is obtained for HS-GOLD n-MOSFETs with effective channel lengths as short as 0.25 mu m. High punch-through resistance is achieved without extreme scaling of S-D (source-drain) junctions and gate oxide (120 AA). The threshold roll-off characteristics suggest that this n-MOSFET structure can be designed with about 0.3 mu m shorter channel length (L/sub eff/=0.15 mu m) while maintaining the 3.5-V supply voltage. Reliable operation of 0.15- mu m n-MOSFETs at 3.5-V supply voltage using the proposed device structure is demonstrated by 2D simulation. >

Fermi threshold field effect transistor

Abstract: A field effect transistor (FET) operates in the enhancement mode without requiring inversion by setting the device's threshold voltage to twice the Fermi potential of the semiconductor material. The FET, referred to as a Fermi Threshold FET or Fermi-FET, has a threshold voltage which is independent of oxide thickness, channel length, drain voltage and substrate doping, the vertical electric field in the channel becomes zero, thereby maximizing carrier mobility, and minimizing hot electron effects. A high speed device, substantially independent of device dimensions is thereby provided, which may be manufactured using relaxed groundrules, to provide low cost, high yield devices. Temperature dependence of threshold voltage may also be eliminated by providing a semiconductor gate contact which neutralizes the effect of substrate contact potential. Source and drain subdiffusion regions may be provided to simultaneously maximize the punch-through and impact ionization voltages of the devices, so that short channel devices do not require scaled-down power supply voltages. Multi gate devices may be provided. An accelerator gate, adjacent the drain, may further improve performance. The Fermi-FET criteria may be maintained, while allowing for a deep channel by providing a substrate contact for the Fermi-FET and applying a substrate bias to this contact. Substrate enhancement pocket regions adjacent the source and drain regions may be provided to produce a continuous depletion region under the source, drain and channel regions to thereby minimize punch-through effects.

Process for forming high and low voltage CMOS transistors on a single integrated circuit chip

Abstract: A process for forming both low voltage CMOS transistors and high voltage CMOS transistors on a common integrated circuit chip uses a common implantation and drive-in step to form both the n-type well of each PMOS transistor and the n-type drain extension well of each lightly doped drain (LDD) NMOS transistor and a separate implant and drive-in to form the p-type drain extension well of each LDD PMOS transistor.

Vertical power mosfet having high withstand voltage and high switching speed

Abstract: In a vertical field effect transistor including a source electrode and a gate on the front surface of a semiconductor substrate having one conductivity type and a drain electrode on the back surface of the substrate, the semiconductor device of the present invention has the structure wherein a connection region of one conductivity type positioned between two channel forming base regions of the opposite conductivity type is formed by a semi­conductor layer having a higher impurity concentration than the drain region of the one conductivity type, and the surface portion of the connection region which is connected to the channel has a lower impurity concentration than the connection region.

Hot electron collector for a LDD transistor

Abstract: A lightly-doped drain (LDD) structure has conductive shield overlying the lightly-doped drain and source portions to collect and/or remove hot carriers which can otherwise cause instabilities such as gain degradation and threshold voltage shifts in short-channel MOS devices. The hot carriers eventually deteriorate the performance of the transistor to the point where the transistor provides insufficient performance. Thus, the lifetime of a transistor is affected by the degradation caused by the formation of hot carriers. The lifetime is increased by collecting the hot carriers in the conductive material over the lightly-doped source and drain.

Amorphous silicon thin film transistor with a depletion gate

Abstract: The present invention is a high speed thin film transistor with an accumulation gate and a depletion gate. When a positive voltage is applied to the accumulation gate, the electrons are accumulated in the channel region of the accumulation gate and the transistor is operated at the "on" state. If a negative voltage is applied to the depletion gate, the accumulated electrons are depleted, and the transistor is operated at the "off" state. The on-current of the thin film transistor is the same as that of conventional thin film transistors; however, a smaller off-current of the transistor is obtained.

Flash EPROM cell and method of making such cell

Abstract: A flash EPROM cell is fabricated using a two polysilicon enhancement mode n-channel transistor process. An active transistor region is formed in a silicon substrate (14) by growing a field oxide (16) around the region. A first polysilicon layer is deposited, etched, and oxidised to form an insulated control gate electrode (18). A second polysilicon layer is deposited over the active transistor region and the control gate electrode (18) and then anisotropically etched to remove all of the second polysilicon material except for a filament (20) adjacent to the control gate electrode (18), which forms a floating gate electrode (20). Source and drain regions (10, 12) are formed in the active transistor region with the control gate electrode (18) and the floating gate electrode (20) positioned over the channel region interconnecting the source and drain regions. The cell is programmed by hot electron channel current injection by proper voltage biasing of the control gate electrode (18) and drain (12). The cell can be either symmetrical or asymmetrical depending on the configuration of the floating gate filament electrode (20).

Smart body contact for SOI MOSFETs

Abstract: Summary form only given. SOI MOSFETs exhibit various floating-body effects due to the lack of a contact to the channel region. These effects can show up as a kink in the saturation region of I/sub DS/-V/sub DS/ characteristics (higher drive current) and an improvement of the subthreshold slope, or can be as severe as latch-up of the SOI MOSFET at large drain biases. The easiest was to eliminate floating-body effects is to provide a contact to the channel region to deep it at or below the source potential. One problem with providing a body contact is that the increased transistor drive current due to the floating-body effects is lost even in the saturation region, where it may be desirable for high-speed circuit operation. Here, a scheme for providing a smart body contact is presented. This contact acts as a low-resistance channel contact at low gate voltages to keep the transistor off and avoid latch-up. At high-gate voltages, the resistance of this body contact becomes very high and allows the MOSFET channel to float, which increases the drain current due to both MOS body effect and bipolar action. >

Process for reducing program disturbance in eeprom arrays

Abstract: A method by which the gate oxide in an EEPROM device is selectively thickened over the channel region nearest to the drain so as to penalize erase-type behavior during programming of a selected cell. First the lattice structure in a portion of the channel near said drain region is intentionally damaged to enhance subsequent thermal oxidation therein. Next, the channel is thermally oxidized to form the tunnel oxide for the device. Due to the damage inflicted in the portion of the channel near the drain, the tunnel oxide over the damaged region is thicker relative to the other portion of the channel. A thicker gate oxide near the drain thwarts drain disturbance in adjacent memory cells while speeding up source erase performance.

MOS transistor with a charge induced drain extension

Abstract: A process is taught which provides very shallow conductive regions in a semiconductor material by the formation of a fixed charge placed in an overlying dielectric layer which induces an inversion region in the underlying semiconductor. The inversion region so formed is used as a MOSFET drain extension between a drain contact region and the channel located beneath the gate region. The conductivity of the induced inversion region is controlled by the concentration of the ionic charge present in the dielectric layer.

Programmable interconnect or cell using silicided MOS transistors

Abstract: A programmable device (10) is formed from a silicided MOS transistor. The transistor 10) is formed at a face of a semiconductor layer (12), and includes a diffused drain region (17, 22) and a source region (19, 24) that are spaced apart by a channel region (26). At least the drain region (22) has a surface with a silicided layer (28) formed on a portion thereof. The application of a programming voltage in the range of ten to fifteen volts from the drain region (17, 22) to the source region (19, 24) has been discovered to reliably form a melt filament (40) across the channel region (26). A gate voltage (Vg) may be applied to the insulated gate (14) over the channel region (26) such that a ten-volt programming voltage (VPROG) will cause melt filaments to form in those transistors to which the gate voltage is applied, but will not cause melt filaments to form in the remaining transistors (10) of an array.

CMOS voltage multiplier

Abstract: A wholly integrated, multistage, CMOS voltage multiplier utilizes as a diode structure for transferring electric charge from an input node to an output node of each stage an enhancement type MOS transistor, the gate of which is coupled to the same switching phase to which the output capacitor of the stage is connected by means of a coupling capacitor. During a semicycle of charge transfer through said MOS transistor, the coupling capacitor charges through a second MOS transistor of the same type and having the same threshold of said charge transfer MOS transistor, connected in a diode configuration between the output node of the stage and the gate of the charge transfer MOS transistor, in order to cut-off the latter when reaching a voltage lower than the voltage reached by the output node by a value equal to the threshold value of said second transistor. In this way, a significant voltage drop across the charge transfer transistor is efficiently eliminated, thus allowing the generation of a sufficiently high output voltage though having available a relatively low supply voltage.

Submicrometer near-intrinsic thin-film SOI complementary MOSFETs

Abstract: Two-dimensional numerical simulations indicate that a surface-potential bending greater than the Si-film Fermi potential is required to reach the threshold condition for the near-intrinsic thin-film SOI (silicon-on-insulator) MOSFETs. Additionally, both n- and p-type SOI films result in approximately the same device threshold voltage when in the near intrinsic state and fully depleted condition. The threshold voltages of these devices are mainly dependent on the work function of gate material. High-performance submicrometer near-intrinsic thin-film SOI complementary MOSFETs with balanced threshold voltages of about 0.4 V (negative for PMOSFETs) are achievable with proper selection of gate material and back-gate bias. For very thin (less than 100 nm) SOI films, drain-induced barrier lowering (DIBL) is not sufficient to cause degradation of the threshold voltage or punchthrough behavior in the submicrometer region. For relatively thick (greater than 100 nm) SOI films, DIBL becomes more pronounced but can be suppressed by a proper back-gate bias. The simulated front-gate linear transconductance remains nearly constant up to about 10/sup 15/ cm/sup -3/ and then falls off rapidly with increasing doping concentration because of mobility degradation. The subthreshold slope increases with decreasing drain voltage as a result of DIBL, but the increase is small for very thin SOI films. >

Manufacturing method for LDDFETS using oblique ion implantion technique

Abstract: By symmetrically forming source and drain regions to the gate electrodes, electrically symmetrical transistor characteristics are obtained. After forming the first source and drain regions by large-tilt-angle ion implantation, without a sidewall in the gate electrode or after forming a sidewall shorter than the distance in the lateral direction of the second source and drain regions from the end of the mask for ion implantation, the diffusion of the second source and drain regions in the lateral direction is restricted to the maximum extent by heat treatment for a short time, and then the end of the gate electrode and the end of the second source and drain regions are matched, or their overlap region is formed. As a result, the manufacturing method of the MOS transistor results in both high performance and high reliability.

Physical mechanisms for short channel effects in polysilicon thin films transistors

Abstract: It is demonstrated that channel avalanched multiplication is the dominant mechanism giving rise to short-channel threshold shifts in n- and p-channel polysilicon thin-film transistors (TFTs) at moderate or high drain bias The effects are greater in nMOS TFTs than pMOS due to the higher ionization rates for electrons in comparison to holes At low drain bias, a charge sharing mechanism dominates and p-channel devices show greater threshold shifts Device design parameters such as gate oxide or active island thickness have little influence, and the most effective method for reducing the threshold shifts is to reduce the supply voltage When the supply voltage is scaled to maintain a fixed minimum threshold voltage, CMOS circuit speeds decrease at shorter gate lengths when a fixed capacitive load is driven, although in more complex circuits the speed improves >

Stacked channel heterojunction fet

Abstract: A field effect transistor comprising a high electron mobility field effect transistor (HEMT) portion and a metal-Schottky-gate field effect transistor (MESFET) portion having respective channel layers (10, 22) controlled by a common gate (26). At microwave and higher radio frequencies, the drain current capability of the HEMT portion reaches an upper limit; the MESFET portion takes over to provide drain current capability greater than this limit.

CMOS output circuit using a low threshold device

Abstract: A CMOS output driver includes an n-channel low threshold device in series between a p-channel transistor and an output terminal. Under normal driver operation, the low threshold transistor drops essentially zero volts and is imperceptible in the circuit. However, under special mode conditions when high voltage is applied to the output terminal, the low threshold transistor stops conducting when the output terminal approaches Vcc, so that any further increase in the voltage at the output terminal cannot be applied to the drain of the p-channel transistor which can cause its failure.

High voltage thin film transistor with second gate

Abstract: A high voltage thin film transistor comprises a charge transport layer, laterally disposed source and drain electrodes, a first gate electrode with one edge laterally overlapping the source electrode and another edge laterally spaced from the drain electrode. A source of high potential is continuously applied to the drain electrode and a source of low potential is applied to the first gate electrode in a time varying manner so as to form a first accumulation channel periodically in the charge transport layer, opposite to the first gate electrode. Device performance is improved by including a second gate electrode for forming a second, weaker, accumulation channel extending laterally from the region of the first accumulation channel toward the drain electrode. A source of potential is applied to the second gate electrode means for maintaining charge carriers within the second accumulation channel so as to prevent the charge transport layer from becoming depleted of charge carriers.

Control circuit for an inductive load

Abstract: The circuit according to the invention controls the supply to an inductive load by a power transistor of the N-channel MOS type, placed on the side of the positive terminal of a supply source delivering a voltage +Vbat. The conduction of the transistor is maintained by means of a gate voltage Vs>+Vbat supplied by a voltage multiplier. On cutting off this voltage, there is blocking of the transistor and discharge of the load, which rapidly develops a high negative voltage. An interconnecting transistor than prevents the return to conduction of the power transistor while, according to the invention, a transistor of the P-channel MOS type isolates the gate of the interconnecting transistor to authorize the application to said gate of the negative voltage developed by the inductive load. The invention has application to the control of actuators for the automobile industry.

Vertical MOS transistor

Abstract: A transistor structure is disclosed which has a vertical channel which has its length controllable by currently-used diffusion processes, and which occupies a minimum of silicon surface area. The transistor is constructed by using a triple-level implant and diffusion process. The drain region is diffused into the silicon area by way of ion implantation and subsequent diffusion. The channel region, of opposite conductivity-type from the drain region, is implanted and diffused into the drain region. The source region is similarly implanted, and diffused into the channel region. A trench is etched into the silicon, extending through the source, channel and drain regions; gate oxide is grown in the trench and a polysilicon gate is deposited in the trench, conformal with the gate oxide. Transistor action takes place in the channel region along the walls of the trench, dependent upon the voltage applied to the gate electrode. Series drain resistance, and gate-to-drain capacitance, is minimized by a deeper implant of the drain region away from the trench and under the electrical interconnection to the drain diffusion.

Semiconductor transmission gate with capacitance compensation

Abstract: A transmission gate employs a pair of capacitors ahead of and a pair of capacitors behind a transistor. One capacitor of each pair is supplied with a control voltage pulse that leads and the other with a control voltage pulse that lags the complement of a control voltage pulse supplied to the gate of the transistor. The capacitors are typically each a MOS transistor with the gate serving as one terminal and the drain and source shorted together and serving as the other terminal. Moreover, each of the capacitors has a capacitance equal to one half the capacitance of the gate to source and gate to drain capacitance of the transistor. This circuitry makes possible charge compensation to avoid the build up of trapped charge in the transistor. The capacitance of the pair of capacitors ahead of the transistor is approximately equal to the gate-to-drain parasitic of the transistor and the capacitance of the pair of capacitors behind the transistor is equal to the parasitic capacitance of the gate-to-source of the transistor.

Distributive nature of gate current and negative transconductance in heterostructure field-effect transistors

Abstract: Experimental data showing that the dependence of the gate current on the drain voltage in enhancement-mode heterostructure field-effect transistors changes qualitatively when the gate voltage is varied from below to above threshold are presented. The data lead to the conclusion that for gate voltages higher than the threshold voltage and drain voltages larger than the drain saturation voltage, most of the potential drop occurs in a small region near the drain end of the channel. The gate current is distributed along the channel so that electrons in the channel are diverted toward the gate. A model is proposed that takes into account such a distribution of the gate current along the channel. The distributive nature of the gate current leads to negative transconductance in heterostructure field-effect transistors at high gate voltages. Negative transconductance reaching -125 mS/mm in 1- mu m gate devices is observed, and an equivalent circuit model is proposed that describes the dependence of the drain current on the gate voltage in good agreement with present experimental data. >

E2 prom cell including isolated control diffusion

Abstract: An improved EEPROM having a cell including source and drain diffusions, a channel having a source region and a drain region, a floating gate that is disposed only over the drain region of the channel and has a coupling edge disposed adjacent to the drain diffusion to strongly capacitively couple the floating gate to the drain. During programming the floating gate voltage is increased, due to the capacitive coupling of the floating gate to the drain, which in turn inverts the drain region of the channel. The inversion of the drain region increases the coupling of the floating gate to the drain to increase electron tunneling to program the floating gate. Only three control signals are required to read, program, and erase the cell.

MOS thin film transistor

Abstract: Reduction of parasitic coupling capacitances which are otherwise formed between conventional NMOS transistor N type drain regions and the transistor's substrate and well regions is described by using a semiconductor-on-insulator (SOI) substrate and forming the NMOS transistor on a semiconductor (Si) substrate having a buried insulator forming a deep, lightly doped N type subsurface region beneath the conventional surface drain region (but not the source region) which contacts the buried insulator.

Tunnel EEPROM with overerase protection

Abstract: The present invention provides protection against the effects of overerasure while essentially maintaining a single transistor per memory cell through the use of an additional transistor for each row of memory cells. The added transistor is a positive voltage threshold device which is coupled between the connected sources of the floating gate transistors and a read input line to limit the threshold voltage. For programming, a second transistor with a negative voltage threshold is coupled in the same manner, but is coupled to a program input line. The positive threshold transistor prevents an unselected transistor from turning on during a read operation.

Method for manufacturing a depletion type double-diffused metal-oxide semiconductor field effect transistor device

Abstract: A method for manufacturing double-diffused metal-oxide-semiconductor field effect transistor (DMOSFET) device is to form an insulating layer having an opening in top surface on a semiconductor wafer, channel regions and well regions and source regions through two stage diffusions of impurity materials respectively of a different conductivity type from and the same conductivity type as the wafer and carried out through the opening, and further gate, source and drain electrodes are formed after masks provided on a surface area where the drain regions and the source electrode regions that are to be connected to the well regions and source regions and a further ion-implantation of an impurity material of the same conductivity type as the wafer into the channel regions, with the threshold voltage controlled to achieve a depletion type. The channel regions are relatively lower in the carrier concentration than the other parts in the well regions to achieve a high breakdown voltage notwithstanding that the device is of the depletion type.

Conductance-modulated integrated transistor structure

Abstract: Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each including a source and drain region with a gate contact positioned therebetween, an ohmic contact to the source regions, and a Schottky contact to each of the drain regions. The dopant concentration of the drain regions is sufficiently low to prevent the Schottky contact from forming an ohmic contact with the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two Schottky contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the Schottky diodes. Minority and majority carriers injected by the Schottky diodes modulate the channel regions, thereby lowering their resistivity and increasing the transconductance of the device without increasing the physical size or the capacitance of the device and thereby improving the speed of the device.

Rugged lateral DMOS transistor structure

Abstract: A lateral DMOS transistor includes a high conductivity substrate having an epitaxial layer grown thereon to have a resistivity suitable for the transistor body. A highly doped topside body contact is diffused into the epitaxial layer along with an abutting heavily doped source. The source is self-aligned with a conductive polysilicon gate lying on top of a thin gate oxide. After source diffusion the gate is oxide coated so as to be fully insulated. A main drain electrode portion is diffused near the opposing side of the gate spaced a distance away. A lightly doped drain region portion extends between the main drain region and the edge of the gate providing the required surface breakdown behavior. The main drain diffusion portion is extended into the epitaxial layer so that the spacing between the heavily doped substrate and the drain diffusion produces depletion region reach through at a voltage that is lower than the drain avalanche voltage. Several embodiments are set forth for practicing the invention.

Method of making asymmetrically optimized CMOS field effect transistors

Abstract: A process for forming an asymmetrically structured pair of CMOS field effect transistors having feature refinements matched to the individual idiosyncrasies of the p-channel and n-channel transistors. Complementary transistors are formed using a single photolithographic mask and a fabrication sequence which begins with the p-channel transistor source/drain formation. Thereafter, the p-channel transistor source/drain regions are metalized, the n-channel transistor lightly doped drain regions are formed, and the sidewall dielectric spaced n-channel transistor source/drain regions are formed using the p-channel metalization as a mask. The p-channel transistor source/drain metalization suppresses the effects of the relatively greater p-type source/drain resistivity, while the LDD structure of the n-channel transistor reduces performance degradation attributable to hot electron trapping. The structural asymmetry attributable to the process materially offsets performance limitations common to the individual CMOS transistor types.