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Showing papers on "Drain-induced barrier lowering published in 1993"


Journal ArticleDOI
TL;DR: In this article, the threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep submicrometer range has been investigated.
Abstract: The threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V/sub th/ on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V/sub th/ dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined. >

466 citations


Journal ArticleDOI
TL;DR: An analytical model for the subthreshold regime of operation of short-channel MOSFETs is presented, and expressions for the thresholdvoltage shift associated with the drain-induced barrier lowering (DIBL) caused by the application of a drain bias are developed as discussed by the authors.
Abstract: An analytical model for the subthreshold regime of operation of short-channel MOSFETs is presented, and expressions for the threshold-voltage shift associated with the drain-induced barrier lowering (DIBL) caused by the application of a drain bias are developed. The amount of drain-bias-induced depletion charge in the channel is estimated, and an expression for the distribution of this charge along the channel is developed. From this distribution, it is possible to find the lowering of the potential barrier between the source and the channel, and the corresponding threshold-voltage shift. The results are compared with experimental data for deep-submicrometer NMOS devices. Expressions for the subthreshold current and for a generalized unified charge control model (UCCM) for short-channel MOSFETs are presented. The theory is applicable to deep-submicrometer devices with gate lengths larger than 0.1 mu m. The model is suitable for implementation in circuit simulators. >

146 citations


Patent
29 Nov 1993
TL;DR: In this article, a vertical field effect transistor (1400) and diode (1450) were formed on a single III-V substrate and the diode cathode and the transistor drain or collector were formed in a common layer (1408).
Abstract: A vertical field effect transistor (1400) and diode (1450) formed on a single III-V substrate. The diode cathode and the transistor drain or collector may be formed in a common layer (1408).

120 citations


Journal ArticleDOI
J.C. Huang1, G. Jackson1, S. Shanfield1, A. Platzker1, P. Saledas1, C. Weichert1 
TL;DR: In this paper, a model based on surface states was proposed to explain this phenomenon, which then led to the use of charge-screen layers and a double-recessed gate process to suppress surface effects.
Abstract: The authors determined that RF drain current degradation is responsible for the poor power performance of wide-recessed pseudomorphic high-electron-mobility transistors (PHEMTs). A model based on surface states was proposed to explain this phenomenon, which then led to the use of charge-screen layers and a double-recessed gate process to suppress surface effects. Combined, these two modifications increased the device's gate-drain reverse breakdown voltage without causing a degradation in the transistor's RF drain current. This allowed the simultaneous achievement of high power-added efficiency and high power density which established a new performance record for power PHEMTs at X- and Ku-bands. Delay time analysis of single- and double-recessed PHEMTs revealed that the benefit of a larger breakdown voltage in the latter device design came at the cost of a larger drain delay time. Drain delay accounted for 45% of the total delay when the 0.35- mu m double-recessed PHEMT was biased at V/sub ds/=6 V. >

88 citations


Journal ArticleDOI
09 May 1993
TL;DR: In this paper, transient threshold voltage shifts are characterized with respect to their dependence on stress amplitude and duration, relaxation time, gate bias, substrate bias, drain voltage, temperature, and channel width and length.
Abstract: MOSFETs subjected to large-signal gate-source voltage pulses on microsecond to millisecond time scales exhibit transient threshold voltage shifts which relax over considerably longer periods of time. This problem is important in high-accuracy analog circuits where it can cause errors at the 12 b level and above. In this paper, transient threshold voltage shifts are characterized with respect to their dependence on stress amplitude and duration, relaxation time, gate bias, substrate bias, drain voltage, temperature, and channel width and length. In contrast to previous studies, threshold voltage shifts are measured at time and voltage scales relevant to analog circuits, and are shown to occur even when the effects of Fowler-Nordheim tunneling, avalanche injection, hot carriers, trap generation, self-heating, mobile ions, and dipolar polarizations are absent. A new model is proposed in which channel charge carriers tunnel to and from near-interface oxide traps by one of three parallel pathways. Transitions may occur elastically, by direct tunneling between the silicon band edges and an oxide trap, or inelastically, by tunneling in conjunction with a thermal transition in the insulator or at the Si-SiO/sub 2/ interface. Simulations based on this model show excellent agreement with experimental results. The threshold voltage shifts are also shown to be correlated with 1/f noise, in corroboration of the tunneling model. Techniques for the minimization and modeling of errors in circuits are presented. >

86 citations


Patent
Yoshitaka Sugawara1
17 Nov 1993
TL;DR: In this paper, a MOSFET is formed of an n source, a p well, an n drain and a mOS gate electrode, and a bipolar transistor is formed with an n emitter, a base and an n collector formed in sequential order adjacent to the n drain.
Abstract: According to the present invention, a MOSFET is formed of an n source, a p well, an n drain and a MOS gate electrode, a bipolar transistor is formed of an n emitter, a p base and an n collector formed in sequential order adjacent to the n drain. These transistors are formed by being merged with each other by the contact of n drain and the n emitter of the same conductivity type. Holes are injected into the drain of a voltage-driven type transistor comprised of the MOSFET from the bipolar transistor having a very small collector saturation resistance. With this, it is possible to give rise to conductivity modulation in the drain of the MOSFET, while the power dissipation of the voltage-driven type semiconductor device becomes very small.

84 citations


Patent
Kodama Noriaki1
16 Aug 1993
TL;DR: In this article, an ion implantation for forming a drain region is repeated more than twice at different angles, and the drain region has an impurity profile gently changed by virtue of the ion implantations at the different angles so that a drain disturbe is effectively suppressed.
Abstract: In a process of fabricating a floating gate type field effect transistor, an ion implantation for forming a drain region is repeated more than twice at different angles, and the drain region has an impurity profile gently changed by virtue of the ion implantation at the different angles so that a drain disturbe is effectively suppressed, thereby improving the stability of the data bit stored in the floating gate type field effect transistor.

84 citations


Patent
27 Sep 1993
TL;DR: In this paper, a silicon carbide field effect device with a drift region and a channel region is presented, where the drift region extends adjacent the drain region and the channel region extends between the source and drain regions.
Abstract: A silicon carbide field effect device includes vertically stacked silicon carbide regions of first conductivity type, extending from a lowermost drain region to an uppermost source region. In between the drain and source regions, a drift region and a channel region are provided. The drift region extends adjacent the drain region and the channel region extends between the drift region and the source region. Control of majority carrier conduction between the source and drain regions is provided by a plurality of trenches, which extend through the source and channel region, and conductive gate electrodes therein. To provide high blocking voltage capability and low on-state resistance, the doping concentration in the drift region is selected to be greater than the doping concentration of the channel region but below the doping concentration of the drain and source regions. Preferably, the material used for the gate electrodes, the spacing between adjacent trenches and the doping concentration of the channel region are chosen so that the channel region is depleted of majority charge carriers when zero potential bias is applied to the gate electrodes.

83 citations


Proceedings ArticleDOI
Mizuno1, Okamura, Toriumi
17 May 1993
TL;DR: In this paper, the threshold voltage fluctuatioris of 8k NMOSFETs in a less than 0.8mm2 area, using a newly developed 256x32 transistor array with a 8-bit binary counter.
Abstract: Increasing the number of transistors and scaling down the dimensions of the transistors in ULSIs are considered to enhance the fluctuations of the transistor characteristics, from the viewpoint of the channel doping fluctuations [l], 121. However, the statistical study of the transistor fluctuations has not been experimentally performed. In this paper, we have focussed on the threshold voltage V,, fluctuatioris of 8k NMOSFET’s in a less than 0.8mm2 area, using a newly developed 256x32 transistor array with a 8bit binary counter. It is experimentally shown for the first time that the V,, fluctuatioris depend on the channel length and the gate oxide thiclmess. Furthermore, it is directly demonstrated that the V,, fluctuations correlate with the dopant number fluctuations of the channel region.

73 citations


Patent
15 Mar 1993
TL;DR: In this article, a gate electrode is removed for self-alignment to selectively implant impurities only into end portions of a source region and a drain region, and the impurity concentration in the channel region is ununiform.
Abstract: Insulating films formed on side walls of a gate electrode are removed for a self-alignment to selectively implant impurities only into end portions of a source region and a drain region. Therefore, p + -type semiconductor regions are selectively formed only on sides near a channel region of the source and the drain regions. A punch through of the source or drain region is prevented by the p + -type semiconductor regions controlling an inversion threshold voltage. Therefore, the impurity concentration of the p-type substrate can be settled low, and the semiconductor transistor device can be miniaturized without increasing a parasitic junction capacitance. Moreover, since the impurity concentration in the channel region is ununiform, a drivability of the transistor can be increased. As a result, a semiconductor transistor device with a high withstand voltage and a high drivability in which the inversion threshold voltage can be easily controlled, and a method for producing the same are provided.

68 citations


Patent
16 Feb 1993
TL;DR: In this paper, an improved insulated-gate, field effect transistor and a three-sided junction-gate field-effect transistor are connected in series on the same chip to form a high-voltage MOS transistor.
Abstract: An embodiment of the present invention is an improved insulated-gate, field-effect transistor and a three-sided, junction-gate field-effect transistor connected in series on the same chip to form a high-voltage MOS transistor. An extended drain region is formed on top of a substrate of opposite conductivity material. A layer of material with a conductivity opposite to that of the material of the extended drain region is buried within the extended drain region such that field-effect pinch-off depletion zones extend both above and below the buried layer. A top layer of material similar to the substrate is formed by ion implantation through the same mask window as the extended drain region. The top layer covers the buried layer and extended drain region and itself is covered by a silicon dioxide layer above. Current flow through the extended drain is controlled by the substrate and buried layer when a voltage is applied to pinch-off the extended drain between them in a familiar field-effect fashion.

Patent
Jaewon Lee1
17 Dec 1993
TL;DR: In this article, a thin-film transistor was proposed to prevent the generation of a leakage current and to improve the operation stability of the transistor by using a reverse bias voltage suppression method.
Abstract: A thin film transistor wherein generation of a leakage current is prevented to improve the operation stability thereof and a method for manufacturing the same. A polysilicon layer is formed on an insulating layer. A gate insulating layer is formed on the polysilicon layer. A gate electrode having a barrier layer formed thereon is formed on the gate insulating layer. The sidewall surface portion of the gate electrode is anodic oxidized to form a metal oxide layer on the sidewall of the gate electrode. A lightly doped drain region having a lower impurity concentration than that of source and drain regions of the thin film transistor or an offset region wherein no impurity is doped is formed in a portion of the polysilicon layer under the metal oxide layer. The thin film transistor may be manufactured by a low temperature process, and leakage current is suppressed when a reverse bias voltage is applied. Therefore, the operation stability of the thin film transistor is improved.

Patent
09 Nov 1993
TL;DR: In this paper, a semiconductor device is provided with a high-voltage portion including NMOS transistor (78) and PMOS transistor(82b) and a low-voltages portion including N- and N+ regions self-aligned with sidewall spacers formed on the sidewalls of the gate.
Abstract: A semiconductor device (76) is provided with a high-voltage portion including NMOS transistor (78) and PMOS transistor (82b) and a low-voltage portion including NMOS transistor (80) and PMOS transistor 82(a). The high-voltage NMOS transistor (78) includes source/drain regions (90a, 90b) having N- regions (90a 1 , 90b 1 ) that are self-aligned with a gate (78) and N+ regions (90a 2 , 90b 2 ) that are self-aligned with sidewall spacers (91) formed on sidewalls of the gate (78) to improve reliability under continuous high voltage operating conditions. The low voltage NMOS transistor includes source/drain regions (92a, 92b) that are self-aligned with sidewall spacers (92) to permit channel lengths to be scaled to less than 2 microns. The low-voltage PMOS transistor (82a) and high-voltage PMOS transistor (82b) include source/drain regions (116a-116d) that are self-aligned with sidewall spacer extension regions (110a) formed over sidewall spacers (91) permitting low-voltage PMOS transistor channel lengths to be scaled to less than 2 microns.

Patent
09 Mar 1993
TL;DR: In this article, a layer of titanium nitride over the N-channel and P-channel source/drain areas which acts as a barrier to phosphorus or boron atom outdiffusion so that the junction doping levels remain low in the source/ drain areas.
Abstract: Processes for fabrication of: an N-channel raised source/drain MOSFET transistor; an N-channel and P-channel raised source/drain MOSFET device; and an N-channel raised source/drain MOSFET in conjunction with a DRAM memory cell capacitor. The process deposits a layer of titanium nitride over the N-channel and P-channel source/drain areas which acts as a barrier to phosphorus or boron atom outdiffusion so that the junction doping levels remain low in the source/ drain areas, and N-channel and P-channel junctions will be shallow. The titanium nitride layer will serve as a dopant atom barrier in a capacitor storage node, an N-channel source/drain area, and a P-channel source/drain area.

Journal ArticleDOI
Hans-Oliver Joachim1, Y. Yamaguchi1, K. Ishikawa1, Y. Inoue1, T. Nishimura1 
TL;DR: In this article, a modified boundary condition for the two-dimensional Poisson equation is introduced to account for the nonlinear potential distribution inside the buried oxide, and it is found that the S-factor short-channel degradation is governed by three mechanisms: the rise of capacitances at the channel source and drain ends due to the twodimensional potentional distribution; the subthreshold current flow at the back channel surface; and the modulation of the effective current channel thickness during the gate voltage swing in the sub-reshold region.
Abstract: The subthreshold slope in ultra-thin-film fully depleted SOI MOSFETs is investigated for channel lengths from the long channel region down to 0.1 mu m. A doping effect is found which allows improvement of the S-factor by increasing the channel doping concentration. In order to explain this phenomenon and to clarify the mechanism of S-factor degradation at short gate lengths, a two-dimensional analytical model is developed. A modified boundary condition for the two-dimensional Poisson equation is introduced to account for the nonlinear potential distribution inside the buried oxide. It is found that the S-factor short-channel degradation is governed by three mechanisms: the rise of capacitances at the channel source and drain ends due to the two-dimensional potentional distribution; the subthreshold current flow at the back channel surface; and the modulation of the effective current channel thickness during the gate voltage swing in the subthreshold region. The analytical model results are compared to those of numerical device simulation, and a good agreement is found. >

Patent
Steven L. Merchant1, Emil Arnold1
08 Feb 1993
TL;DR: In this paper, a method and thin film transistor having a linear doping profile between the gate and drain regions was presented, which achieved a significantly high breakdown voltage of the order of 700 to 900 volts, much greater than that achieved in the prior art.
Abstract: The present invention is directed to a method and thin film transistor having a linear doping profile between the gate and drain regions. This is constructed in a particular manner in order to achieve a thin film transistor having a significantly high breakdown voltage of the order of 700 to 900 volts, much greater than that achieved in the prior art.

Patent
Bernard L. Morris1
28 Oct 1993
TL;DR: In this paper, an integrated circuit is disclosed comprising a first field effect transistor having a source connected to a first node and a gate connected to the second node, and a second field-effect transistor for protecting the first transistor from voltages that are greater than a predetermined nominal voltage.
Abstract: An integrated circuit is disclosed comprising a first field effect transistor having a source connected to a first node and a gate connected to a second node, and a second field effect transistor for protecting the first transistor from voltages applied to the first node and greater than a predetermined nominal voltage. The second transistor includes a drain connected to the second node, a source connected to the first node, and a gate connected to a third node. A constant voltage source is coupled to the third node and supplies a gate voltage to the gate of the second transistor such that a drain-source path of the second transistor does not conduct while voltage applied to the first node is generally less than the gate voltage plus a threshold voltage of the second transistor. The constant voltage source comprises a third field effect transistor having a drain and a gate connected to the third node, and a source coupled to a first power supply voltage, such that the gate voltage is substantially equal to the first power supply voltage minus a threshold voltage of the third transistor.

Patent
Kazumi Kurimoto1
14 Oct 1993
TL;DR: In this paper, a MOS FET is constructed with a downwardly protruding convex shape, where a thick region of gate insulation film is positioned between the drain diffusion regions and the most closely adjacent part of the gate electrode, whereby gate-to-drain stray capacitance and the vertical component of electric field within the lightly doped drain diffusion region are reduced.
Abstract: Structures and methods of manufacture are described for a MOS FET that is suitable for extreme miniaturization, of a type in which lightly doped drain and source diffusion regions are formed respectively adjoining the conventional highly doped drain and source diffusion regions in the semiconductor substrate surface, for reducing electric field concentration in the drain region. The underside of the gate electrode of the FET is formed with a downwardly protruding convex shape, so that a thick region of gate insulation film is positioned between the drain diffusion regions and the most closely adjacent part of the gate electrode, whereby gate-to-drain stray capacitance and the vertical component of electric field within the lightly doped drain diffusion region are reduced. The underside of the gate electrode can be formed in the required shape by various methods which effectively utilize self alignment and are easily adapted to currently used types of LSI manufacturing process.

Patent
Hideaki Arima1, Makoto Ohi1, Natsuo Ajika1, Atsushi Hachisuka1, Tomonori Okudaira1 
02 Feb 1993
TL;DR: In this article, a semiconductor memory device is proposed in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced.
Abstract: Disclosed is a semiconductor memory device in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced. The semiconductor memory device includes, on the side of a gate electrode at which the capacitor is connected, a sidewall formed to have a width larger than that of a sidewall on the side of a bit line, and a source/drain region to which the capacitor is connected and which is formed to have a diffusion depth larger than that of the opposite source/drain region. Therefore, the source/drain region effectively prevents defects in crystal from being produced in the junction region between the capacitor and the source/drain region connected to the capacitor and the sidewall effectively reduces the short channel effect.

Journal ArticleDOI
Hussein I. Hanafi1, W.P. Noble, R.S. Bass, K. Varahramyan, Y. Lii, A.J. Dally 
TL;DR: In this paper, a model that attributes roll-up as well as roll-off to lateral redistribution of doping near the source and drain junctions is proposed, which is caused by crystal defects formed during post-source/drain-implant anneal.
Abstract: Experimental data and simulation results for submicron MOSFETs are reported and used to support a physical explanation for two important anomalies in the dependence of device threshold voltage on channel length. They are the widely observed increase in threshold voltage with decreasing channel length (roll-up), and the more recent observation that the ultimate threshold voltage decrease (roll-off) occurs at a rate which is far in excess of that which can be explained with conventional models of laterally uniform channel doping. A model that attributes roll-up as well as roll-off to lateral redistribution of doping near the source and drain junctions is proposed. This lateral redistribution is caused by crystal defects formed during post-source/drain-implant anneal. The resulting profile consists of an enhancement of background doping adjacent to the junction edge, bounded by a depression of the doping farther into the channel. >

Patent
16 Mar 1993
TL;DR: In this article, an improved current source having high output impedance, low saturation voltage, and less sensitivity to process parameters is achieved by having enhancement P-channel transistor devices used as current mirror, while depletion P-Channel transistor devices are provided as the cascode devices.
Abstract: An improved current source having high output impedance, low saturation voltage, and less sensitivity to process parameters is achieved by having enhancement P-channel transistor devices used as current mirror, while depletion P-channel transistor devices are provided as the cascode devices. A "diode connected" depletion device may be inserted between the enhancement gate and the drain of the current reference transistor to reduce saturation voltage. The "diode connected" depletion device keeps the drains of the enhancement devices at a similar voltage even when the enhancement and depletion device threshold, i.e. V T , do not track over temperature or process. Thus, the current mirror circuit provides not only higher output impedance, lower saturation voltage, but is also less sensitive to process variation.

Patent
16 Apr 1993
TL;DR: In this article, the authors proposed a laterally spreading N-type diffusion region with impurity concentration level higher than P-type and N-Type wells but lower than source and drain regions.
Abstract: A CMIS transistor suitable for device miniaturization, elimination of degradation of operational characteristics by hot carrier effect, and elimination of decrease of threshold voltage caused by short channel effect, includes a laterally spreading N-type diffusion region having an impurity concentration level higher than P-type and N-type wells but lower than source and drain regions, such that the N-type diffusion region extends laterally into a part located immediately below an edge of an insulating gate and has a depth smaller than a depth of the source and drain regions. The device is thereby capable of increasing the width of depletion layer at the bottom of the source and drain regions while maintaining effectiveness as a punch-through stopper. Thereby, the junction capacitance at the source and drain regions is reduced and the operational speed of the device improved in the P-channel transistor part in the device. In the N-channel transistor part, an effective suppression of punch-through is achieved because of the small diffusion depth of the N-type diffusion region. Thereby, the decrease of threshold voltage caused by the short channel effect is effectively eliminated even when the gate length of the transistor is reduced.

Patent
10 Sep 1993
TL;DR: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and the drain terminals of all other stages, is described in this paper.
Abstract: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and drain terminals of all other stages, a second N type field effect control transistor device having drain and source terminals connecting the drain terminal and the gate terminal of the first switching transistor device, and a storage capacitor joined to the source terminal of the first device; a source of voltage to be pumped is connected to the drain terminal of the first device of the first stage. A first series of clock pulses is applied to the gate terminals of the first switching transistor devices in every other stage of the charge pump and to the gate terminals of the second control transistor devices in stages between; and a second series of clock pulses which do not overlap the first series of clock pulses is applied to the gate terminals of the first switching transistor devices in alternate stages of the charge pump and to the gate terminals of the second control transistor devices in stages between the alternate stages. These pulses cause the switching transistor to switch on and off in alternate stages in a manner that the gate terminal goes higher than the drain terminal so that charge is transferred without threshold drop between stages and high current as well as high voltage is pumped to the output terminal.

Patent
08 Jul 1993
TL;DR: In this article, an improved ETOX-type flash memory cell which requires only a single 5-volt power supply for read, write and erase functions was proposed. But the drain junction depth was not reduced, due to the low diffusivity of antimony during high-temperature cycling.
Abstract: An improved ETOX-type flash memory cell which requires only a single 5-volt power supply for read, write and erase functions. By substituting antimony or the combination of antimony and arsenic for the usual arsenic drain dopant, drain junction depth is reduced, due to the low diffusivity of antimony during high-temperature cycling. In order to maximize the concentration of antimony in the drain region, which is limited to approximately 3×10 19 atoms/cm 3 (due to solid solubility characteristics of antimony at standard silicon process activation temperatures in the 800°-1,000° C. range), an antimony implant concentration of approximately 1×10 15 atoms/cm 2 is employed. The resulting shallow junction raises the electric field strength at the cell's drain junction, thus increasing the hot electron generation rate and improving the programming efficiency. The decreased junction depth also acts to improve short channel effects such as punch-through and drain-to-gate capacitive coupling. The addition of a boron halo implant to obtain a traditional doubly diffused drain further enhances programming efficiency.

Patent
28 May 1993
TL;DR: In this article, a circuit is provided for supplying a negative high voltage to an integrated circuit from a high positive voltage source Vpp, where the negative voltage is applied to a plurality of FLASH EPROM cells.
Abstract: A circuit is provided for supplying a negative high voltage to an integrated circuit from a high positive voltage source Vpp. The negative voltage is applied to a plurality of FLASH electrically erasable programmable read only memory (EPROM) cells. The circuit includes an oscillator coupled to a voltage converter which provides a periodic signal. The periodic signal is coupled to a charge pump (3) including three P-channel type transistors to produced the negative voltage. The source and drain of the first transistor (41) is coupled to the periodic signal. The second transistor's (43) gate and drain is coupled to a reference ground potential with the source coupled to the first transistor's gate. Finally, the third transistor's drain and gate is coupled to the first transistor's gate and the third transistor's source outputs negative voltage to floating gates of the plurality of FLASH EPROM cells during an erase operation. Further, the negative voltage generated is relatively precise, so no regulation is required.

Patent
25 Feb 1993
TL;DR: In this article, the authors proposed a separation of the source region and the drain region from the electrically insulating layer to prevent a parasitic channel from forming, thereby reducing leakage current and making the semiconductor device more efficient.
Abstract: A semiconductor device comprises a complementary MOS transistor integrated circuit formed in a semiconductor single crystal silicon disposed on an electrically insulating layer. A thickness of the single crystal silicon in a region in which an N-type MOS transistor is formed is made thicker than the thickness in a region in which a P-type MOS transistor is formed. By this structure, the bottoms of the source region and the drain region of the N-type transistor are separated from the electrically insulating layer by a predetermined distance. The separation of the source region and the drain region from the electrically insulating layer is effective to prevent a parasitic channel from forming, thereby reducing leakage current and making the semiconductor device more efficient.

Patent
04 Jan 1993
TL;DR: In this paper, the flyback voltage is felt through the vertical pnp transistor at the drain, which onducts to the substrate, which represents a power loss and a source of heat.
Abstract: When a field effect transistor is used to control the current through an inductive load, the flyback voltage is felt through the vertical pnp transistor at the drain, which onducts to the substrate. This current represents a power loss and a source of heat. This invention supplies a second lateral transistor which conducts this current back to the power supply.

Patent
Takanori Ozawa1
19 Mar 1993
TL;DR: In this article, a nonvolatile memory device with a field effect transistor for storing is described, which includes source and drain regions in a semiconductor substrate with a channel region interposed between them and a gate electrode above the channel region with a ferroelectric gate film sandwiched between them.
Abstract: A nonvolatile memory device having a field effect transistor for storing, which includes source and drain regions in a semiconductor substrate with a channel region interposed between them and a gate electrode above the channel region with a ferroelectric gate film sandwiched between them. Barrier metal is formed in contact with the source region of the field effect transistor for storing to make a Schottky diode in serial connection with the field effect transistor for storing. In reading information, voltage is applied to a serial circuit consisting of the field effect transistor for storing and the Schottky diode to turn the Schottky diode on.

Patent
25 Oct 1993
TL;DR: In this article, a gate region is formed on a surface of the substrate and a drain region of the first conductivity type is formed in contact with a second end of the extended drain region.
Abstract: In a method for constructing a semiconducting device, within a substrate of a first conductivity type there is formed a well of second conductivity type. Within the well, an extended drain region of a first conductivity type is formed. An insulating region over the extended drain region is formed. A gate region is formed on a surface of the substrate. A first side of the gate region is adjacent to a first end of the extended drain region. A drain region of the first conductivity type is formed. The drain region is in contact with a second end of the extended drain region. A source region is formed on a second side of the gate region.

Patent
19 Feb 1993
TL;DR: In this article, a bulk charge modulated MOSFET for sensing light comprising a semiconductor substrate with a gate region of a first conductivity type formed in the substrate.
Abstract: A bulk charge modulated MOSFET for sensing light comprising a semiconductor substrate with a gate region of a first conductivity type formed in the substrate. The gate region forms a potential well for carriers of the first conductivity type. The well is formed at a substantial depth from the surface of the gate region. The carriers are formed responsive to incident light. The gate region collects the carriers generated at depths less than the well. A source region of a second conductivity type is formed in the semiconductor substrate laterally adjacent the gate region. The source region is operable to sense a change in threshold voltage of the MOSFET responsive to the collection of carriers by the gate region. A drain region of the second conductivity type is formed in the layer adjacent the gate region and spaced from the source. The drain region is connected to a voltage source. The voltage source is pulsed to create a large potential well that extends under the gate region from the source to the drain during charge integration period and a smaller potential well during readout period.