Showing papers on "Drain-induced barrier lowering published in 1994"

Current/voltage characteristic collapse in AlGaN/GaN heterostructure insulated gate field effect transistors at high drain bias

Abstract: The authors describe the current/voltage characteristic collapse under a high drain bias in AlGaN/GaN heterostructure insulated gate field effect transistors (HIGFETs) grown on sapphire substrates. These devices exhibit a low resistance state and a high resistance state, before and after the application of a high drain voltage, respectively. At room temperature, the high resistance state persists for several seconds. The device can also be returned into the low resistance state by exposing it to optical radiation. Electron trapping in the gate insulator near the drain edge of the gate is a possible mechanism for this effect, which is similar to what has been observed in AlGaAs/GaAs HFETs at cryogenic temperatures.

Method for forming a field-effect transistor including anodic oxidation of the gate

Abstract: An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.

Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation

Abstract: A dynamic threshold voltage IGFET such as a MOSFET is operable at voltages of 0.6 volt or less. The threshold voltage of the transistor is reduced to zero volt or less by interconnecting the gate contact and the device body in which the voltage controlled channel is located. Several efficient connections using through hole plating or polycrystalline silicon gate extension are disclosed. A higher power supply voltage can be used by interconnecting the gate and device body through a smaller MOSFET.

Semiconductor device with an MOST provided with an extended drain region for high voltages

Abstract: The invention relates to a semiconductor device with a semiconductor body (1) comprising a surface region (3) of a first conductivity type which adjoins a surface and in which a field effect transistor is provided which comprises a channel region (7) with a gate electrode (8) above it, and a source region (4), a drain region (5) and a drain extension region (6). The drain extension region (6) serves to improve the drain breakdown voltage of the field effect transistor. In practice, a high breakdown voltage is accompanied by a comparatively high on-resistance of the transistor. According to the invention, the drain extension region (6) has a geometry different from that in known transistors, i.e . the drain extension region (6) comprises a number of zones (25) of the second conductivity type which extend from the channel region (7) to the drain region (5) and which have a width (26) and doping concentration such that, when the voltage difference across the blocked pn junction (28) between the surface region (3) and the drain extension region (6) is increased, the drain extension region (6) is fully depleted at least locally before drain breakdown occurs. The measure according to the invention renders it possible to choose the number and the width (26) of the zones (25) as an additional parameter of the device. It is a surprise to find that devices according to the invention have comparatively high drain breakdown voltages and comparatively low on-resistances which cannot be realised with a continuous drain extension region (6).

Voltage translation and overvoltage protection

Abstract: A voltage translator is provided that translates a lower voltage to a higher voltage, for example, a 3.3V voltage to a 5.0V voltage. The 3.3V voltage is received on source/drain terminal N1 of an NMOS transistor (130). The transistor gate is at 3.3V. The other source/drain terminal N2 of the transistor (130) is connected to an input of a CMOS inverter (138) powered by 5.0V. The inverter output is connected to the gate of a PMOS transistor connected between 5.0V and terminal N2. The PMOS transistor pulls terminal N2 to 5.0V when terminal N1 is at 3.3V. The same translator is suitable for translating a 5.0V voltage on terminal N1 to 3.3V on terminal N2 if the inverter is powered by 3.3V and the PMOS transistor is connected betwween 3.3V and terminal N2. Also, an output driver is provided in which a voltage protection circuitry prevents charge leakage from the driver output terminal to the driver's power supply when the voltage on the bus connected to the output terminal exceeds the power supply voltage.

Method for fabricating a field effect transistor with a self-aligned anti-punchthrough implant channel

Abstract: A structure and method for fabricating a field effect transistor (FET) having improved drain to source punchthrough properties was achieved. The method utilizes the selective deposition of silicon oxide by a Liquid Phase Deposition (LPD) method to form a self-aligning implant mask. The mask is then used to implant a buried anti-punchthrough implant channel under and aligned to the gate electrode of the FET. The buried implant reduces the depletion width at the substrate to source and drain junction under the gate electrode but does not increase substantially the junction capacitance under the source and drain contacts, thereby improving punch-through characteristic while maintaining device performance.

Brief review of the MOS device physics for low temperature electronics

Abstract: A brief review of the main physical phenomena involved in the cryogenic operation of CMOS silicon devices down to liquid helium temperature is given. Going from solid state physics towards electrical engineering point of views, several aspects such as the quantification of the inversion layer, the electronic transport in the 2D electron or hole gases, the scattering mechanisms, the impurity freeze-out in the substrate or in the lightly doped source and drain regions, the field-assisted impurity and impact ionization phenomena, the influence of series resistance and other parasitic effects (kink effect, hysteresis, transient, …) which alter the device characteristics will be discussed. The short channel effects such as drain induced barrier lowering, punch through, velocity overshoot will also be addressed.

High-performance insulated-gate field-effect transistor

Abstract: An improved device fabrication method and transistor structure 36 provide shallow, heavily doped, source/drain junction regions 64 and a uniformly doped lower gate region 50 having a high concentration of dopants efficiently distributed near the gate electrode/gate interface 51. The gate, source, and drain terminals of transistor 36 may be interconnected to other neighboring or remote devices through the use of reacted refractory metal interconnect segments 98 and 100. Transistor structure 36 of the present invention may be constructed in an elevated source/drain format to include elevated source/drain junction regions 87 which may be fabricated simultaneous with a primary upper gate electrode region 88. This elevated source/drain junction feature is provided without added device processing complexity.

Field effect transistor with crystallized channel region

Abstract: A semiconductor device which is excellent in reliability and electrical characteristics. The semiconductor device is formed on an insulating substrate. A channel region is formed between a source and a drain by the voltage applied to a gate electrode. The channel region, the source, and the drain are fabricated from a semiconductor having a large mobility. The other regions including the portion located under the channel region are fabricated from a semiconductor having a small mobility.

Low power, high performance junction transistor

Abstract: An improved junction transistor requiring low power and having high performance is described. The transistor includes a substrate, a well region of a first conductivity type, and source and drain regions of a second conductivity type separated by a channel region. The transistor further includes a gate region positioned on the surface of the substrate over the channel region, and a buried region of the first conductivity type is positioned within the well region and below the surface of the substrate. The buried region has a dopant concentration of the first conductivity type sufficiently high to slow the growth of source-drain depletion regions and diminish the likelihood of punch through. The buried region may take the form of a buried electrode region or a retrograde well in alternate embodiments. The device is characterized by a gate threshold voltage of at most about 150 mV which can be electrically adjusted using back biasing or floating gate techniques.

Process for fabricating a complementary MIS transistor

Abstract: A CMIS transistor suitable for device miniaturization, elimination of degradation of operational characteristics by hot carrier effect, and elimination of decrease of threshold voltage caused by short channel effect, includes a laterally spreading N-type diffusion region having an impurity concentration level higher than P-type and N-type wells but lower than source and drain regions, such that the N-type diffusion region extends laterally into a part located immediately below an edge of an insulating gate and has a depth smaller than a depth of the source and drain regions. The device is thereby capable of increasing the width of depletion layer at the bottom of the source and drain regions while maintaining effectiveness as a punch-thorough stopper. Thereby, the junction capacitance at the source and drain regions is reduced and the operational speed of the device improved in the P-channel transistor part in the device. In the N-channel transistor part, an effective suppression of punch-through is achieved because of the small diffusion depth of the N-type diffusion region. Thereby, the decrease of threshold voltage caused by the short channel effect is effectively eliminated even when the gate length of the transistor is reduced.

Semiconductor device having a protective transistor

Abstract: A semiconductor device has an internal circuit, an output transistor and a protective transistor for protecting the output transistor and the internal circuit against an ESD-induced destruction caused by a surge pulse entering from an input/output terminal. The sum of a first distance between a contact for connecting an input/output terminal with the collector of the protective transistor and a field oxide film and a second distance between a contact for connecting the input/output terminal with the emitter of the protective transistor and the field oxide film overlying the base of the laterally formed protective transistor is made smaller than the sum of a third distance between a contact for connecting the input/output terminal with the drain of the output transistor and the gate electrode of the output transistor and a fourth distance between a contact for connecting a potential line with the source of the output transistor and the gate electrode of the output transistor. Besides, the effective channel length of the output transistor is made longer than the effective base width of the protective transistor.

Apparatus and method for adjusting the threshold voltage of mos transistors

Abstract: An apparatus and method for adjusting the effective threshold voltage of a MOS transistor is disclosed. Reference voltage generation circuitry is used for generating a first voltage signal. Threshold voltage monitoring circuitry that includes the MOS transistor is used for measuring the effective threshold voltage of the MOS transistor and for generating a second voltage signal. Feedback circuitry compares the first voltage signal to the second voltage signal and adjusts the effective threshold voltage of the MOS transistor so that the first voltage signal is substantially equal to the second voltage signal. The effective threshold voltage of the MOS transistor is adjusted by adjusting its source-body voltage potential. The method includes the steps of generating a first voltage signal, measuring the effective threshold voltage of the MOS transistor, generating a second voltage signal, comparing the first voltage signal to the second voltage signal, and adjusting the effective threshold voltage of the MOS transistor so that the second voltage signal is substantially equal to the first voltage signal.

Method for fabricating insulated gate field effect transistor having subthreshold swing

Abstract: Insulated gate field effect transistors (10, 70) having process steps for setting the VT and a device leakage current which are decoupled from the process steps for providing punchthrough protection, thereby lowering a subthreshold swing. In a unilateral transistor (10), a portion (37, 45) of a dopant layer (25, 30) between a source region (48, 51) and a drain region (49, 52) serves as a channel region and sets the VT and the device leakage current. A halo region (34, 39) contains the source region (48, 51) and sets the punchthrough voltage. In a bilateral transistor (70), both a source region (83, 86) and a drain region (84, 87) are contained within halo regions (75, 74, 79, 81). A portion (76, 82) of a dopant layer (25, 30) sets the VT and a leakage current, whereas the halo region (75, 79) sets the punchthrough voltage.

EEPROM cell with the drain diffusion region self-aligned to the tunnel oxide region

Abstract: A method of semiconductor fabrication, in which a single aperture is used to define both a thin oxide tunneling region and a drain diffusion region in a self-aligned fashion, produces a device structure suitable for use in an electrically-erasableread-only memory (EEPROM) cell. A gate oxide is grown, then a photoresist mask is formed having a slit for ion implantation into the drain diffusion region. The oxide within the slit is etched away, and ion implantation forms a drain diffusion region. After the mask is stripped away, a healing furnace cycle removes the implant damage. A thin tunnel oxide layer is grown over the drain diffusion region, and then a polysilicon floating gate is formed so that one edge of this gate intersects a portion of the area of tunnel oxidation so as to form a small region of tunnel oxide under the floating gate. The process sequence then reverts to a conventional MOS flow. The self-aligned drain diffusion region and tunnel oxide region can be used in a variety of EEPROM cell designs. One embodiment involves a double-polysilicon, single-metal process in which three diffusion regions are used to form the EEPROM cell. The second layer of polysilicon overlies the floating gate and forms a control gate word line. The control gate and the floating gate overly the channel between the drain diffusion region and a common source diffusion region. The first layer of polysilicon is also used to form a select gate overlying the channel between the drain diffusion region and a select drain diffusion region. The metal layer provides contact to the select drain diffusion region and forms the bit line.

Method of driving ferroelectric memory

Abstract: A ferroelectric memory having a structure in which source and drain are formed on a semiconductor substrate, a ferroelectric thin film is formed on a channel region between the source and drain regions, and a ferroelectric gate transistor memory cell having a ferroelectric gate transistor structure including a gate electrode made of a conductive gate electrode, is arranged on the thin film. An X selection line (column) is connected to the gate of the memory cell, and a Y selection line (row line) is connected to the source and drain, or the column and row of the X and Y selection line are connected to the memory cell vice versa. The memory can be driven only by 1-transistor/1-cell without a pass gate transistor, and the data can be non-destructively read out by applying a voltage lower than the coercive voltage of the ferroelectric to the gate electrode, the source and drain.

Source/drain structural configuration for MOSFET integrated circuit devices

Abstract: A source/drain structural configuration suitable for metal-oxide semiconductor field-effect transistors is provided, having a wedge-shaped configuration with a thickness that increases in the direction from its end near to one the channel of the transistor toward the other end. The source/drain configuration includes a shallow junction advantageously formed to reduce sheet resistance and prevent the hot carrier punchthrough effect. The wedge-shaped source/drain configuration is fabricated by depositing a dielectric layer, which is flowable under thermal treatment, after the formation of a polysilicon gate electrode. After annealing, the dielectric layer is etched to form a wedge-shaped mask. The resulting mask has a thickness that decreases in the direction from its one end near the gate electrode toward the other end. The presence of the wedge-shaped shielding masks facilitates the formation of a pair of wedge-shaped source/drain regions on the substrate via implementation of an ion implantation procedure. The wedge-shaped mask also assists in achieving improved step coverage for the deposition of the pre-metal dielectric layer.

Detector for the detection of chemical species or photons using a field effect transistor

Abstract: The invention relates to a detector or sensor for the detection of chemical species or photons. This detector uses a field effect transistor having a semiconducting material substrate (1) in which are defined a source (3) and a drain (5), a gate (9) separated from the substrate by an insulating layer, an external energy source for polarizing the drain, source and gate of the transistor, a film (11), which is conductive or which can be rendered conductive and which is sensitive to the chemical species or photons to be detected, and an ammeter for measuring an electric current variation of the transistor. The arrangement of the film (11) between the connections of the gate (9) and the drain (5) makes it possible to modify the polarization voltage of the transistor gate under the effect of the species to be detected, which is represented by a variation of the current between the drain and the source, when the transistor is correctly polarized.

Floating gate memory device having discontinuous gate oxide thickness over the channel region

Abstract: A method and structure for a programmable read-only memory comprises a thin gate oxide over a source region and a thick gate oxide over the drain region. A semiconductor substrate is lightly doped and has regions of thin sacrificial oxide overlying what will become the transistor channel, source, and drain, and thick field oxide. The region that will become the transistor source is protected with photoresist, and the drain region and a portion of the channel is doped, for example, with boron. The resist and sacrificial oxide is stripped, and gate oxide is formed from the exposed silicon substrate. The more heavily doped drain and channel regions oxidize at a faster rate than the lightly doped source region, and thus the gate oxide formed is thicker. Floating and control gates are formed over the channel region, covering both the thicker and thinner gate oxide. The cell resulting from the process has increased coupling coefficient, easier programmability, and better storage of the charge on the floating gate than a conventional cell.

Method and apparatus for a two phase bootstrap charge pump

Abstract: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and drain terminals of all other stages, a second N type field effect control transistor device having drain and source terminals connecting the drain terminal and the gate terminal of the first switching transistor device, and a storage capacitor joined to the source terminal of the first device; a source of voltage to be pumped is connected to the drain terminal of the first device of the first stage. A first series of clock pulses is applied to the gate terminals of the first switching transistor devices in every other stage of the charge pump and to the gate terminals of the second control transistor devices in stages between; and a second series of clock pulses which do not overlap the first series of clock pulses is applied to the gate terminals of the first switching transistor devices in alternate stages of the charge pump and to the gate terminals of the second control transistor devices in stages between the alternate stages. These pulses cause the switching transistor to switch on and off in alternate stages in a manner that the gate terminal goes higher than the drain terminal so that charge is transferred without threshold drop between stages and high current as well as high voltage is pumped to the output terminal.

Detailed characterization and analysis of the breakdown voltage in fully depleted SOI n-MOSFET's

Abstract: The breakdown voltage in fully depleted SOI n-MOSFET's has been studied over a wide range of film thicknesses, channel dopings, and channel lengths. In lightly-doped films, the breakdown voltage roll-off at shorter channel lengths becomes much less severe as the film thickness is reduced. This is a result of improved resistance to punchthrough and DIBL effects in thinner SOI. Consequently, at channel lengths below about 0.8 /spl mu/m, ultrathin (50 nm) SOI can provide better breakdown voltages than thicker films. At heavier doping levels the punchthrough and DIBL are suppressed, and there is little dependence of breakdown voltage on film thickness. Two-dimensional simulations have been used to investigate the breakdown behavior in these devices. It is found that the drain-induced barrier lowering affects the breakdown voltage both directly, via punchthrough, and indirectly through its effect on the current flow and hole generation in the high-field regions. >

Methods for manufacturing low leakage current offset-gate thin film transistor

Abstract: A thin film transistor structure and methods of manufacture provide high ON/OFF current ratio and significantly reduce OFF state leakage currents. A doped thin film disposed on an insulating substrate is etched to form opposing source and drain regions. An undoped thin film is disposed between the opposing source and drain regions so that there is some overlap of the undoped thin film onto the top sides of the source and drain regions. Conventional photomasking, etching and ion implantation steps are then used to form a gate electrode offset from at least the drain region, and preferably offset from both source and drain regions, as well as conventional insulation and interconnect layers. The reduction in electric field intensity in the drain region, and the reduction in trap state density result from, performing heavy junction doping prior to deposition of the undoped thin film, and offsetting the gate electrode from the drain region. This structure provides very low OFF state leakage current while not seriously affecting the ON current. Several alternative fabrication processes are disclosed.

Temperature dependence of drain-induced barrier lowering in deep submicrometre MOSFETs

Abstract: A new method for extracting the drain-induced barrier lowering (DIBL) parameter in an MOS transistor is proposed. This method is used to study the influence of temperature on the DIBL effect. It is found that the DIBL parameter is almost independent of temperature between 50 and 300K. This method makes it also possible to recalculate the intrinsic output characteristics that the device would have in the absence of DIBL, and, in turn, to evaluate the intrinsic device saturation parameters.

Device and method for high performance high voltage operation

Abstract: A high voltage device (10) having MOS input characteristics. A low voltage MOS transistor (12) is provided which has a source (18), a drain (22), and a gate (25). A high voltage transistor (14) is also provided which has a source (20), a drain (24), and gate (16). The source (18) of the low voltage MOS transistor (12) is connected to the gate (16) of the high voltage transistor (14). The drain (22) of the low voltage MOS transistor (12)is connected to the source (20)of the high voltage transistor The low voltage MOS transistor (12) may have a silicon substrate and the substrate of the high voltage transistor (14)may comprise silicon, silicon carbide, or gallium arsenide.

An integrated device having MOS transistors which enable positive and negative voltage swings

Abstract: A semiconductor circuit integrated with CMOS circuits for receiving a TTL input voltage and generating a large negative and positive voltage swing with respect to p-type or n-type substrate is disclosed. This invention is based on elimination of the electro-static discharge (ESD) protection circuit which is a requirement for any integrated circuit. Eliminating the ESD protection circuit also eliminates the clamping feature of the ESD protection circuit and therefore the circuit can be driven to negative voltages for PMOS circuits and to positive voltages for NMOS circuits. This provides the possibility of connecting the drain of a a P-channel type metal oxide silicon field effect (PMOS) transistor, which is fabricated on a p-type substrate within an n-well, to a voltage below the the substrate voltage. Also, in a n-channel type metal oxide silicon field effect (NMOS) transistor which is fabricated on a n-type substrate within a P-well, the drain can be connected to voltages higher than the substrate voltage. Utilizing this feature of a MOS transistor provides a way to design an integrated circuit which can handle negative voltage swings as well as positive voltage swings.

Method for electrically characterizing the insulator in SOI devices

Abstract: A rapid method for determining electrical characteristics of SOI wafers whereby the silicon substrate acts as a gate and tungsten probes make a source and drain connection at the top silicon surface to form a point contact transistor. Drain current is measured as a function of gate voltage as gate voltage is swept from negative to positive values. The subthreshold voltage current characteristic exhibits a minimum drain current occurring close to zero gate voltage. The tungsten probe point contacts apparently are responding to both electron and hole conduction or simply intrinsic CMOS behavior. Using current voltage characteristics, estimates may be made of interface state density and oxide charge density. Analysis of the gate voltage shift for minimum drain current allows determination of threshold voltage shift due to radiation.

Current regulating semiconductor integrated circuit device and fabrication method of the same

Abstract: A semiconductor integrated device having a current regulating diode may be substantially reduced in size and improved in performance by forming the current regulating diode of a plurality of MOS transistors each having a gate, a drain region, and a source region formed in a semiconductor substrate, the source regions and the substrate regions being electrically coupled to each other, the drain regions of at least two of the MOS transistors being electrically coupled, and the source regions of each of the MOS transistors being electrically coupled, the coupled drain regions, the coupled source regions, and the coupled gates forming a drain terminal, a source terminal and a gate terminal, respectively. In order to set a desired regulated current, selected coupling lines in the current regulating diode may be cut. This may be accomplished, for example, by measuring a first current which flows in the drain terminal while applying a first voltage to the gate terminal and a second voltage to the drain terminal relative to an electric potential of the source terminal, then measuring a second current which flows in the drain terminal while applying a third voltage to the gate terminal and the second voltage to the drain terminal relative to an electric potential of the source terminal. In order to achieve the desired current characteristic, selected conductive lines between coupled drains or between coupled sources are then cut.

Modulation doped field effect transistor

Abstract: A modulation doped field effect transistor (10) is formed to have a drain (28, 12, 11) that is vertically displaced from the source (16, 17) and channel (20, 21) regions. The transistor (10) has the source (16, 17), channel (20, 21) and a portion of the drain (28) arranged laterally so that current (27) flows from the source (16, 17) laterally to the drain (28, 12, 11). A heterojunction layer (18) on the channel region (20, 21) facilitates forming a two dimensional electron gas in the channel (20, 21) region which provides the transistor (10) with a high transconductance.

Field effect transistor structure heavily doped source/drain regions and lightly doped source/drain regions

Abstract: A field effect transistor structure includes heavily doped source/drain regions and lightly doped source/drain regions, The lightly doped source/drain regions extend form the source drain regions partway under a sidewall spacer adjacent a gate electrode. Very lightly doped source/drain regions extend the remainder of the way under the sidewall spacers to provide improved transistor characteristics.

Metal oxide semiconductor transistors having a polysilicon gate electrode with nonuniform doping in source-drain direction

Abstract: The gate electrode of a polysilicon gate MOS transistor--the transistor having either a thin film polysilicon substrate or a bulk monocrystalline substrate--has a pair of contiguous regions: a heavily doped gate electrode region near the source, and a lightly doped gate electrode region near the drain. The gate electrode region near the drain is thus doped significantly more lightly, in order to reduce electric fields in the channel region in the neighborhood of the drain (and hence reduce field induced leakage currents) when voltages are applied to turn transistor OFF. At the same time, sufficient impurity doping is introduced into the gate electrode region near the source in order to enable the transistor to turn ON when other suitable voltages are applied.