Showing papers on "Drain-induced barrier lowering published in 1998"

Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors

Abstract: The authors report the characterization and analysis of a novel double-gate elevated-channel thin-film transistor (ECTFT) fabricated using polycrystalline silicon. The transistor has a thin channel and thick source/drain regions with a double-gate control. Using this structure, the kink effect in the I-V characteristics of a conventional TFT is completely eliminated, and leakage current at zero gate bias is reduced by over 15 times. The elimination of the kink effect and the significant reduction in leakage current are obtained due to the reduction in lateral electric field at the channel/drain junction region. Two-dimensional (2-D) device simulations are used to study the electric field reduction mechanism in the structure. Experimental results on the forward conduction and gate transfer characteristics of the structure are also presented.

Scalable MOS field effect transistor

Abstract: A field effect transistor and method for making is described incorporating self aligned source and drain contacts with Schottky metal-to-semiconductor junction and a T-shaped gate or incorporating highly doped semiconductor material for the source and drain contacts different from the channel material to provide etch selectivity and a T-shaped gate or incorporating a metal for the source and drain contacts and the oxide of the metal for the gate dielectric which is self aligned. The invention overcomes the problem of self-aligned high resistance source/drain contacts and a high resistance gate electrode for submicron FET devices which increase as devices are scaled to smaller dimensions.

Analysis of Drain Field and Hot Carrier Stability of Poly-Si Thin Film Transistors

Abstract: Hot carrier instabilities in poly-Si thin film transistors (TFTs) are caused by high electric fields at the drain. These high fields are determined mainly by the abruptness of the lateral n+ doping profile in the drain and the two-dimensional (2D) coupling of the x and y components of the electric field between the gate and drain. The density of trapping states in the poly-Si film, however, has a much less significant impact on the field. Further, it is shown that improving the properties of the poly-Si film tends to have an adverse affect on hot carrier stability. Consequently, it is concluded that drain field relief is essential for hot carrier stability of n-channel poly-Si TFTs. It is shown that gate overlapped lightly doped drain (GOLDD) architectures can be used to relieve the drain field without introducing series resistance. Stable TFTs have been fabricated with GOLDD, consistent with circuit operation up to drain biases of 20 V. GOLDD is also effective in reducing the field enhanced leakage current in the off-state.

Cross coupled thin film transistors and static random access memory cell

Abstract: A pair of thin film transistors formed in adjacent layers of polysilicon. The gate of the first TFT and the source, drain and channel regions of the second TFT are formed in the first polysilicon layer. The source, drain and channel regions of the first TFT and the gate of the second TFT are formed in the second polysilicon layer. A dielectric layer is interposed between the first and second polysilicon layers. The first TFT gate overlaps the second TFT drain region in the first polysilicon layer and the second TFT gate overlaps the first TFT drain region in the second polysilicon layer. In another aspect of the invention, two TFTs are incorporated into a SRAM memory cell. The memory cell includes: (i) a bit line; (ii) an access transistor having a first source/drain and a second source/drain, the first source/drain being electrically connected to the bit line; (iii) a parasitic diode formed between the second source/drain of the access transistor and the substrate; (iv) a pull down transistor having a source, drain, channel and gate; (v) a first TFT having a source, drain, channel and gate, the first TFT gate being coupled to a power supply voltage V cc through an active load device comprising a second TFT having a source, drain, channel and gate, and to a voltage not greater than ground through the pull down transistor; and (vi) a storage node for storing a high voltage representative of a first digital data state or a low voltage representative of a second digital state, the storage node being coupled to the bit line through the access transistor, to the substrate through the parasitic diode, to the pull down transistor gate and to the power supply voltage V cc through the first TFT.

Three mechanisms determining short-channel effects in fully-depleted SOI MOSFETs

Abstract: Mechanisms determining short-channel effects (SCE) in fully-depleted (FD) SOI MOSFETs are clarified based on experimental results of threshold voltage (V/sub T/) dependence upon gate length, and analysis using a two-dimensional (2-D) device simulator. Drain-induced barrier lowering (DIBL) effect is a well known mechanism which determines the SCE in conventional bulk MOSFETs. In FDMOSFETs, two more peculiar and important mechanisms are found out, i.e., the accumulation of majority carriers in the body region generated by impact ionization, and the DIBL effect on the barrier height for majority carriers at the edge of the source near the bottom of the body. Due to these peculiar mechanisms, V/sub T/ dependence upon gate length in the short-channel region is weakened. It is also shown that floating body effects, the scatter of V/sub T/, and transient phenomena are suppressed due to the SCE peculiar to FD MOSFETs.

A simple model for threshold voltage of surrounding-gate MOSFET's

Abstract: We propose a threshold voltage model for surrounding-gate MOSFETs. The model treats the ends and the double-gate regions of the channel as separate devices operating in parallel. The threshold voltage for the full device is obtained as the perimeter-weighted sum of the threshold voltages of the two parts enabling simple analytic threshold models to be used. Short channel effects and drain-induced barrier lowering are also modeled in this manner.

Leakage power reduction in low-voltage CMOS designs

Abstract: Lowering supply voltage is one of the most effective ways of reducing power dissipation. Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between the leakage current and the transistor threshold voltage in the weak inversion region, static current (and hence, static power power dissipation) can no longer be ignored. In this paper the author presents different design techniques such as multiple threshold voltage, dynamic threshold control, substrate biasing, and leakage control using transistor stacking to achieve large improvements in leakage power during both stand-by and active mode of operation.

ESD protection clamp for mixed voltage I/O stages using NMOS transistors

Abstract: An electrostatic discharge protection device for protecting a mixed voltage integrated circuit against damage is provided which includes at least one pair of NMOS transistors connected in a cascode configuration. Each NMOS transistor pair includes a first transistor, having a drain region coupled to an I/O stage of the mixed voltage integrated circuit, and a gate region coupled to the mixed voltage integrated circuit's low power supply. The protection device also includes a second NMOS transistor, merged into the same active area as the first transistor, having a gate region and source region coupled to the ground plane of the mixed voltage integrated circuit. The drain region of the second transistor and the source region of the first transistor is constructed by a shared NMOS diffusion region. This shared diffusion region also constructs the common node coupling the source region of the first transistor to the drain region of the second. The shared diffusion area is a further benefit of the invention because its length controls the trigger voltage and the holding voltage of each cascode configured transistor pair. This electrostatic discharge protection device can be used either as a self protecting pull-down portion of a mixed voltage I/O stage or, in a further aspect of the present invention, as a separate electrostatic discharge clamp.

Method for forming field effect transistor having multiple gate electrodes surrounding the channel region

Abstract: A field effect transistor comprising source and drain regions, a channel region composed of a semiconductor layer formed between the source and drain regions and gate electrodes disposed to at least three surfaces surrounding the channel region. The structure can increase the number of carriers induced in the channel region and enhance the current driving performance and mutual conductance as compared with the single gate structure or double gate structure.

Transistor circuit, display panel and electronic equipment

Abstract: PROBLEM TO BE SOLVED: To control, using an input signal of relatively low voltage, a transistor circuit in which the conductance of a drive transistor is controlled according to the voltage of an input signal and to compensate for variations in threshold characteristic of the drive transistor. SOLUTION: A transistor circuit 100 has a drive transistor 110 in which the conductance between its source and drain is controlled according to the voltage of an input signal supplied to its gate and a compensating transistor 120 whose gate is connected to either the source or drain so that its input signal is supplied to the gate of the drive transistor via the source and drain.

Disposable gate/replacement gate MOSFETS for sub-0.1 micron gate length and ultra-shallow junctions

Abstract: A counter-doped epitaxial silicon (doped opposite to the substrate type) is used to form the buried layer in a CMOS transistor, while maintaining an abrupt channel profile Shallow source/drain junctions with abrupt source/drain profiles may be formed using raised (or elevated) source/drain design The invention encompasses a transistor structure including a doped silicon substrate, and an oppositely-doped epitaxial silicon layer formed on the substrate A gate is formed on the epitaxial layer, the gate defining a channel region in the epitaxial layer underneath the gate A layer is formed on the epitaxial silicon layer on opposing sides of, and is electrically isolated from, the gate

Constant current programming waveforms for non-volatile memories

Abstract: An EEPROM MOSFET memory device with a floating gate and control gate stack above source and drain regions formed in a substrate self-aligned with the stack. There is a means for writing data to the floating gate electrode by applying an upwardly stepwise increasing control gate voltage V CG1 waveform applied to the control gate of the EEPROM device. The waveform is a voltage ramp providing a substantially constant tunneling current into the floating gate electrode which is approximately constant with respect to time so programming speed and the number of write/erase cycles is increased. The means for threshold voltage testing compares the voltage of the drain electrode to a reference potential. The ramped pulse output is supplied to the control gate electrode by producing a sequence of increasingly higher counts to a decoder which provides sequential switching of successively higher voltage pulses from a voltage divider, and there is means for providing ramping programming voltages to the successively higher voltage pulses.

Semiconductor diodes having low forward conduction voltage drop and low reverse current leakage

Abstract: Semiconductor diodes having a low forward voltage conduction drop, a low reverse leakage current and a high voltage capability suitable for use in integrated circuits as well as for discrete devices. The semiconductor diodes are fabricated as field effect devices having a common gate and drain connection by a process which provides very short channels, shallow drain regions and longitudinally graded junctions. Continuation of the gate/drain contact layer over specially located tapered edge field oxide (34) maximizes the breakdown voltages of the devices. The preferred fabrication technique utilizes four masking steps, all without any critical mask alignment requirements. Various embodiments are disclosed.

Buffer using dynamic threshold-voltage MOS transistor

Abstract: A buffer using a dynamic threshold-value MOS transistor reduces its power consumption. Since transmitted to an output signal (S 3 ) with some delay, transition of the input signal (S 1 ) from low to high, for example, is also transmitted to a body of a transistor (N 1 ) for a while. This increases the body potential to reduce the threshold value, thereby shortening time required to turn on the transistor (N 1 ). After that, the output signal (S 1 ) becomes completely high to turn off a transistor (P 2 ), which stops the transmission of the input signal (S 1 ) to the body of the transistor (N 1 ). At the same time, a transistor (N 2 ) is turned on, so that the body potential of the transistor (N 1 ) is grounded to be completely low. Thus, the threshold voltage is increased again. This prevents a current flow from body to source in the transistor (N 1 ), thereby reducing power consumption.

Multiple threshold voltage transistor implemented by a damascene process

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs include gate structures with a polysilicon material. The polysilicon material is implanted with lower concentrations of germanium where lower threshold voltage MOSFETs are required. Over a range of 0-60% concentration of germanium, the threshold voltage can be varied by roughly 240 mV. A damascene process can be utilized to fabricate the MOSFETs.

An analytical surrounding gate MOSFET model

Abstract: In this paper we present a complete and analytical drain current model for surrounding gate MOSFETs. The model was developed using a quasi-two-dimensional cylindrical form of the Poisson equation and based on the drift-diffusion equation. The model applicable for digital/analog circuit simulation contains the following advanced features: precise description of the subthreshold, near threshold and above-threshold regions of operation by one single expression; single-piece drain current equation smoothly continuous from the linear region to the saturation region; considering the source/drain resistance; inclusion of important short channel effects such as velocity saturation, drain-induced barrier lowering and channel length modulation.

Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion

Abstract: A method of reducing an effective channel length of a lightly doped drain transistor (50), includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and implanting a drain region (58) of the substrate (56) with a sub-amorphous large tilt angle implant to thereby supply interstitials (62) at a location under the gate oxide (54). The method also includes forming a lightly doped drain extension region (66) in the drain region (58) of the substrate (56) and forming a drain (70) in the drain region (58) and forming a source extension region (67) and a source (72) in a source region (60) of the substrate (56). Lastly, the method includes thermally treating the substrate (56), wherein the interstitials (62) enhance a lateral diffusion (84) under the gate oxide (54) without substantially impacting a vertical diffusion (86) of the extension regions (66, 67), thereby reducing the effective channel length without an increase in a junction depth of the drain (70) and the drain extension region (66) or the source (72) and the source extension region (67).

Semiconductor storage device capable of improving controllability of density and size of floating gate

Abstract: There is provided is a semiconductor storage device that can reduce a dispersion in characteristics such as a threshold voltage and a writing performance and has a low consumption power and a non-volatility. There are included a source region 9 and a drain region 10 formed on a silicon substrate 1, a channel region 3 a located between the source and drain regions 9 and 10, a gate electrode 8 that is formed above the channel region 3 a and controls a channel current flowing through the channel region 3 a, and a control gate insulating film 7, a floating gate 6 and a tunnel insulating film 4 that are arranged in order from the gate electrode 8 side between the channel region 3 a and the gate electrode 8. The floating gate 6 is comprised of a plurality of crystal grains 6 a linearly discretely arranged substantially parallel to the surface of the channel region 3 a.

Potential detect circuit for detecting whether output potential of potential generation circuit has arrived at target potential or not

Abstract: A resistance element and an N channel MOS transistor are connected in series between an output terminal of a voltage generation circuit in a flash memory and a line of a ground potential. A constant current is conducted to the MOS transistor, and the potential of the drain of the N channel MOS transistor is compared with a reference potential by a comparator. The voltage conversion factor becomes 1, so that the voltage detection accuracy is improved.

Dual-gate SOI transistor

Abstract: A dual-gate SOI transistor has self-aligned upper and lower gates, in which a gate trench that will hold the dual-gate structure is formed by damaging the oxide under the transistor active area and preferentially etching that damaged region with HF, thus producing a self-aligned opening that has less overlap of the lower gate and the source/drain junctions and is filled with LPCVD polysilicon to form a dual-gate structure having reduced capacitance compared with prior art devices.

Kilowatt power transistor

Abstract: A high-power high-voltage transistor has four or more semiconductor dies (14) mounted in thermal contact on a metal flange (12). Each die (14) has a flat lower surface with a drain (collector) region formed over at least 80 percent of its lower surface. A gate (base) region and a source (emitter) region are formed respectively on upper surfaces of the did. The drain region is seated in direct electrical and thermal contact with the flange (12), so that the flange serves as a drain lead for the transistor did (14). The did has a drain-source breakdown voltage (or collector-emitter breakdown voltage) on the order of one kilovolt or higher and an area of one hundred thousand square mils or larger. Molybdenum tabs (57) between the drain (collector) region and the flange protect the did from thermally-induced stresses. The dies can be MOSFET power transistors, bipolar junction transistors or other solid-state devices. An oval lead frame (60) can be employed for connecting to the source regions. A carousel arrangement carries an array of chips (114) on a circular flange (112). The transistor can be implemented as a DC grounded drain, RF common source amplifier circuit. The gate-source input can float, allowing the drain to be DC and thermally grounded. The RF current path is conventional common source (emitter).

Impact of epi facets on deep submicron elevated source/drain MOSFET characteristics

Abstract: Deep submicron elevated source/drain (S/D) MOSFET's with epi facets, without facets, and with a second sidewall spacer covering the facets were studied using two-dimensional (2-D) process and device simulations. A slight degradation of drain-induced-barrier-lowering /spl Delta/V/sub t/ (DIBL) has been projected due to the locally deeper junction beneath the epi facets. The locally deeper junction also shortens the S/D extension length if the spacer thickness is kept the same. The shorter extension in turn leads to a smaller parasitic resistance and therefore a higher device drive current. Gate-to-drain capacitance of the elevated S/D MOSFET is decreased as a result of faceting because of the reduced overlap area.

Insulated-gate field effect transistor and method for driving thereof

Abstract: An insulated-gate field effect transistor comprising a channel forming region, source/drain regions, a gate region, a bias supplying means, and a capacitive element, wherein a potential for controlling a gate threshold voltage of the insulated-gate field effect transistor in an off-state thereof is applied to the channel forming region through the bias supplying means, and a signal having approximately the same phase as a phase of a signal supplied to the gate region is supplied to the channel forming region through the capacitive element.

Epitaxial channel vertical MOS transistor

Abstract: A vertical MOS transistor includes an epitaxially formed channel between its lower source/drain region and upper source/drain region, with a gate electrode in a trench that extends vertically through those regions A process for forming the vertical MOS transistor implants the substrate to provide the lower source/drain region, then forms an epitaxial layer that provides the channel over the previously formed lower source/drain region Then, the upper source/drain region is implanted above the lower source/drain region and epitaxial channel layer, followed by formation of a vertical trench and polysilicon gate Forming the epitaxial layer over a previously implanted lower source/drain region allows independent control of the resistivity of the lower source/drain region, such that it can have low resistivity, facilitating device symmetry Also, the epitaxial channel layer has improved doping uniformity over diffusion type channel region, lowering channel length and increasing performance and yield Finally, the source/drain regions may incorporate two separate dopants to provide an extended region that further minimizes the channel length while providing higher punch through voltage levels and retaining low resistivity

Method and apparatus for measuring the threshold voltage of flash EEPROM memory cells being applied a variable control gate bias

Abstract: There is provided a method of measuring the value of the threshold voltage of a memory core cell in an array of flash EEPROM memory core cells. The memory core cell includes an array core transistor having a corresponding array threshold voltage which is to be measured. There is provided a reference current level at a constant value which is generated by a reference cell transistor having a fixed bias condition and a fixed threshold voltage so that the relationship of the bias voltage applied to its gate and the fixed threshold voltage is linear. A control gate bias voltage applied to the gate of the array core transistor having the array threshold voltage which is to be measured is varied continuously. The varied control gate bias voltage and the reference current level is compared so as to generate a high logic when the varied control gate bias voltage produces a core cell current which is greater than the reference current level to obtain immediately the value of the threshold voltage of the array core transistor.

V-band high-power low phase-noise monolithic oscillators and investigation of low phase-noise performance high drain bias

Abstract: This paper reports on the excellent performance of V-band monolithic high electron-mobility transistor (HEMT) oscillators, and discusses oscillation characteristics on drain bias. With regard to output characteristics, double-hetero (DH) HEMT (especially with a high-density Si-planar doped layer) are superior to single-hetero (SH) HEMT's. A monolithic microwave integrated circuit (MMIC) oscillator has been developed with a planar doped DH HEMT and has achieved the peak output power of 11.1 dBm at a 55.9-GHz oscillation frequency. Phase noise of -85 dBc/Hz at 100-kHz offset and -103 dBc/Hz at 1-MHz offset have been achieved at a drain voltage of 5.5 V and a gate voltage of 0 V. These characteristics have been achieved without any buffer amplifiers of dielectric resonators. This study has revealed that the phase noise decreases as drain voltage increases. This phenomenon is caused by lower pushing figure and lower noise level at a low-frequency range obtained under a high drain voltage. It is because the depletion layer in the channel is extended to the drain electrode with increase of drain voltage, resulting in the small fluctuation of the gate-to-source capacitance. We also investigate low-frequency noise spectra of AlGaAs-InGaAs-GaAs DH HEMT's with different bias conditions. The low-frequency noise decreases for more than 3 V of the drain voltage. A unique mechanism is proposed to explain this phase noise reduction at high drain voltage.

Constant current cmos output driver circuit with dual gate transistor devices

Abstract: In one aspect of the invention, an output driver circuit having an output terminal operatively coupled to a resistive termination load comprises: a dual gate pFET device including a source transistor and a drain transistor, each transistor respectively having a gate terminal, a source terminal and a drain terminal, the source terminal of the source transistor being operatively coupled to a voltage source V, the drain terminal of the source transistor being operatively coupled to the source terminal of the drain transistor, the drain terminal of the drain transistor being operatively coupled to the output terminal of the output driver circuit; a dual gate nFET device including a source transistor and a drain transistor, each transistor respectively having a gate terminal, a source terminal and a drain terminal, the source terminal of the source transistor being operatively coupled to a ground potential, the drain terminal of the source transistor being operatively coupled to the source terminal of the drain transistor, the drain terminal of the drain transistor being operatively coupled to the output terminal of the output driver circuit; first switching means, operatively coupled to the gate terminal of the source transistor of the dual gate pFET device, for turning on and off current flow from the voltage source V through the source transistor of the dual gate pFET device; second switching means, operatively coupled to the gate terminal of the source transistor of the dual gate nFET device, for turning on and off current flow to the ground potential through the source transistor of the dual gate nFET device; and bias generating means having a first output terminal operatively coupled to the gate terminal of the drain transistor of the dual gate pFET device and providing a first bias voltage to the drain transistor which is a function of a reference voltage associated with the resistive termination load and which substantially controls the amount of current provided by the drain transistor of the dual gate pFET device to the resistive termination load, the bias generating means also having a second output terminal operatively coupled to the gate terminal of the drain transistor of the dual gate nFET device and providing a second bias voltage to the drain transistor which is a function of the reference voltage associated with the resistive termination load and which substantially controls the amount of current provided by the resistive termination load to the drain transistor of the dual gate nFET device.

Fabrication process employing a single dopant implant for formation of a drain extension region and a drain region of an LDD MOSFET using enhanced lateral diffusion

Abstract: A method of making a lightly doped drain transistor includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and forming a drain (70) in a drain region (58) and a source (72) in a source region (60) of the substrate (56). The method further includes generating interstitials (62) near a lateral edge of at least one of the drain (70) and the source (72) and thermally treating the substrate (56). The thermal treatment cause the interstitials (62) to enhance a lateral diffusion (84) of the drain (70) under the gate oxide (54) without substantially impacting a vertical diffusion (82) of the drain (70) or the source (72). The enhanced lateral diffusion (84) results in the formation of at least one of a lightly doped drain extension region (75) and a lightly doped source extension region (76) without an increase in a junction depth of the drain (70) or the source (72). The step of generating interstitials (62) may include the step of implanting at least one of the drain region (58) and the source region (60) of the substrate (56) with a large tilt angle implant which creates the interstitials (62) at a location near the gate oxide (54).