Showing papers on "Drain-induced barrier lowering published in 2000"

Active matrix type display apparatus and drive circuit thereof

Abstract: Each of picture elements comprises an input transistor for accepting a signal current from a data line when a scanning line is selected, a conversion transistor for converting the signal current into a voltage and for holding thus converted voltage, and a drive transistor for driving a light emitting device with drive current corresponding to the converted voltage. The conversion transistor flows the signal current to its channel to generate the voltage corresponding to the converted voltage and a capacitor to restrain the generated voltage. Further the drive transistor flows the drive current corresponding to the voltage stored in the capacitor. In this case the threshold voltage of the drive transistor is set not to be smaller than the threshold voltage of the conversion transistor, and thereby a leakage current flowing through the light emitting device is suppressed.

A comparative study of gate direct tunneling and drain leakage currents in n-MOSFET's with sub-2 nm gate oxides

Abstract: This work examines different components of leakage current in scaled n-MOSFET's with ultrathin gate oxides (1.4-2.0 nm). Both gate direct tunneling and drain leakage currents are studied by theoretical modeling and experiments, and their effects on the drain current are investigated and compared. It concludes that the source and drain extension to the gate overlap regions have strong effects on device performance in terms of gate tunneling and off-state drain currents.

Exploring the novel characteristics of hetero-material gate field-effect transistors (HMGFETs) with gate-material engineering

Abstract: The novel characteristics of a new type of MOSFET, the hetero-material gate field-effect transistor (HMGFET), are explored theoretically and compared with those of the compatible MOSFET. Two conceptual processes for realizing the HMG structure are proposed for integration into the existing silicon technology. The two-dimensional (2-D) numerical simulations reveal that the HMGFET demonstrates extended threshold voltage roll-off to much smaller length and shows simultaneous transconductance enhancement and suppression of short-channel effects (SCEs) [drain-induced barrier-lowering (DIBL) and channel-length modulation (CLM)] and, more importantly, these unique features could be controlled by engineering the material and length of the gate. This work demonstrates a new way of engineering ultrasmall transistors and provides the incentive and guide for experimental exploration.

A method for locating the position of oxide traps responsible for random telegraph signals in submicron MOSFETs

Abstract: Random telegraph signals (RTS) have been measured in the drain to source voltage of W/spl times/L=0.97/spl times/0.15 /spl mu/m/sup 2/ medium-doped drain (MDD) n-MOSFET's. The depth of the trapping center in the oxide is found from the gate voltage dependence of the emission and capture times. The difference in the drain voltage dependence of the capture and emission times between the forward and reverse modes is utilized to find the position of the trap in the channel with respect to the source.

Ultra-thin elevated channel poly-Si TFT technology for fully-integrated AMLCD system on glass

Abstract: A novel low temperature poly-Si (LTPS) TFT technology called the ultra-thin elevated channel TFT (UT-ECTFT) technology is proposed. The devices fabricated using this technology have an ultra-thin channel region (300 /spl Aring/) and a thick drain/source region (3000 /spl Aring/). The ultra-thin channel region is connected to the heavily doped thick drain/source region through a lightly doped overlapped region. The ultra-thin channel region is used to obtain a low grain-boundary trap density in the channel, and the overlapped lightly doped region provides an effective way for electric field spreading at the drain, thereby reducing the electric field there significantly. With the low grain-boundary trap density and low drain electric field, excellent current saturation characteristics and high drain breakdown voltage are obtained in the UT-ECTFT. Moreover, this technology provides complementary LTPS TFT's with more than two times increase in on-current and 3.5 times reduction in off-current compared to conventional thick channel LTPS TFT's.

Polysilicon gate enhancement of the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFETs with ultrathin gate oxide

Abstract: In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFETs with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3D) "atomistic" simulation technique. MOSFETs with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled to thickness in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect of the polysilicon grain boundaries on the threshold voltage variation are also presented.

Active matrix display device including a transistor

Abstract: A transistor adapted to be used in an active-matrix liquid-crystal display, the channel length, of the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric fields is applied to these offset regions from the gate electrode.

Channel implant through gate polysilicon

Abstract: A field effect transistor having a doped region in the substrate immediately underneath the gate of the transistor and interposed between the source and drain of the transistor is provided. The doped region has a retrograde dopant profile such that the doping concentration immediately adjacent the gate is selected to allow for the formation of a channel when a threshold voltage is applied to the gate thereby eliminating the need for an enhancement doping step during formation of the transistor. The retrograde doping profile increases with the depth into the substrate which inhibits stray currents from traveling between the source and drain of the transistor in the absence of the formation of a channel as a result of voltage being applied to the gate of the transistor.

Power MOS transistor

Abstract: A new and improved power MOS transistor having a protective diode with an increased breakdown voltage difference and less sheet resistivity is disclosed. In an up-drain type MOSFET, an n-type well layer has its top surface in which an elongated p-type base region is provided adjacent to a deep n + -type region (drain region). The p-type base region is formed so that it partly overlaps the deep n + region. A p + -type region (p-type base region) is connected to a source electrode. A surge bypassing diode D 1 is thus formed between the source and drain of the MOSFET.

Low Power and Low Voltage MOSFETs with Variable Threshold Voltage Controlled by Back-Bias

Abstract: We have studied the characteristic trade-offs in low power and low voltage MOSFETs from the viewpoint of back-gate control and body effect factor. Previously reported MOSFET structures are classified into four categories in terms of back-gate structures. It is shown that a MOSFET with a fixed back-bias has only a limited current drive at low voltage irrespective of device structures, while current drive of a dynamic threshold MOSFET with body tied to gate is more enhanced with increasing body effect factor. We have proposed a new dynamic threshold MOSFET, electrically induced body (EIB) DTMOS, which has a very large body effect factor at low threshold voltage and high current drive at low supply voltage. key words: MOSFET, low power, low voltage, variable thresh-

Photoelectric conversion devices and photoelectric conversion apparatus employing the same

Abstract: A photoelectric conversion device comprises a semiconductor substrate, a same-dopant-type semiconductor layer, a photodiode having a charge-accumulation region, a JFET (which has a gate region, a source region, a channel region, and a drain region, the drain region electrically connected to the substrate 100), a transfer gate for transferring a charge from the photodiode to the gate region, and a reset drain having a charge-drain region for draining excess charges generated by the photodiode, the reset drain also controlling the electric potential of the gate region. Two overflow-control regions are included, one at the boundary between the charge-accumulation region and the charge-drain region within the device, one at the boundary between the charge-accumulation region and the charge-drain region of an adjacent device. Two reset gates are also provided, one at the boundary between the JFET gate and the reset drain within a device and one at the boundary between the JFET gate and a reset drain of an adjacent device. The layer is preferably more lightly doped relative to the substrate, such that sensitivity to longer wavelengths is increased. When used as a pixel in a pixel matrix, the device (and each pixel) may be surrounded by filled trenches extending downward from the top surface of the layer. The trenches may be filled so as to decrease the resistance between the substrate and the layer, and so as to reduce or eliminate cross-talk between pixels.

Active matrix display device having multiple gate electrode portions

Abstract: In a thin-film transistor of multi-gate structure, the width of a channel forming region 108 closest to a drain region 102 is made the narrowest. This prevents a transistor structure closest to the drain region from first deteriorating. Further, the channel length at the vicinity of a center of an active layer is intentionally widened, so that the amount of current flowing through the vicinity of the center of the active layer is decreased and the deteriorating phenomenon due to heat accumulation is prevented. Therefore, a semiconductor device with a high reliability is realized.

Threshold voltage generation circuit

Abstract: A threshold voltage generation circuit includes a control transistor, one or more load transistors, and a current mirror. The load transistors are diode-connected transistors that are operated in saturation. The source-to-gate voltage of the load transistors approximates the threshold voltage of the transistors over process and temperature. The operation of the circuit is affected by choosing a bias voltage for the control transistor, the sizes of the control transistor and load transistors, and the ratio of transistor sizes within the current mirror.

High voltage MOS transistor with up-retro well

Abstract: A high voltage MOS transistor is provided that is compatible with low-voltage, sub-micron CMOS and BiCMOS processes. The high voltage transistor of the present invention has dopants that are implanted into the substrate prior to formation of the epitaxial layer. The implanted dopants diffuse into the epitaxial layer from the substrate during the formation of the epitaxial layer and subsequent heating steps. The implanted dopants increase the doping concentration in a lower portion of the epitaxial layer. The implanted dopants may diffuse father into the epitaxial layer than dopants in the buried layer forming an up-retro well that prevents vertical punch-through at high operating voltages for thin epitaxial layers. In addition, the doping concentration below the gate may be light so that the threshold voltage of the transistor is low. Also, the high voltage transistor of the present invention may be isolated from the substrate and the buried layer, and have symmetrical source and drain regions so that it can be used as a pass transistor.

New simple procedure to determine the threshold voltage of MOSFETs

Abstract: A new alternative technique is proposed to extract the threshold voltage from the subthreshold-to-strong inversion transition region of MOSFETs. It uses an auxiliary operator that involves integration of the drain current as a function of gate voltage. Tests show that the procedure produces results comparable to conventional methods.

Lateral high voltage transistor having spiral field plate and graded concentration doping

Abstract: A lateral high voltage transistor device is disclosed. The transistor includes a gate, a drain, and a source. The drain is located apart from the gate to form an intermediate drift region. The drift region has variable dopant concentration between the drain and the gate. In addition, a spiral resistor is placed over the drift region and is connected to the drain and either the gate or the source of the transistor.

A 25-nm-long Channel Metal-Gate p-Type Schottky Source/Drain Metal-Oxide-Semiconductor Field Effect Transistor on Separation-by-Implanted-Oxygen Substrate

Abstract: A 25-nm-long channel metal-gate PtSi Schottky source/drain metal-oxide-semiconductor field effect transistor (MOSFET) fabricated on a separation-by-implanted-oxygen (SIMOX) substrate was demonstrated. The drain current and transconductance were 293 µA/µm and 431 mS/mm, respectively.

High-voltage MOS transistor

Abstract: A high-voltage MOS transistor wherein a dopant concentration of a source offset region is set lower than a dopant concentration of a drain offset region whereby a resistance value of the resource region is set independently of a resistance value of the drain region in such a manner as to maintain a high sustaining breakdown voltage of the high-voltage MOS transistor, which is based on a voltage of the source offset region and a voltage of a substrate region directly under a gate insulating film during operation of the high-voltage MOS transistor.

Fabrication of a field effect transistor with minimized parasitic Miller capacitance

Abstract: A field effect transistor is fabricated to have a drain overlap and a source overlap to minimize series resistance between the gate and the drain and between the gate and the source of the field effect transistor. The parasitic Miller capacitance formed by the drain overlap and the source overlap is reduced by forming a depletion region at the sidewalls of the gate structure of the field effect transistor. The depletion region at the sidewalls of the gate structure is formed by counter-doping the sidewalls of the gate structure. The sidewalls of the gate structure at the drain side and the source side of the field effect transistor are doped with a type of dopant that is opposite to the type of dopant within the gate structure. Such dopant at the sidewalls of the gate structure forms a respective depletion region from the sidewall into approximately the edge of the drain overlap and source overlap that extends under the gate structure to reduce the parasitic Miller capacitance formed by the drain overlap and the source overlap.

Double sidewall short channel split gate flash memory

Abstract: An electrically programmable read only memory device which has efficiency of electron injection from channel to floating gate is provided. This memory cell includes a control gate and floating gate between source and drain regions. The region under the floating gate has extremely small enhanced mode channel and N region. Therefore, this channel is completely depleted by the program drain voltage. The enhanced mode channel region is precisely defined by the side wall spacer technique. Also, the N drain region is accurately defined by the difference of side wall polysilicon gate and the first spacer.

EEPROM memory cell and method of fabricating the same

Abstract: An object of the present invention is to realize a memory cell including a single polysilicon layer so as to simplify the fabrication process, improve the productivity and lower the fabrication cost of the memory cell. Another object of the present invention is to realize a memory cell with a simple structure as well as to reduce the area of the memory cell so as to attain high integration. Still another object of the present invention is to form a fine memory cell by utilizing DHE (drain channel hot electrons) and GIDL (gate induced drain leakage). An EEPROM memory cell 10 includes a substrate 12 ; a source region 14 and a drain region 16 formed on a surface of the substrate 12 ; a channel region 18 defined on the surface of the substrate 12 between the source region 14 and the drain region 16 ; a gate oxide film 20 formed on the channel region 18 so as to partly overlap with the source region 14 and the drain region 16 ; and a gate 22 including polysilicon formed on the gate oxide film 20.

Field effect transistor with electrically induced drain and source extensions

Abstract: For fabricating a field effect transistor within an active device area of a semiconductor substrate, a gate dielectric is formed on the active device area of the semiconductor substrate, and a gate structure is formed on the gate dielectric with the gate structure being comprised of a first conductive material. A drain spacer comprised of a second conductive material is formed on a first sidewall of the gate structure, and a first liner dielectric is formed between the drain spacer and the first sidewall of the gate structure and between the drain spacer and the semiconductor substrate. A source spacer comprised of the second conductive material is formed on a second sidewall of the gate structure, and a second liner dielectric is formed between the source spacer and the second sidewall of the gate structure and between the source spacer and the semiconductor substrate. Application of at least a drain threshold voltage on the drain spacer with respect to the semiconductor substrate induces charge accumulation in the semiconductor substrate under the first liner dielectric to form a drain extension of the field effect transistor. Similarly, application of at least a source threshold voltage on the source spacer with respect to the semiconductor substrate induces charge accumulation in the semiconductor substrate under the second liner dielectric to form a source extension of the field effect transistor. In this manner, the drain and source extensions of the field effect transistor are electrically induced to have a depth that is shallow regardless of thermal processes used for fabrication of the integrated circuit having the field effect transistor.

Photodetector and method for detecting radiation

Abstract: In a photodetector, a photodiode and a capacitor are coupled between a sensing node and a ground voltage line, and a MOS transistor is coupled between the sensing node and a reference voltage line. Initially, the capacitor is charged so that the sensing node voltage is greater than a transition voltage and a predetermined gate voltage is applied to switch the transistor off. During a sampling time, the capacitor initially discharges through the photodiode, the discharge current being dependent on the intensity of radiation incident on the photodiode, until the sensing node voltage falls to the transition voltage. If the sensing node voltage falls to the transition voltage during the sampling time, the transistor enters its weak inversion operation domain and the current through the photodiode can flow through the transistor such that the sensing node voltage varies logarithmically with the radiation intensity. At the end of the sampling time, a readout circuit coupled to the sensing node generates an output signal dependent on the sensing node voltage, and the photodetector is reset by recharging the capacitor before the start of another sampling time.

Method of forming a transistor having a low-resistance gate electrode

Abstract: A method is disclosed in which a low-resistance portion of the gate electrode of a transistor is formed independently of the formation of low-resistance portions in the drain and source regions. Accordingly, the device features a thick low-resistance portion in the gate electrode, for example, a thick gate silicide for supporting low gate delays by minimizing the gate resistance, and a thin low-resistance portion in the drain and source in order to meet the requirements for shallow junction integration. Moreover, a transistor is disclosed having a low-resistance gate electrode portion, the composition of which is different from the low-resistance portion of the drain and source.

Vertical MOS transistor having body region formed by inclined ion implantation

Abstract: There is provided a vertical MOS transistor in which a high frequency characteristic is improved, a low voltage operation is realized, and a stable characteristic with less fluctuation is obtained. After trench gate oxidation, a body is formed at a side wall by inclined ion implantation, and after formation of a gate electrode, a low concentration source region is formed by inclined ion implantation, so that a capacitance between a gate and a source and a capacitance between a gate and a drain are suppressed. When the above body region formation method is used, an impurity distribution between the drain and the source of a channel region also becomes uniform. Besides, since a channel length is determined by an etching apparatus, by using the same apparatus for trench-etching and for etching of the gate electrode, a stable channel length can be obtained.

Two-dimensional analytical model for drain induced barrier lowering (DIBL) in short channel MOSFETs

Abstract: An analytical model to elucidate various effects of drain induced barrier lowering in a short channel MOSFET's performance is presented. In particular, the amount of drain bias induced depletion charge under the gate is assessed and an expression for the distribution of this charge along the channel length is developed. Then, based on a simplified two-dimensional solution of Poisson's equation along the channel, the potential barrier lowering between source and channel, and consequently threshold voltage shift is estimated. The results are compared with numerical simulation data for deep submicron NMOS devices. Finally, the dependence of threshold voltage on drain bias for LDD and non-LDD MOSFETs with effective channel lengths down to deep submicron range has been investigated. Due to its simplicity, the developed model is suitable for circuit simulators.

Method of operating flash memory

Abstract: A method of programming an electrically programmable memory cell which cell includes a transistor formed in a semiconductor substrate of first conductivity type having a surface a first well region of second conductivity type is disposed in the substrate adjacent the surface thereof A second well region of first conductivity type is disposed in the first well region adjacent the surface The transistor has a source region, a drain region, a floating gate, and a control gate The method includes raising the control gate to a first selected potential no greater than 90 volts, raising the drain to a potential to no more than 50 volts, coupling the source region to ground potential, coupling the first well region of second conductivity type to ground potential, and placing the second well region at a potential below ground potential

Avalanche injection of hot holes in the gate oxide of LDMOS transistors

Abstract: A new degradation mode of n-channel lateral double-diffused MOS (LDMOS) transistors has been investigated. The degradation, resulting in a large increase of the drain saturation current at the onset of strong inversion, is attributed to avalanche-generated hot holes injected and trapped in the gate oxide above the n-type drift region of LDMOS transistors operating at a high drain voltage and a low gate voltage near threshold. Worst-case static gate-bias condition, drain voltage dependence, maximum operating drain voltage, and the effect of varying some geometrical parameters of the device are studied. A method, based on gate-to-drain capacitance measurements, to characterize the spatial extension of the damaged region and the amount of trapped holes, is presented.

Damascene-gate process for the fabrication of MOSFET devices with minimum poly-gate depletion, silicided source and drain junctions, and low sheet resistance gate-poly

Abstract: A sub-0.1 μm MOSFET device having minimum poly depletion, salicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene-gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.