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Showing papers on "Drain-induced barrier lowering published in 2002"


Patent
30 May 2002
TL;DR: In this article, a high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or multiple dielectric layers.
Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

197 citations


Patent
11 Mar 2002
TL;DR: In this article, a 1T/FB dynamic random access memory (DRAM) cell is provided that includes a field effect transistor fabricated using a process compatible with a standard CMOS process.
Abstract: A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell is provided that includes a field-effect transistor fabricated using a process compatible with a standard CMOS process. The field-effect transistor includes a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region. A buried region of the first conductivity type is located under the source region, drain region and floating body region. The buried region helps to form a depletion region, which is located between the buried region and the source region, the drain region and the floating body region. The floating body region is thereby isolated by the depletion region. A bias voltage can be applied to the buried region, thereby controlling leakage currents in the 1T/FB DRAM cell.

169 citations


Journal ArticleDOI
TL;DR: In this article, the authors proposed a two-dimensional analytical model of a dual material gate MOSFET for reduced drain-induced barrier lowering (DIBL) effect, merging two metal gates of different materials, laterally into one.
Abstract: We propose a new two-dimensional (2-D) analytical model of a dual material gate MOSFET (DMG-MOSFET) for reduced drain-induced barrier lowering (DIBL) effect, merging two metal gates of different materials, laterally into one. The arrangement is such that the work function of the gate metal near the source is higher than the one near the drain. The model so developed predicts a step-function in the potential along the channel, which ensures screening of the drain potential variation by the gate near the drain. The small difference of voltage due to different gate material keeps a uniform electric field along the channel, which in turn improves the carrier transport efficiency. The ratio of two metal gate lengths can be optimized along with the metal work functions and oxide thickness for reducing the hot electron effect. The model is verified by comparison to the simulated results using a 2-D device simulator ATLAS over a wide range of device parameters and bias conditions.

94 citations


Patent
12 Sep 2002
TL;DR: In this article, the authors proposed a method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device, where an oxide layer is sandwiched between underlying and overlying silicon layers.
Abstract: A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprise silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer, to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain. A gate trench is etched through the NMOS and PMOS sources and channel regions. The gate trench terminates at the NMOS and PMOS drains and exposes the sidewalls of the NMOS and PMOS channel regions. A gate oxide layer is formed overlying the NMOS and PMOS channel regions and lining the gate trench. A polysilicon layer is deposited and etched back to form polysilicon sidewalls and to thereby form gates for the closely-spaced, vertical NMOS and PMOS transistor pair.

92 citations


Patent
05 Aug 2002
TL;DR: In this paper, the strong piezoelectric effect, found in group-III nitride materials, was used to circumvent the need to selectively remove Gallium Nitride (GaN) in the fabrication of GaN/AlGaN Heterostructure Field Effect Transistors.
Abstract: The present invention utilizes the strong piezoelectric effect, found in group-III nitride materials to circumvent the need to selectively remove Gallium Nitride (GaN) in the fabrication of GaN/AlGaN Heterostructure Field Effect Transistors. The transistor is comprised of a semi-insulating substrate 300, a buffer layer 302 which is in continual contact with the semi-insulating substrate 300. A GaN active channel 304 is atop the buffer layer 302. An AlGaN barrier 306 in laid on top of, and is in continual contact with, the GaN active channel 304. Thereafter, there is a source contact 308 and a drain contact 310 both in physical contact with the GaN active channel 308. There is a gate 312 upon the AlGaN barrier 306 and between the source contact 308 and a drain contact 310. At least one dielectric stressor 314 is placed upon the AlGaN barrier 306. The dielectric stressors 314 are between the gate 312 and the source 308 and drain 310 contacts.

88 citations


Patent
18 Jun 2002
TL;DR: A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop.
Abstract: A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

86 citations


Journal ArticleDOI
TL;DR: In this article, the effect of the choice of the source and drain contact metal is investigated for both top and bottom-contact device structures, and the results of two-dimensional electrostatic modeling of organic field effect transistors, focusing on the formation of the conductive channel, are reported.
Abstract: Results of two-dimensional electrostatic modeling of organic field-effect transistors, focusing on the formation of the conductive channel, are reported. The effect on channel formation of the choice of the source and drain contact metal is investigated for both top- and bottom-contact device structures. High-work-function metal (e.g., gold) source and drain contacts produce a conducting p-type region near these contacts. In contrast, low-work-function metal source and drain contacts (e.g., magnesium) lead to depleted regions. In the center of the device, between the source and drain contacts, the channel carrier density at a fixed gate bias is determined by the work function of the gate contact material, and is essentially independent of the metal used to form the source and drain contacts. The principal difference between top- and bottom-contact structures is the spatial variation of the charge density in the vicinity of the source and drain contacts. The channel carrier density for a fixed gate bias (a...

85 citations


Patent
05 Feb 2002
TL;DR: In this article, a silicon-on-isolator CMOS integrated circuit device includes a semiconductor substrate, an isolation layer formed over the substrate, a n-type MOS transistor having a gate, a drain region, and a source region forming over the isolation layer.
Abstract: A silicon-on-isolator CMOS integrated circuit device includes a semiconductor substrate, an isolation layer formed over the semiconductor substrate, an n-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer, and a p-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer and contiguous with the n-type MOS transistor, wherein the n-type MOS transistor and the p-type MOS transistor form a silicon controlled rectifier to provide electrostatic discharge protection.

85 citations


Patent
13 Mar 2002
TL;DR: In this paper, the double-gate field effect transistor (DFE transistor) was proposed, where the source, drain and channel regions are isolated from the surrounding part by a trench, forming an island, and gate insulation films are formed on the opposing side faces of the channel region exposed in the trench.
Abstract: A double-gate field-effect transistor includes a substrate, an insulation film formed on the substrate, source, drain and channel regions formed on the insulation film from a semiconductor crystal layer, and two insulated gate electrodes electrically insulated from each other. The gate electrodes are formed opposite each other on the same principal surface as the channel region, with the channel region between the electrodes. The source, drain and channel regions are isolated from the surrounding part by a trench, forming an island. Gate insulation films are formed on the opposing side faces of the channel region exposed in the trench. The island region between the gate electrodes is given a width that is less than the length of the channel region to enhance the short channel effect suppressive property of structure.

83 citations


Patent
Leonard Forbes1
21 Jun 2002
TL;DR: In this article, a write-once-read-only memory cell with charge trapping in the gate insulator is described, and a bitline is coupled to the second source/drain region.
Abstract: Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator. A plug couples the first source/drain region to an array plate. A bitline is coupled to the second source/drain region. The MOSFET can be programmed by operation in a reverse direction trapping charge in the gate insulator adjacent to the first source/drain region such that the programmed MOSFET operates at reduced drain source current when read in a forward direction.

71 citations


Patent
Chandra Mouli1
01 Aug 2002
TL;DR: In this paper, a high energy, high dose implant of boron and phosphorus through the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) structure within the insulation layer underlying the P- and Nwells of the SOI wafer.
Abstract: A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) structure within the insulation layer underlying the p- and n-wells of the SOI wafer. Backend high temperature processing steps induce diffusion of the boron and phosphorus contained in the BPSG into the p- and n-wells, thereby forming a retrograde dopant profile in the wells. The retrograde dopant profile reduces DIBL and also provides recombination centers adjacent the insulator layer and the active layer to thereby reduce floating body effects for the CMOS device.

Proceedings ArticleDOI
K. Kanda1, T. Miyazaki1, Min Kyeong Sik1, H. Kawaguchi1, Takeshi Sakurai1 
25 Sep 2002
TL;DR: In this article, a novel SRAM scheme is proposed that can reduce the active leakage power by two orders of magnitude in the low voltage region of less than 1 V, the VTH, V/sub TH/, is lowered to less than 0.2 V and the leakage power of memory cells becomes a dominant issue.
Abstract: A novel SRAM scheme is proposed that can reduce the active leakage power by two orders of magnitude. In the low voltage region of less than 1 V, the VTH, V/sub TH/, is lowered to less than 0.2 V and the leakage power of memory cells becomes a dominant issue. By dynamically dropping the supply voltage of un-accessed cells row by row, the cell leakage can be reduced exponentially through the drain induced barrier lowering (DIBL) effect. Additionally, to lower the leakage from bit-line through transfer gates of memory cells, un-accessed word lines are applied with a negative voltage together with a reduced swing write technique. The basic advantage is verified by measurement and the effectiveness in future generations is discussed by simulations.

Patent
22 Mar 2002
TL;DR: In this paper, a high voltage lateral semiconductor device for integrated circuits with improved breakdown voltage is proposed, which consists of a semiconductor body, an extended drain region formed in the semiconductor bodies, source and drain pockets, a top gate forming a pn junction with the extended drain regions, an insulating layer on a surface of the semiconducting body and a gate formed on the insulating layers.
Abstract: A high voltage lateral semiconductor device for integrated circuits with improved breakdown voltage The semiconductor device comprising a semiconductor body, an extended drain region formed in the semiconductor body, source and drain pockets, a top gate forming a pn junction with the extended drain region, an insulating layer on a surface of the semiconductor body and a gate formed on the insulating layer In addition, a higher-doped pocket of semiconductor material is formed within the top gate region that has a higher integrated doping than the rest of the top gate region This higher-doped pocket of semiconductor material does not totally deplete during device operation Moreover, the gate controls, by field-effect, a flow of current through a channel formed laterally between the source pocket and a nearest point of the extended drain region

Patent
20 Feb 2002
TL;DR: In this paper, a display device capable of keeping the luminance constant irrespective of temperature change is provided as well as a method of driving the display device, where a current mirror circuit composed of transistors is placed in each pixel.
Abstract: A display device capable of keeping the luminance constant irrespective of temperature change is provided as well as a method of driving the display device. A current mirror circuit composed of transistors is placed in each pixel. A first transistor and a second transistor of the current mirror circuit are connected such that the drain current of the first transistor is kept in proportion to the drain current of the second transistor irrespective of the load resistance value. The drain current of the first transistor is controlled by a driving circuit in accordance with a video signal and the drain current of the second transistor is caused to flow into an OLED, thereby controlling the OLED drive current and the luminance of the OLED.

Patent
Jung-Dal Choi1, Chang-Hyun Lee1
25 Apr 2002
TL;DR: In this article, an operation method of programming, erasing, and reading a silicon-oxide-nitrideoxide-silicon (SONOS) nonvolatile memory device having a tunnel oxide layer thicker than 20 Å is provided.
Abstract: An operation method of programming, erasing, and reading a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory device having a tunnel oxide layer thicker than 20 Å is provided. A program operation of the method is accomplished by applying a program voltage higher than 0 volts and a ground voltage to a gate electrode and a channel region of a selected SONOS cell transistor, respectively. Also, an erasing operation is accomplished by applying a ground voltage and a first erase voltage lower than 0 volts to a bulk region and a gate electrode of a selected SONOS cell transistor, respectively, and by applying a second erasure voltage to either a drain region or a source region of the selected SONOS cell transistor. The second erase voltage is a ground voltage or a positive voltage. In addition, a read operation is accomplished using either a backward read mode or a forward read mode. Thus, it is possible to remarkably improve a bake retention characteristic, which is sensitive to a thickness of the tunnel oxide layer.

Proceedings ArticleDOI
Rafael Rios1, Wei-Kai Shih1, A. Shah1, S. Mudanai1, Paul A. Packan1, T. Sandford1, Kaizad Mistry1 
08 Dec 2002
TL;DR: In this paper, a closed-form expression for the threshold voltage, V/sub t/, of MOSFETs fabricated with halo processes is described, and a doping transformation is employed to obtain equivalent channel dopings, necessary for charge sheet models that do not rely on threshold voltage concept.
Abstract: A closed-form expression for the threshold voltage, V/sub t/, of MOSFETs fabricated with halo processes is described. The proposed approach accurately captures the length dependent V/sub t/ behavior under different drain and body bias conditions and temperature. In addition, the necessity of considering separate V/sub t/ expressions for current and capacitances is discussed. A doping transformation is employed to obtain equivalent channel dopings, necessary for charge-sheet models that do not rely on the threshold voltage concept.

Patent
18 Jul 2002
TL;DR: In this paper, an anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate, where a gate and gate oxide are formed on the channel.
Abstract: An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.

Patent
09 Sep 2002
TL;DR: In this article, a CMOS field effect transistor (FET) is provided with predetermined temperature characteristics, and the relationship between the channel length, gate width, gate-to-source voltage, and drain current is exploited to create an FET that has relatively constant drain current across a relatively wide range of frequencies.
Abstract: A CMOS field effect transistor (FET) is provided with predetermined temperature characteristics. More particularly, the relationship between the channel length, gate width, gate-to-source voltage, and drain current is exploited to create an FET that has relatively constant drain current across a relatively wide range of frequencies. Alternately, the above-mentioned relationship is exploited to create a drain current with a predetermined temperature coefficient across a wide temperature range.

Patent
Akio Toda1, Haruihiko Ono1
09 Dec 2002
TL;DR: In this article, the p-channel MOS field effect transistor is designed so that a length of a source/drain region in the channel direction is not more than 1 micrometer.
Abstract: While using conventional manufacturing processes, it is intended to apply a compressive strain in the channel direction to the p-channel MOS field effect transistor and also apply a tensile strain in the channel direction to the n-channel MOS field effect transistor for increasing both MOS currents. In the MOS semiconductor device isolated by a trench device isolation region, the p-channel MOS field effect transistor is designed so that a length of a source/drain region in the channel direction is not more than 1 micrometer, and the gate length is not more than 0.2 micrometers. The n-channel MOS field effect transistor is designed so that a face of the source/drain region in parallel to the gate width direction is adjacent to the device isolation film with the inserted silicon nitride film, and a face of the source/drain region parallel to the gate length direction is adjacent to the device isolation film comprising the silicon oxide film only.

Journal ArticleDOI
TL;DR: In this paper, a sub-100-nm vertical MOSFET with high pressure oxide growing at source/drain (S/D) regions to reduce the gate overlapped capacitances and threshold voltage adjustment with a doped APCVD film is presented.
Abstract: Sub-100-nm vertical MOSFET has been developed for fabrication with low cost processing. This is the first vertical MOSFET design that combines 1) a vertical L/sub DD/ structure processed with implantation and diffusion steps, 2) high-pressure oxide growing at source/drain (S/D) regions to reduce the gate overlapped capacitances, and 3) threshold voltage adjustment with a doped APCVD film. The drive current per unit channel width and S/D punch-through voltage are higher than that of previously published vertical MOSFETs. Fabrication processes are well established, and equipment of the 1 /spl mu/m CMOS generation can be used to fabricate sub-100-nm channel length MOSFETs with good electrical characteristics and high performance.

Patent
19 Apr 2002
TL;DR: In this paper, a floating P-type blocking region is provided to protect an N-channel LDMOS field effect transistor from inadvertent reversal of polarity of voltage applied across the device.
Abstract: An LDMOS field effect transistor (80) provides protection against the inadvertent reversal of polarity of voltage applied across the device. To protect an N-channel device, a floating P-type blocking region (82) is provided surrounding the drain region (32). The blocking region (82) is spaced apart from a body region (28) that forms the diffused channel (34) of the transistor (80). A first gate electrode (36) controls the conductivity of the diffused channel (34) and a second gate electrode (84) controls the conductivity of the surface (35) of the blocking region (82).

Patent
01 Oct 2002
TL;DR: The asymmetric channel region can include silicon abutting the source region and a heterostructure material such as Si1-xGex extending to and abutding the drain region.
Abstract: A MOSFET semiconductor device having an asymmetric channel region between the source region and the drain region. In one embodiment, the device comprises a mesa structure on a silicon substrate with the source region being in the substrate and the mesa structure extending from the source region and substrate. The asymmetric channel region can include silicon abutting the source region and a heterostructure material such as Si1-xGex extending to and abutting the drain region. The mole fraction of Ge can increase towards the drain region either uniformly or in steps. In one embodiment, the doping profile of the channel region is non-uniform with higher doping near the source region and lower doping near the drain region.

Patent
16 Aug 2002
TL;DR: In this paper, an integrated circuit fabricated in a single silicon substrate includes a high-voltage output transistor having source and drain regions separated by a channel region, and a gate disposed over the channel region.
Abstract: An integrated circuit fabricated in a single silicon substrate includes a high-voltage output transistor having source and drain regions separated by a channel region, and a gate disposed over the channel region. Also included is an offline transistor having source and drain regions separated by a channel region and a gate disposed over the channel region of the offline transistor. A drain electrode is commonly coupled to the drain region of the high-voltage output transistor and to the drain region of the offline transistor.

Journal ArticleDOI
TL;DR: In this paper, a sub-threshold surface potential model for pocket n-MOSFETs is proposed based on solutions of the quasi-two-dimensional Poisson's equation, which satisfy rigorously the boundary conditions of continuity of potential and electric field in the lateral direction along the surface of pocket devices.
Abstract: A correct and improved analytical subthreshold surface potential model for pocket n-MOSFETs is proposed. The model is based on solutions of the quasi-two-dimensional (quasi-2-D) Poisson's equation, which satisfy rigorously the boundary conditions of continuity of potential and electric field in the lateral direction along the surface of pocket devices. The closed-form model equations without any fitting empirical formulas efficiently and correctly generate surface potential profiles between the source and drain of deep-submicrometer as well as long-channel pocket n-MOSFETs. Drain-induced barrier lowering (DIBL) effect of deep-submicrometer pocket n-MOSFETs is also predicted by the potential model. The subthreshold surface potential model is applied to off-state current and threshold voltage of deep-submicrometer or sub-100-nm pocket n-MOSFETs.

Patent
24 Sep 2002
TL;DR: In this paper, a charge pump includes at least one switching transistor for switching current on or off in response to an up or down signal, a pair of transistors (one coupled to the source and the other to the drain of the switching transistor) each having its source and drain shorted and coupled to receive a complement of the signal on the gate terminal of the switch transistor on their gate terminals, and a fourth transistor coupled to a power supply.
Abstract: A charge pump includes at least one switching transistor for switching current on or off in response to an up or down signal, a pair of transistors (one coupled to the source and the other to the drain of the switching transistor) each having its source and drain shorted and coupled to receive a complement of the signal on the gate terminal of the switching transistor on their gate terminals, and a fourth transistor coupled to the drain of the switching transistor and a power supply. The pair of transistors are activated concurrent with the deactivation of the switching transistor. The fourth transistor may provide for active shutoff of a current transistor being switched by the switching transistor, by actively charging the source of the current transistor to a voltage which is not exceeded by the gate terminal of the current transistor.

Patent
06 Nov 2002
TL;DR: In this paper, an erasing method for the memory cells of a nonvolatile memory is provided, where each memory cell comprises a gate, a source, a drain, an electron-trapping layer and a substrate.
Abstract: An erasing method for the memory cells of a non-volatile memory is provided. Each memory cell comprises a gate, a source, a drain, an electron-trapping layer and a substrate. The data within the memory cell is erased by applying a first voltage to the control gate, applying a second voltage to the source, applying a third voltage to the drain and applying a fourth voltage to the substrate. The electrons are pulled from the electron-trapping layer into the channel by negative gate F-N tunneling effect.

Patent
Kiyohiko Sakakibara1
13 Mar 2002
TL;DR: In this paper, a transistor including first and second diffused layers of a second conductance, opposite to each other through a channel region, and a two-storied gate electrode on the channel region of the first conductance type, is set at a first voltage level.
Abstract: In a transistor including first and second diffused layers of a second conductance, opposite to each other through a channel region of a first conductance type, and a two-storied gate electrode on the channel region of the first conductance type, a channel region and one of the diffused layers are set at a first voltage level; the other thereof is set at a second voltage level; a control gate is set at the first or a third voltage level; a difference between the first and second voltage levels is set larger in absolute value than that between the first and third voltage levels; and a part of charges flowing in the channel region with respect to the transistor flowing a channel current is injected into the floating gate. This solves difficulties of large driving currents at write back, a long write back time, deterioration of channel conductance, and the like.

Patent
22 Jul 2002
TL;DR: In this paper, a semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film is presented.
Abstract: A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuit 20 is provided between logic circuit 10 and source voltage Vdd supply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MP0 of switching circuit 20, and bias voltage VB equal to or slightly lower than source voltage Vdd is applied to its channel region in order to reduce the threshold voltage of transistor MP0 and increase its current driving capability. While in a standby status, a voltage equal to source voltage Vdd is applied to the gate of transistor MP0, a voltage lower than the source voltage is applied to the source, and bulk bias voltage VB equal to or higher than source voltage Vdd is applied to the channel region in order to minimize the drain current of transistor MP0, so that current path of logic circuit 10 is cut off, and the occurrence of leakage current is suppressed.

Journal ArticleDOI
TL;DR: In this article, a single-step ion implantation was used to form the asymmetric graded doping profile in the channel of vertical sub-100nm nMOSFETs.
Abstract: Graded doping profile in the channel of vertical sub-100-nm nMOSFETs was investigated in this study. Conventional single-step ion implantation was used to form the asymmetric graded doping profile in the channel. No large-angle-tilt implant is needed. The device processing is compatible with conventional CMOS technology. In a graded-channel-doping device, with the higher doping near the source, drain induced barrier lowering (DIBL) and the off-state leakage current are reduced significantly. The graded doped channel also has a lower longitudinal electric field near the drain. Therefore, hot-carrier related reliability is improved substantially with this type of device structure.

Patent
Wen-Tai Wang1, Chung-Hui Chen1
30 Sep 2002
TL;DR: In this article, a new level-shifting circuit consisting of a first cascaded switch comprising a first NMOS transistor and a first zero threshold NMOS transistors is achieved.
Abstract: A new level-shifting circuit is achieved comprising: a first cascaded switch comprising a first NMOS transistor and a first zero threshold NMOS transistor, the second cascaded switch comprises a second NMOS transistor and a second zero threshold NMOS transistor, and the cross-coupled pull-up comprises a first PMOS transistor and a second PMOS transistor. The sources of both of these PMOS transistors are coupled to a high voltage supply. The gate of the second PMOS transistor and the drain of the first PMOS transistor are coupled to the drain of the first zero threshold NMOS transistor to form an inverted output. The gate of the first PMOS transistor and the drain of the second PMOS transistor are coupled to the drain of the second zero threshold NMOS transistor to form a non-inverted output.