Showing papers on "Drain-induced barrier lowering published in 2003"

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Abstract: High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs

Abstract: A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.

Low leakage heterojunction vertical transistors and high performance devices thereof

Abstract: A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.

Drain voltage scaling in carbon nanotube transistors

Abstract: Decreasing the oxide thickness in carbon nanotube field-effect transistors (CNFETs) improves the turn-on behavior. However, we demonstrate that this also requires scaling the range of the drain voltage. This scaling is needed to avoid an exponential increase in off-current with drain voltage, due to modulation of the Schottky barriers at both the source and drain contact. We illustrate this with results for bottom-gated ambipolar CNFETs with oxides of 2 and 5 nm, and give an explicit scaling rule for the drain voltage. Above the drain voltage limit, the off-current becomes large and has equal electron and hole contributions. This allows the recently reported light emission from appropriately biased CNFETs.

Active-matrix display device and method of driving the same

Abstract: In an active-matrix display device and a method for driving the active-matrix display device, a fifth transistor is connected between a power line and a drain terminal of a first transistor so that a power-supply voltage, namely the fixed voltage required for the compensation of the threshold voltage, is supplied by the power line via a fifth transistor and not by a signal line Thus, a sufficient length of time for the threshold voltage compensation period can be maintained, and a second transistor of each pixel can accurately be compensated for threshold voltage irregularities

Semiconductor nano-rod devices

Abstract: In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region to form a nano-rod structure. Part of the nano-rod structure is then used as a gate channel. Preferably, a gate dielectric and a gate electrode both wrap around the nano-rod structure, with the gate dielectric being between the nano-rod structure and the gate electrode, to form a transistor device.

Field effect transistor memory cell, memory device and method for manufacturing a field effect transistor memory cell

Abstract: A field effect transistor memory cell has a source region, a drain region, a channel region and a gate region, with the channel region extending from the source region to the drain region and being formed from at least one nanowire which has at least one defect such that charges can be trapped in the defects and released from the defects by a voltage applied to the gate region. A memory device built up from such memory cells and a method of manufacturing such memory cells is also disclosed.

Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers

Abstract: Nano scale body-tied FinFETs have been firstly fabricated. They have fin top width of 30 nm, fin bottom width of 61 nm, fin height of 99 nm, and gate length of 60 nm. This Omega MOSFET shows excellent transistor characteristics, such as very low subthreshold swing, Drain Induced Barrier Lowering (DIBL) of 24 mV/V, almost no body bias effect, and orders of magnitude lower I/sub SUB//I/sub D/ than planar type DRAM cell transistors.

Insulated gate field effect transistor having passivated schottky barriers to the channel

Abstract: A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω-μm 2 . The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface. Also, the interface layer may include a separation layer of a material different than the passivating material. Where used, the separation layer has a thickness sufficient to reduce effects of metal-induced gap states in the semiconductor channel.

A study of the threshold voltage in pentacene organic field-effect transistors

Abstract: The threshold voltage and carrier mobilities were characterized in pentacene-based organic field-effect transistors with gold top-contact electrodes for different thickness of the pentacene film. The thickness of the semiconductor layer influences the values of the threshold voltage and, to a lesser extent, the saturation current. In this letter, we show that the thickness-dependent part of the threshold voltage results from the presence of an injection barrier at the gold–pentacene contact. We also show how the ratio between the gate insulator thickness and the semiconductor layer thickness alter the value for the saturation current, and therefore produces values for the field-effect mobility that are too low.

Improved independent gate N-type FinFET fabrication and characterization

Abstract: N-type independent gate FinFETs (IGFinFETs) have been fabricated and characterized. Previous published results for this structure highlighted processing deficiencies. Several process enhancements have improved device results beyond those previously reported. These process improvements are presented, and the resulting device is demonstrated. Device results for 2 micron channel length devices are shown. Six decades of drain current suppression and low gate leakage currents are achieved. Subthreshold slope of 200 mV/dec and a threshold voltage tuning range of 1.7 V are demonstrated. This device combines the behavioral characteristics of independent-double-gate MOSFETs with the processing advantages and integration of FinFETs.

Method of fabricating a one transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region

Abstract: A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell is provided that includes a field-effect transistor fabricated using a process compatible with a standard CMOS process. The field-effect transistor includes a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region. A buried region of the first conductivity type is located under the source region, drain region and floating body region. The buried region helps to form a depletion region, which is located between the buried region and the source region, the drain region and the floating body region. The floating body region is thereby isolated by the depletion region. A bias voltage can be applied to the buried region, thereby controlling leakage currents in the 1T/FB DRAM cell.

Electrostatic engineering of nanotube transistors for improved performance

Abstract: With decreasing device dimensions, the performance of carbon nanotube field-effect transistors (CNFETs) is limited by high OFF currents except at low drain voltages. Introducing an asymmetry between source and drain electrostatics can improve the performance, reducing OFF currents and extending the usable range of drain voltage. The improvement is most dramatic for ambipolar Schottky-barrier CNFETs. Moreover, this approach allows a single device to exhibit equally good performance as an n- or p-type transistor, by changing only the sign of the drain voltage. Even for CNFETs having ohmic contacts, an asymmetric design can greatly improve the performance for small-bandgap nanotubes.

Threshold voltage adjustment for long-channel transistors

Abstract: A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at least a part of the channel region with a gate formed over the gate oxide. The gate further includes at least one implant aperture formed therein with the channel region of the substrate further including an implanted region within the channel between the source and drain regions. Methods for forming the threshold voltage adjusted transistor are also disclosed.

Write operation for capacitorless RAM

Abstract: A method for writing data to single-transistor capacitorless (1T/0C) RAM cell, wherein the cell structure is predicated on an SOI MOS transistor that has a floating body region (12). Data is written to the cell by the instigation of band-to-band tunneling (BTBT) and the resulting generation of hole/electron pairs. Electrons are drawn from the body region through forward-biased drain (14) and source (15) regions so that holes accumulate in the body region. The increase in threshold voltage, caused by the accumulation of holes, may be defined and detected as a logic level (ONE, for example). In one embodiment, a split biasing scheme applies substantially identical voltages to the drain and to the source and a negative bias to the gate. In alternative embodiments, a negative gate bias is not required and the drain and source bias voltages may be offset so as to mitigate source damage.

Metal oxide semiconductor transistors having a drain punch through blocking region and methods for fabricating metal oxide semiconductor transistors having a drain punch through blocking region

Abstract: Metal oxide semiconductor transistors and devices with such transistors and methods of fabricating such transistors and devices are provided. Such transistors may have a silicon well region having a first surface and having spaced apart source and drain regions therein. A gate insulator is provided on the first surface of the silicon well region and disposed between the source and drain regions and a gate electrode is provided on the gate insulator. A region of insulating material is disposed between a first surface of the drain region and the silicon well region. The region of insulating material extends toward but not to the source region. A source electrode is provided that contacts the source region. A drain electrode contacts the drain region and the region of insulating material.

Semiconductor wafer with well contacts on back side

Abstract: A supporting structure is wafer-bonded to the upper face side of a partially or fully processed device wafer. The device wafer includes a transistor having a well region that extends into the substrate material of the device wafer. The source and drain regions of the transistor extend into the well region. After attachment of the supporting structure, the device wafer is thinned from the back side until the bottom of the well region is reached. To reduce source and drain junction capacitances, etching can continue until the source and drain regions are reached. In one embodiment, all of the well-to-substrate junction is removed in a subsequent etching step, thereby reducing or eliminating the well-to-substrate junction capacitance of the resulting transistor. Resistance between the well electrode and the transistor channel is reduced because the well contact is disposed on the back side of the device wafer directly under the gate of the transistor.

Low dropout voltage regulator using a depletion pass transistor

Abstract: A linear low dropout voltage regulator is described that makes use of a depletion mode NMOS pass transistor and of a PMOS transistor in series to the NMOS transistor and connected to its drain. The depletion NMOS transistor assures low dropout operations, while the series PMOS transistor allows the current regulation even under the condition of shorted load. The same PMOS transistor may be used to disable the current in the load without generating a negative voltage at the gate of the depletion pass transistor. This regulator is inherently stable without the need for an output capacitor in parallel to the load.

Performance advantage of Schottky source/drain in ultrathin-body silicon-on-insulator and dual-gate CMOS

Abstract: Here, for the first time, advanced simulation models are used to investigate the performance advantage of Schottky source/drain ultrathin-silicon technologies at a 25-nm gate length target. Schottky and doped source/drain MOSFETs were optimized and compared using a novel benchmark. Mixed-mode simulations of optimized devices in a two-stage NAND chain show an approximate 45% speed advantage of Schottky source/drain for one set of parameter choices. Contact requirements for Schottky source/drain, and for doped source/drain relative to ITRS targets through 2016, are discussed.

Double-gated transistor circuit

Abstract: An OR gate circuit includes double-gated four terminal transistor with independent gate control. First and second inputs are independently coupled to the top and bottom gates of the transistor. The drain is coupled to an output and precharged to a low voltage. An input to either the top or bottom gates results in a high voltage to the drain and an output value of 1.

Nonvolatile memory and method of making same

Abstract: A method of discharging a charge storage location of a transistor of a non-volatile memory includes applying first and second voltages to a control gate and a well region, respectively, of the transistor. The first voltage is applied to the control gate of the transistor, wherein the control gate has at least a portion located adjacent to a select gate of the transistor. The transistor includes a charge storage location having nanoclusters disposed within dielectric material of a structure of the transistor located below the control gate. Lastly, a second voltage is applied to the well region located below the control gate. Applying the first voltage and the second voltage generates a voltage differential across the structure for discharging electrons from the nanoclusters of the charge storage location.

Characteristics of erbium-silicided n-type Schottky barrier tunnel transistors

Abstract: The current–voltage characteristics of erbium-silicided n-type Schottky barrier tunnel transistors (SBTTs) are discussed. The n-type SBTTs with 60 nm gate lengths shows typical transistor behaviors in drain current to drain voltage characteristics. The drain current on/off ratio is about 105 at low drain voltage regime in drain current to gate voltage characteristics. However, the on/off ratio tends to decrease as the drain voltage increases. From the numerical simulation results, the increase of off-current is mainly attributed to the thermionic current and the increase of drain current is mainly attributed to the tunneling current, respectively. This phenomenon is explained by using drain induced Schottky barrier thickness thinning effect.

Method for manufacturing a multi-bit memory cell

Abstract: A memory layer intended for trapping charge carriers over a source region and a drain region is interrupted over the channel so that a diffusion of the charge carriers, which are trapped over the source region and over the drain region, is prevented. The memory layer is limited to regions over the parts of the source region and of the drain region facing the channel and is embedded all around in oxide.

Triple-well charge pump stage with no threshold voltage back-bias effect

Abstract: A charge pump stage includes a first n-channel transistor having a source coupled to an input terminal and a drain coupled to an output terminal. A second n-channel transistor has a source coupled to the input terminal, a drain coupled to a gate of the first transistor, and a gate coupled to the output terminal. A third n-channel transistor has a source coupled to the input terminal, a gate coupled to the output terminal, and a drain coupled to a p-well. A fourth n-channel transistor has a source coupled to the output terminal, a gate coupled to the input terminal, and a drain coupled to the p-well. The first, second, third and fourth transistors are fabricated in the p-well, which is surrounded by an n-well. A first capacitor is coupled to the output terminal, and a second capacitor is coupled to the gate of the first transistor.

Technology for nanoperiodic doping of a metal–oxide–semiconductor field-effect transistor channel using a self-forming wave-ordered structure

Abstract: A self-forming nanostructure—a wave-ordered structure with a controllable period (20–180 nm)—results from the off-normal bombardment of amorphous silicon layers by low-energy (~ 1–10 keV) nitrogen ions. The nanostructure has been modified by reactive-ion etching in plasma to form a periodic nanomask on the surface of the channel region of a metal–oxide–semiconductor field-effect transistor (MOSFET). Implantation of arsenic ions through the nanomask followed by the technological steps completing the fabrication of the MOSFET resulted in a periodically doped channel field-effect transistor (PDCFET), which can be considered as a chain of short-channel MOSFETs with a common gate. Having worse subthreshold characteristics, PDCFETs show greater drain current and transconductance than to MOSFETs without a periodically doped channel. This improvement in device performance is attributed to the fact that the channel length is cut by the length of high-conductivity doped areas in the channel and that the voltage is distributed between the areas, depressing the scaling rules for short-channel MOSFETs and allowing the channel to be less doped between the areas, thus keeping drift mobility high.

High voltage shunt regulator for flash memory

Abstract: A high shunt regulator provides precise voltage over process, temperature, power supply, and foundries The HV level is settable by a digital control bits such as fuse bits A filter network filters out the ripple noise and charge transient A tracking capacitor divider network speeds up response time A fractional band gap reference provides fractional bandgap voltage and current, and operates at low power supply and has superior power supply rejection It is unsusceptible to substrate hot carrier effect It exposes very little to drain induced barrier lowering effect The bandgap core has better than conventional transient response and stability One embodiment has adjustable level control Complementary TC (temperature coefficient) trimming allows efficient realization of zero temperature coefficients of current and voltage Higher order curvature correction of voltage and current is integrated Replica bias for the control loop is presented A Binary and Approximation Complementary TC search trimming is described A zero TC fractional voltage less than the theoretical bandgap voltage (<<˜12 Volt) is realizable The bandgap core has a filtering mechanism to reject high frequency noise A low power startup circuit powers up the bandgap The bandgap also has variable impedance

Charge pump circuit without body effects

Abstract: A charge pump circuit has input and output nodes, a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. A drain of the first transistor and a drain of the second transistor are connected to the input node. A source of the second transistor and a drain of the third transistor are connected to the output node. The first capacitor is connected to a gate of the second transistor. The third transistor is connected to a substrate and a source of the second transistor. When the first transistor is turned on, a voltage at the input node will charge the first capacitor. When the second transistor is turned on, the third transistor is turned on simultaneously so that the substrate and the source of the second transistor will reach the same voltage level. Then, voltage at the input node will charge the second capacitor.

Simulation of Schottky barrier tunnel transistor using simple boundary condition

Abstract: The current–voltage characteristics of a Schottky barrier tunnel transistor (SBTT) are simulated by considering the internal voltage drop at the Schottky barrier and using the current continuity condition between the tunneling and channel current. The numerical results show typical behaviors as can be found in many experimental results. From these results, a significantly higher threshold voltage is expected for the SBTT compared to the conventional metal–oxide–semiconductor field-effect transistors, because of the suppression of the tunneling current at low gate voltage. For the nanometer-size device application, a metal gate should be used to decrease the threshold voltage.

Method of manufacturing a transistor

Abstract: A technique for reducing an on-resistance of a transistor is provided. A power MOSFET of the present invention has a semiconductor material which is disposed under a polysilicon gate and composed of polysilicon into which impurities are doped at low concentration. Therefore, a depletion layer is expanded to the inside of the semiconductor material under the polysilicon gate. Since the electric field strengths are uniform from the surface of a drain layer to a depth of the bottom surface of the semiconductor material and a high electric field is not generated at one site, the avalanche breakdown voltage of the transistor is increased. Therefore, the concentration of impurities in drain layer can be made higher than that in a conventional transistor and thereby the on-resistance of the transistor 1 can be reduced.