Showing papers on "Drain-induced barrier lowering published in 2004"

Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

Abstract: This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs

Abstract: A two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide and also the silicon thin film. We demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended to find an expression for the threshold voltage in the submicrometer regime, which predicts a desirable "rollup" in the threshold voltage with decreasing channel lengths. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations.

Extracting Parameters from the Current–Voltage Characteristics of Organic Field‐Effect Transistors

Abstract: Organic field-effect transistors were fabricated with vapor-deposited pentacene on aluminum oxide insulating layers. Several methods are used in order to extract the mobility and threshold voltage from the transfer characteristic of the devices. In all cases, the mobility is found to depend on the gate voltage. The first method consists of deriving the drain current as a function of gate voltage (transconductance), leading to the so-called field-effect mobility. In the second method, we assume a power-law dependence of the mobility with gate voltage together with a constant contact resistance. The third method is the so-called transfer line method, in which several devices with various channel length are used. It is shown that the mobility is significantly enhanced by modifying the aluminum oxide layer with carboxylic acid self-assembled monolayers prior to pentacene deposition. The methods used to extract parameters yield threshold voltages with an absolute value of less than 2 V. It is also shown that there is a shift of the threshold voltage after modification of the aluminum oxide layer. These features seem to confirm the validity of the parameter-extraction methods.

Non-volatile electromechanical field effect devices and circuits using same and methods of forming same

Abstract: Non-volatile field effect devices and circuits using same. A non-volatile field effect transistor utilizes a nanatube-based mechanical switch (30). The switch location can be at the source, drain or gate locations of the field effect transistor. Under one embodiment, the field effect device includes a source region and a drain region with a channel region (27) disposed therebetween. The source region is connected to a corresponding terminal (T2). A gate structure is disposed over the channel region and connected to a corresponding terminal (T1). A nanotube switching element (30) is responsive to a first control terminal (T3) and a second control terminal (T4) and is electrically positioned in series between the drain region and a terminal corresponding to the drain region. The nanotube switching element is electromechanically operable to one of an open and closed state to thereby open or close an electrical communication path between the drain region and its corresponding terminal.

Vertical NROM having a storage density of 1 bit per 1F2

Abstract: Structures and methods for vertical memory cell. The vertical memory cell includes a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate. The MOSFET has a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator. A first transmission line is coupled to the first source/drain region. A second transmission line is coupled to the second source/drain region. The MOSFET is adapted to be programmed to have a charge trapped in at least one of a first storage region and a second storage region in the gate insulator and operated with either the first source/drain region or the second source/drain region serving as the source region.

Metal gate transistors with epitaxial source and drain regions

Abstract: An MOS transistor formed on a heavily doped substrate is described. Metal gates are used in low temperature processing to prevent doping from the substrate from diffusing into the channel region of the transistor.

Method of fabricating a field effect transistor structure with abrupt source/drain junctions

Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

Circuit and method for programming charge storage memory cells

Abstract: A circuit and method for self-converging programming of a charge storage memory cell, such as NROM or floating gate flash, having a source and a drain in a substrate, a charge storage element and a control gate. The method includes applying source voltage, inducing a body effect that increases the effective threshold, and increasing the source voltage along with the drain voltage to moderate hot electron injection efficiency during the program operation, at least during a portion of the program operation in which convergence on a target threshold occurs. A selected gate voltage is applied during the operation to establish the target threshold voltage. In multiple bit cells, the gate voltage is set according to the data values to be stored, enabling self-convergence at more than one target threshold.

Programming methods for multi-level flash EEPROMs

Abstract: A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected constant drain-to-source bias voltage and a selected gate voltage.

Partially depleted SOI MOSFETs under uniaxial tensile strain

Abstract: The effects of tensile uniaxial strain on the DC performance of partially-depleted silicon-on-insulator n and p-channel MOSFETs as a function of orientation and gate length are reported. The drain current of the n-MOSFETs increases for both longitudinal and transverse strain orientations with respect to the current flow direction. In the n-MOSFET, longitudinal strain provides greater enhancement than transverse strain. In contrast, for p-MOSFETs, longitudinal strain decreases the current while transverse strain increases the drain current. The magnitude of the fractional change in drain current decreases as gate length is reduced from 20 to 0.35 /spl mu/m. These phenomena are consistent with those of bulk silicon MOSFETs and are shown to be qualitatively correlated with the piezoresistance coefficients of the Si inversion layer. Analysis of the linear drain current versus gate voltage characteristics shows that the threshold voltage is independent of strain while the change in drain current tracks with the change in effective electron and hole mobility. Closer examination shows that as the gate length is reduced from 20 to 0.35 /spl mu/m, the relative increase in low-field electron and hole mobility is constant for transverse strain and generally decreases with gate length for longitudinal strain.

High voltage ESD protection circuit with low voltage transistors

Abstract: An ESD protection circuit includes a stacked NMOS transistor pair coupled between a pad and a negative voltage supply, with a first transistor's drain connected to the pad and a second transistor's source connected to the negative power supply. A first voltage divider provides reduced voltage from a high voltage positive power supply to a gate of the first transistor, a first diode string coupled between the gates of the first and second transistors, a second diode string with its anode coupled to the pad, an inverter with a source of its PMOS transistor coupled to a cathode of the second diode string and with its NMOS transistor coupled to the negative power supply, an output node of the inverter coupled to a gate of the second transistor, and a RC circuit coupled to an input node of the inverter, for dissipation of ESD current.

A novel multi-channel field effect transistor (McFET) on bulk Si for high performance sub-80nm application

Abstract: We demonstrate highly manufacturable double FinFET on bulk Si wafer, named multi-channel field effect transistor (McFET) for the high performance 80nm 144M SRAM. Twin fins are formed for each transistor using our newly developed simple process scheme. McFET with L/sub G/=80nm shows several excellent transistor characteristics, such as /spl sim/5 times higher drive current than planar MOSFET, ideal subthreshold swing of 60mV/dec, drain induced barrier lowering (DIBL) of 15mV/V without pocket implantation, and negligible body bias dependency, maintaining the same source/drain resistance as planar transistor due to the unique feature of McFET.

Improved off-current and subthreshold slope in aggressively scaled poly-Si TFTs with a single grain boundary in the channel

Abstract: A polycrystalline-silicon thin-film transistor (TFT), with a single grain boundary (GB) present in the channel, is simulated using two-dimensional numerical simulation, which includes a model of deep trap states at GBs. It is observed that the potential barrier resulting from a GB in the channel acts to suppress current flowing through the channel when the barrier height is greater than the thermal voltage. The conduction mechanism in the subthreshold regime is clarified. The turn-on characteristics of the device are controlled primarily by gate-induced grain barrier lowering as opposed to modulation of carriers in the channel by the gate voltage. In the negative bias region it is found that suppression of the off current is aided by the GB potential barrier. Scaling of the various geometrical parameters of the device are investigated. Improved subthreshold characteristics, compared to an equivalent silicon-on-insulator (SOI) structure, are found for aggressively scaled devices, due to the presence of a GB in the channel.

NOR flash memory cell with high storage density

Abstract: Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A sourceline is formed in a trench adjacent to the vertical floating gate transistor and coupled to the first source/drain region. A transmission line coupled to the second source/drain region. And, a wordline is coupled to the control gate perpendicular to the sourceline.

Isolated high-voltage LDMOS transistor having a split well structure

Abstract: The isolated high-voltage LDMOS transistor according to the present invention includes a split N-well and P-well in the extended drain region. The P-well is split in the extended drain region of the N-well to form a split junction-field in the N-well. The split N-well and P-well deplete the drift region, which shifts the electric field maximum into the bulk of the N-well. This achieves a higher breakdown voltage and allows the N-well to have a higher doping density. Furthermore, the LDMOS transistor according to the present invention includes a N-well embedded beneath the source diffusion region. This creates a low-impedance path for the source region, which restricts the transistor current flow between the drain region and the source region.

Apparatus and manufacturing process of carbon nanotube gate field effect transistor

Abstract: The present invention generally relates to an apparatus and method of carbon nanotube (CNT) gate field effect transistor (FET), which is used to replace the current metal gate of transistor for decreasing the gate width greatly. The carbon nanotube has its own intrinsic characters of metal and semiconductor, so it can be the channel, connector or next-level gate of transistor. Furthermore, the transistor has the structure of exchangeable source and drain, and can be defined the specificity by outside wiring.

Doubly asymmetric double gate transistor structure

Abstract: The present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping one of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. Additionally, the preferred transistor design uses an asymmetric structure that results in reduced gate-to-drain and gate-to-source capacitance. In particular, dimensions of the weak gate, the gate that has a workfunction less attractive to the channel carriers, are reduced such that the weak gate does not overlap the source/drain regions of the transistor. In contrast the strong gate, the gate having a workfunction that causes the inversion layer to form adjacent to it, is formed to slightly overlap the source/drain regions. This asymmetric structure allows for the performance benefits of a double gate design without the increased capacitance that would normally result.

High voltage double diffused drain MOS transistor with medium operation voltage

Abstract: A method of fabricating a high voltage MOS transistor with a medium operation voltage on a semiconductor wafer. The transistor has a double diffused drain (DDD) and a medium operation voltage such as 6 to 10 volts, which is advantageous for applications having both low and higher operation transistor devices. The second diffusion region of the DDD is self-aligned to the spacer on the sidewalls of the gate and gate dielectric, so that the transistor size may be decreased.

Multiple-gate MOS transistor and a method of manufacturing the same

Abstract: Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability.

Transistor structure with a curved channel, memory cell and memory cell array for DRAMs, and methods for fabricating a DRAM

Abstract: A transistor structure having source/drain regions arranged in a horizontal plane along an x axis has a recess structure, which separates the two source/drain regions from one another and increases the effective channel length L eff of the transistor structure. A vertical gate electrode with respect to the horizontal plane extends along the x axis and in this case encloses an active zone of the transistor structure from two sides or completely. The effective channel width W eff is dependent on the depth to which the gate electrode is formed. A memory cell having a selection transistor in accordance with the transistor structure has both a low leakage current and a good switching behavior. By a suitable integration concept, the transistor structure is integrated into a memory cell array of a DRAM having hole trench capacitors or stacked capacitors.

Multiple-gate device with floating back gate

Abstract: Disclosed is a multiple-gate transistor that includes a channel region and source and drain regions at ends of the channel region. A gate oxide is positioned between a logic gate and the channel region and a first insulator is formed between a floating gate and the channel region. The first insulator is thicker than the gate oxide. The floating gate is electrically insulated from other structures. Also, a second insulator is positioned between a programming gate and the floating gate. Voltage in the logic gate causes the transistor to switch on and off, while stored charge in the floating gate adjusts the threshold voltage of the transistor. The transistor can comprise a fin-type field effect transistor (FinFET), where the channel region comprises the middle portion of a fin structure and the source and drain regions comprise end portions of the fin structure.

Transistor circuit, pixel circuit, display device, and driving method therefor

Abstract: There is provided a transistor circuit having a function to correct fluctuation of a threshold voltage of a thin film transistor. The transistor circuit includes a plurality of thin film transistors (Tr1 to Tr3) formed on a substrate and a wire connecting a transistor gate, source, or drain in such a manner that a predetermined operation can be obtained. During an operation, a forward bias is applied repetitively or continuously to the wire between the gate and the source of the thin film transistor (Tr2). At a timing not disturbing the operation, backward bias is applied to the wire between the gate and the source of the transistor (Tr2) so as to suppress fluctuation of the threshold voltage. More specifically, an additional transistor (Tr3) connected in parallel to the transistor (Tr2) is driven for compensation so as to create the aforementioned timing not disturbing the operation and apply a backward bias to the transistor (Tr2) at the timing created.

Dual-gate field effect transistor

Abstract: A dual-gate field effect transistor includes two gate insulation films (6-1, 6-2) sandwiching a vertical channel (5) standing on a substrate (1) and arranged between a source (7-1) and a drain (7-2), from a direction orthogonal to the carrier running direction of the vertical channel; and two gate electrodes (3-1, 3-2) respectively facing the vertical channel (5) via the gate insulation films (6-1, 6-2) The gate insulation films (6-1, 6-2) have different thickness values t1,t2 It is also possible that the gate insulation films (6-1, 6-2) have different dielectric constants e1, e2, or the gate electrodes (3-1, 3-2) have different work functions Φ1, Φ2 Thus, it is possible to set the threshold value voltage of the dual-gate field effect transistor to a desired value when manufacturing the transistor Furthermore, it is possible to prevent the problem of increase of the sub-threshold coefficient which occurs in the conventional technique

High voltage ldmos transistor having an isolated structure

Abstract: A high voltage LDMOS transistor according to the present invention includes a P-field and divided P-fields in an extended drain region of a N-well. The P-field and divided P-fields form junction-fields in the N-well, in which a drift region is fully depleted before breakdown occurs. Therefore, a higher breakdown voltage is achieved and a higher doping density of the N-well is allowed. Higher doping density can effectively reduce the on-resistance of the LDMOS transistor. Furthermore, the N-well generated beneath a source diffusion region provides a low-impedance path for a source region, which restrict the transistor current flow in between a drain region and a source region.

Offset spacer formation for strained channel CMOS transistor

Abstract: A strained channel transistor and method for forming the the strained channel transistor including a semiconductor rate; a gate dielectric overlying a channel region; a gate rode overlying the gate dielectric; source drain extension regions and source and drain (S/D) regions; wherein a sed dielectric portion selected from the group consisting of r of stressed offset spacers disposed adjacent the gate rode and a stressed dielectric layer disposed over the gate rode including the S/D regions is disposed to exert a strain channel region.

Physical modeling and prediction of the matching properties of MOSFETs

Abstract: A physical model is presented that describes the matching properties of the MOS transistor Fluctuations in channel doping, fixed oxide charge, gate doping, and oxide thickness are taken into account A good agreement is demonstrated between the model and the mismatch in the drain current and transconductance of a 013 /spl mu/m technology Fluctuations in the channel doping are found to be the dominating effect These affect the transistor through the threshold voltage directly, and through Coulomb scattering A prediction is made concerning the matching properties of future technologies It is expected that the fluctuations in the threshold voltage remain constant at A/sub 0/(/spl Delta/V/sub T/)=3 mV/spl mu/m, independently of the technology generation

Programmable memory cell using charge trapping in a gate oxide

Abstract: An illustrative embodiment of the present invention includes a non-volatile, reprogrammable circuit switch. The circuit switch includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide. According to the teachings of the present invention, the MOSFET is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2).

High voltage and low on-resistance ldmos transistor having equalized capacitance

Abstract: A high voltage LDMOS transistor according to the present invention includes P-field blocks in the extended drain region of a N-well. The P-field blocks form the junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown occurs. A higher breakdown voltage is therefore achieved and the N-well having a higher doping density is thus allowed. The higher doping density reduces the on-resistance of the transistor. Furthermore, the portion of the N-well generated beneath the source diffusion region produces a low-impedance path for the source region, which restricts the transistor current flow in between the drain region and the source region.

Programmable fuse device

Abstract: A fuse device including a transistor having a source, drain, and gate. The gate includes a first and second gate contact. A current may be run from the first gate contact to the second gate contact to heat the gate. The current through the gate indirectly heats the channel region beneath the gate, causing localized annealing of the channel region. The heated gate causes dopants to diffuse from the source and drain into the channel region, permanently changing the properties of the transistor material and programming the fuse device. The fuse device functions as a transistor in an unprogrammed state, and acts as a shunt in a programmed state, caused by the shorting of the source and drain of the transistor during programming.

Asymmetric MOS transistor with trench-type gate

Abstract: a A MOS (metal oxide semiconductor) transistor with a trench-type gate is fabricated with a channel stopping region for forming an asymmetric channel region for reducing short channel effects. For example in fabricating an N-channel MOS transistor, a gate structure is formed within a trench that is within a P-well. A channel stopping region with a P-type dopant is formed to a first side of the trench to completely contain an N-type source junction therein. An N-type drain junction is formed within a LDD region to a second side of the trench, thus forming the asymmetric channel region.