Showing papers on "Drain-induced barrier lowering published in 2006"

Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power and RF IC Design

Abstract: Foreword. Preface. List of Symbols. 1. Introduction. 1.1 The Importance of Device Modeling for IC Design. 1.2 A Short History of the EKV MOST Model. 1.3 The Book Structure. PART I: THE BASIC LONG-CHANNELINTRINSIC CHARGE-BASED MODEL. 2. Introduction. 2.1 The N-channel Transistor Structure. 2.2 Definition of charges, current, potential and electric fields. 2.3 Transistor symbol and P-channel transistor. 3. The Basic Charge Model. 3.1 Poisson's Equation and Gradual Channel Approximation. 3.2 Surface potential as a Function of Gate Voltage. 3.3 Gate Capacitance. 3.4 Charge Sheet Approximation. 3.5 Density of Mobile Inverted Charge. 3.6 Charge-Potential Linearization. 4. Static Drain Current. 4.1 Drain Current Expression. 4.2 Forward and Reverse Current Components. 4.3 Modes of Operation. 4.4 Model of Drain Current Based on Charge Linearization. 4.5 Fundamental Property: Validity and Application. 4.6 Channel Length Modulation. 5. The Small-Signal Model. 5.1 The Static Small-Signal Model. 5.2 A General Non-Quasi-Static Small-Signal Model. 5.3 The Quasi-Static Dynamic Small-Signal Model. 6. The Noise Model. 6.1 Noise Calculation Methods. 6.2 Low-Frequency Channel Thermal Noise. 6.3 Flicker Noise. 6.4 Appendices. Appendix : The Nyquist and Bode Theorems. Appendix : General Noise Expression. 7. Temperature Effects and Matching. 7.1 Introduction. 7.2 Temperature Effects. PART II: THE EXTENDED CHARGE-BASED MODEL. 8. Non-Ideal Effects Related to the Vertical Dimension. 8.1 Introduction. 8.2 Mobility Reduction Due to the Vertical Field. 8.3 Non-Uniform Vertical Doping. 8.4 Polysilicon Depletion. 8.4.1 Definition of the Effect. 8.5 Band Gap Widening. 8.6 Gate Leakage Current. 9. Short-Channel Effects. 9.1 Velocity Saturation. 9.2 Channel Length Modulation. 9.3 Drain Induced Barrier Lowering. 9.4 Short-Channel Thermal Noise Model. 10. The Extrinsic Model. 10.1 Extrinsic Part of the Device. 10.2 Access Resistances. 10.3 Overlap Regions. 10.4 Source and Drain Junctions. 10.5 Extrinsic Noise Sources. PART III: THE HIGH-FREQUENCY MODEL. 11. Equivalent Circuit at RF. 11.1 RF MOS Transistor Structure and Layout. 11.2 What Changes at RF?. 11.3 Transistor Figures of Merit. 11.4 Equivalent Circuit at RF. 12. The Small-Signal Model at RF. 12.1 The Equivalent Small-Signal Circuit at RF. 12.2 Y-Parameters Analysis. 12.3 The Large-Signal Model at RF. 13. The Noise Model at RF. 13.1 The HF Noise Parameters. 13.2 The High-Frequency Thermal Noise Model. 13.3 HF Noise Parameters of a Common-Source Amplifier. References. Index.

Utilizing reverse short channel effect for optimal subthreshold circuit design

Abstract: The impact of the Reverse Short Channel Effect (RSCE) on device current is stronger in the subthreshold region due to the reduced Drain-Induced-Barrier-Lowering (DIBL) and the exponential dependency of current on threshold voltage This paper describes a device size optimization method for subthreshold circuits utilizing RSCE to achieve high drive current, low device capacitance, less sensitivity to random dopant fluctuations, and better subthreshold swing Simulation results using ISCAS benchmark circuits show that the critical path delay and power consumption can be improved by up to 104% and 344%, respectively

Impact of drain induced barrier lowering on read scheme in silicon nanocrystal memory with two-bit-per-cell operation

Abstract: The threshold voltages (Vth's) and read schemes of silicon nanocrystal memories with two bits per cell are examined by experiments and simulations. It is found that the drain induced barrier lowering (DIBL) has a marked effect on Vth's in the four states and thus on read schemes for detecting the four Vth's. It is also shown that the read scheme can be selected by controlling DIBL using device parameters including gate length, injected charge fraction, and injected charge density. Suitable read schemes for low-voltage and low-power applications are discussed.

Method for forming an integrated circuit

Abstract: A method is described for manufacturing an n-MOS semiconductor transistor. Recesses are formed in a semiconductor substrate adjacent a gate electrode structure. Silicon is embedded in the recesses via a selective epitaxial growth process. The epitaxial silicon is in-situ alloyed with substitutional carbon and in-situ doped with phosphorus. The silicon-carbon alloy generates a uniaxial tensile strain in the channel region between the source and drain, thereby increasing electron channel mobility and the transistor's drive current. The silicon-carbon alloy decreases external resistances by reducing contact resistance between source/drain and silicide regions and by reducing phosphorous diffusivity, thereby permitting closer placement of the transistor's source/drain and channel regions.

A Three-Dimensional Simulation Study of the Performance of Carbon Nanotube Field-Effect Transistors With Doped Reservoirs and Realistic Geometry

Abstract: This paper simulates the expected device performance and scaling perspectives of carbon nanotube (CNT) field-effect transistors with doped source and drain extensions. The simulations are based on the self-consistent solution of the three-dimensional Poisson-Schroumldinger equation with open boundary conditions, within the nonequilibrium Green's function formalism, where arbitrary gate geometry and device architecture can be considered. The investigation of short channel effects for different gate configurations and geometry parameters shows that double-gate devices offer quasi-ideal subthreshold slope and drain-induced barrier lowering without extremely thin gate dielectrics. Exploration of devices with parallel CNTs shows that on currents per unit width can be significantly larger than the silicon counterpart, while high-frequency performance is very promising

Tunable threshold voltage and flatband voltage in pentacene field effect transistors

Abstract: Charged interface states are introduced by UV-ozone treatment of a polymer gate dielectric, parylene, prior to deposition of the organic semiconductor, pentacene, thereby modifying the organic field effect transistor (OFET) operation from enhancement to depletion mode. Quasistatic capacitance-voltage measurements and the corresponding current-voltage characteristics show that the threshold voltage VT and flatband voltage VFB can be shifted by over +50V, depending on the ozone exposure time. This work demonstrates that careful control of the semiconductor-insulator interface state densities is essential to VT and VFB control and the fabrication of reliable OFET integrated circuits.

Nanocrystal write once read only memory for archival storage

Abstract: Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions. A gate insulator is formed opposing the channel region. The gate insulator includes a number of high work function nanoparticles. A gate is formed on the gate insulator. A plug is coupled to the first source/drain region and couples the first source/drain region to an array plate. A transmission line is coupled to the second source/drain region. The MOSFET is a programmed MOSFET having a charge trapped in the number of high work function nanoparticles in the gate insulator adjacent to the first source/drain region.

Pixel circuit of organic electroluminescent display device and method of driving the same

Abstract: A pixel circuit of an organic electroluminescent display device and a method of driving the same. In the pixel circuit, a capacitor has a first electrode connected to a gate of a driving transistor, and a second electrode connected to a drain of a switching transistor. Further, a compensation voltage applying transistor is connected to the second electrode of the capacitor. The compensation voltage applying transistor compensates for a difference in IR-drops of a power supply voltage in response to a previous emission control signal. Further, the compensation voltage applying transistor cuts off the compensation voltage in an initialization period, thereby preventing a source of a data voltage and a source of the compensation voltage from being shorted with each other. Additionally, a threshold voltage compensation transistor is connected between the gate and the drain of the driving transistor. Therefore, a difference in threshold voltages of driving transistors is compensated.

Soi device with reduced drain induced barrier lowering

Abstract: A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) structure within the insulation layer underlying the p- and n-wells of the SOI wafer. Backend high temperature processing steps induce diffusion of the boron and phosphorus contained in the BPSG into the p- and n-wells, thereby forming a retrograde dopant profile in the wells. The retrograde dopant profile reduces DIBL and also provides recombination centers adjacent the insulator layer and the active layer to thereby reduce floating body effects for the CMOS device.

Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs : Analytical model and design considerations

Abstract: In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient ( d ), (ii) spacer width ( s ), (iii) spacer to doping gradient ratio ( s / d ) and (iv) silicon film thickness ( T si ), on short channel effects – threshold voltage ( V th ) and subthreshold slope ( S ), on-current ( I on ), off-current ( I off ) and I on / I off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG SOI devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below.

Transistor having reduced channel dopant fluctuation

Abstract: According to one exemplary embodiment, a transistor includes a source and a drain separated by a channel. The transistor further includes a gate dielectric layer situated over the channel. The channel is situated in a well formed in a substrate. A pocket implant is not formed between the source and the drain so as to reduce dopant fluctuation in the channel, thereby reducing transistor mismatch. According to this exemplary embodiment, an LDD implant is not formed between the source and the drain so as to further reduce the dopant fluctuation in the channel.

The Impact of Deep Ni Salicidation and $hboxNH_3$ Plasma Treatment on Nano-SOI FinFETs

Abstract: In this letter, 50-nm gate-length nano-silicon-on-insulator FinFETs with deep Ni salicidation and NH3 plasma treatment are fabricated. It is found that device performances, including subthreshold slope (SS) drain-induced barrier lowering (DIBL) and off-state leakage current, can be greatly improved by using deep Ni salicidation process compared to no Ni salicidation process. The deep Ni-salicided devices effectively suppress the floating-body effect and parasitic bipolar junction transistor action. In addition, the effect of NH3 plasma on the deep Ni-salicided devices is discussed. Experimental results reveal that the devices under a new state-of-the-art NH3 plasma process can achieve better performance such as an SS of 66 mV/dec and a DIBL of 0.03 V

Analytical modeling of the two-dimensional potential distribution and threshold voltage of the SOI four-gate transistor

Abstract: The two-dimensional (2-D) channel potential and threshold voltage of the silicon-on-insulator (SOI) four-gate transistor (G4-FET) are modeled. The 2-D analytical body potential is derived by assuming a parabolic potential variation between the lateral junction-gates and by solving Poisson's equation. The model is used to obtain the surface threshold voltage of the G4-FET as a function of the lateral gate bias and for all possible charge conditions at the back interface. The body-potential model is extendable to fully depleted SOI MOSFETs and can serve to depict the charge-sharing and drain-induced barrier-lowering effects in short-channel devices

Bias Stress Induced Threshold Voltage Shift in Pentacene Thin-Film Transistors

Abstract: Threshold voltage instabilities in SiO2/polyimide dual-gate dielectric pentacene thin-film transistors are investigated as a function of bias stress time for 1000 s at temperatures between 260 and 340 K in nitrogen atmosphere. Field-effect mobility maintains constant values at every measurement temperature during the application of constant bias stress voltage. The threshold voltage shift at all measurement temperatures is described by the stretched exponential stress time dependence of ΔVth(t) = ΔVth0{1-exp [-(t/τ)β]}. These experimental results suggest that our threshold voltage shift can be interpreted as carrier injection from the pentacene channel into traps located at the channel/gate dielectric interface.

A novel 50 nm vertical MOSFET with a dielectric pocket

Abstract: A vertical metal-oxide-semiconductor field-effect transistor with the novel feature of a dielectric pocket between the channel and source/drain has been fabricated and tested. These dielectric pocket vertical MOSFETs (DPV-MOSFETs) show an improved suppression of short-channel effects such as VT roll-off and drain induced barrier lowering (DIBL). This is due to reduced charge sharing, thus allowing better threshold voltage control. The dielectric pocket also prevents dopant diffusion from the source/drains into the body during device fabrication, mitigating bulk punchthrough.

Semiconductor integrated circuit apparatus

Abstract: Providing semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current. The monitor unit includes a constant current source and a monitoring MOSFET formed on the same substrate as the plurality of MOSFETs, the substrate voltage regulating unit includes a comparison unit for comparing the source potential of the monitoring MOSFET with a predetermined reference potential with the drain terminal of the monitoring MOSFET and the drain terminals of the plurality of MOSFETs connected to the ground potential, and substrate voltage regulating unit feeds back the output voltage output based on the comparison result by the comparison unit to the substrate voltage of the monitoring MOSFET.

Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channels

Abstract: The performance of thin-film transistors with a novel poly-Si nanowire channel prepared by solid-phase crystallization is investigated in this paper. As compared with conventional planar devices having self-aligned source/drain, the new devices show an improved on-current per unit width and better control over the short channel effects. The major conduction mechanism of the off-state leakage is identified as the gate-induced drain leakage, and it is closely related to the source/drain implant condition and the unique device structure

A subthreshold surface potential model for short-channel MOSFET taking into account the varying depth of channel depletion layer due to source and drain junctions

Abstract: An analytical subthreshold surface potential model for short-channel MOSFET is presented. In this model, the effect of varying depth of the channel depletion layer on the surface potential has been considered. The effect of the depletion layers around the source and drain junctions on the surface potential, which is very important for short channel devices is included in this model. With this, the drawback of the existing models that assume a constant channel depletion layer thickness is removed resulting in a more accurate prediction of the surface potential. A pseudo-two-dimensional method is adopted to retain the accuracy of two-dimensional analysis yet resulting in a simpler manageable one-dimensional analytical expression. The subthreshold drain current is also evaluated utilizing this surface potential model.

Source/Drain Extensions Having Highly Activated and Extremely Abrupt Junctions

Abstract: A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90 . Dopants are implanted into the SiGe source/drain extensions 90 and the semiconductor wafer 10 is annealed. Also, a transistor source/drain region 80, 90 having a SiGe source/drain extension 90 that contains evenly distributed dopants, is highly doped, and has highly abrupt edges.

Fast dynamic low-voltage current mirror with compensated error

Abstract: A current mirror comprising: a current source; a first p-channel MOS transistor having a source coupled to an operating potential, and a gate and a drain coupled to the current source; a second p-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate of the first p-channel transistor, and a drain; a first n-channel MOS transistor having a source coupled to ground, and a gate and a drain coupled to the drain of the second p-channel transistor; a zero-threshold n-channel MOS transistor having a drain coupled to a current-output node, a gate coupled to the gate of the first n-channel transistor, and a source; and a second n-channel MOS transistor having a source coupled to ground, and a gate coupled to the gate of the first n-channel transistor and a drain coupled to the source of the zero-threshold n-channel transistor.

MOS transistor with elevated source/drain structure

Abstract: In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

High voltage ESD power clamp

Abstract: Method and device for protecting against electrostatic discharge The method includes configuring a gate of at least one upper transistor of a transistor network connected between power rails to be biased to a prescribed value, and coupling an electrostatic discharge event to a gate of a lower transistor of the transistor network The at least one upper and at least one lower transistors of the transistor network are respectively coupled between the power rails from a higher voltage to a lower voltage

Field effect transistor using oxide film for channel, and manufacturing method thereof

Abstract: PROBLEM TO BE SOLVED: To solve the problem that Id-Vg characteristic sometimes varies in a thin-film transistor using oxides including an amorphous In-Ga-Zn-O system. SOLUTION: A field effect transistor having an oxide film as a semiconductor layer 11 has a source and a drain to which hydrogen or heavy hydrogen is added into the oxide film. A channel 18, a source 16 and a drain 17 are included in the oxide film, and the concentration of hydrogen or heavy hydrogen in the source section and the drain section is larger than that in the channel. The source and the drain are arranged as self-aligned with a gate electrode arranged through a gate insulation layer, and have a coplanar structure. COPYRIGHT: (C)2007,JPO&INPIT

Circuit and method of effectively enhancing drive control of light-emitting diodes

Abstract: An LED drive circuit includes a plurality of LEDs, a power supply circuit for outputting a variable output voltage to supply electricity to the LEDs, a plurality of drive transistors for driving the respective LEDs, a bias voltage setting circuit for generating and outputting a reference gate voltage for causing the drive transistors to have drain currents having a predetermined constant value, and a minimum drain voltage for causing the drive transistors to have the predetermined constant drain currents when the reference gate voltage is input to the drive transistors, and a voltage detection circuit for sequentially comparing drain voltages of the drive transistors with the minimum drain voltage to output one of the drain voltages smaller than the minimum drain voltage, wherein the power supply circuit controls the output voltage so that the drain voltage output from the voltage detection circuit becomes greater than or equal to the minimum drain voltage.

Field-effect transistor and thyristor

Abstract: A decrease in breakdown voltage can be prevented as much as possible. A field-effect transistor includes: a drain region made of SiC; a drift layer which is formed on the drain region and is made of n-type SiC; a source region which is formed on the surface of the drift layer and is made of n-type SiC; a channel region which is formed on the surface of the drift layer located on a side of the source region and is made of SiC; an insulating gate which is formed on the channel region; and a p-type base region interposed between the bottom portion of the source region and the drift region, and containing two kinds of p-type impurities.

Non-planar transistor and techniques for fabricating the same

Abstract: A non-planar transistor and methods for fabricating the same. In certain embodiments, the transistor includes an active gate and a passive gate. The active gate may be switchably coupled to a first voltage that is configured to turn on the transistor, and the passive gate may be fixedly coupled to a second voltage different than the first voltage. In some embodiments, the difference in voltage between the first voltage and the second voltage is greater than or substantially equal to a difference in voltage between the first voltage and a substrate voltage.

Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering and methods for fabricating such device structures and for fabricating a semiconductor-on-insulator substrate

Abstract: Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering, methods for fabricating such device structures, and methods for forming a semiconductor-on-insulator substrate. The semiconductor structure comprises a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant. In one embodiment, the dielectric constant of the first dielectric region may be less than about 3.9 and the dielectric constant of the second dielectric region may be greater than about ten (10). The semiconductor-on-insulator substrate comprises a semiconductor layer separated from a bulk layer by an insulator layer of a high-dielectric constant material. The fabrication methods comprise modifying a region of the dielectric layer to have a lower dielectric constant.

Electrical Properties of Phase Change and Channel Current Control in Ultrathin Phase-Change Channel Transistor Memory by Annealing

Abstract: We studied phase-change channel transistor memory devices with an ultrathin Ge2Sb2Te5 chalcogenide film channel and tried to demonstrate two combined functions (memory: resistance change and selection: channel current control) by annealing in this paper. Drain–source resistance can be markedly decreased by 2 – 3 orders of magnitude after annealing due to the phase change from the amorphous to crystalline phases. A channel current control effect in which the drain current decreases with the gate voltage was clearly observed in 10- and 20-nm-thick Ge2Sb2Te5 devices. The absolute channel current modulation by the gate voltage in the crystalline state is much stronger than that in the amorphous state. Furthermore, the channel current control ability in devices with thin Ge2Sb2Te5 is stronger than that in devices with thick Ge2Sb2Te5. The channel current control effect might result from the potential change of the ultrathin Ge2Sb2Te5 channel by the gate voltage. [DOI: 10.1143/JJAP.45.3238]

Shallow junctions on pillar sidewalls for sub-100-nm vertical MOSFETs

Abstract: A simple process for the fabrication of shallow drain junctions on pillar sidewalls in sub-100-nm vertical MOSFETs is described. The key feature of this process is the creation of a polysilicon spacer around the perimeter of the pillar to connect the channel to a polysilicon drain contact. The depth of the junction on the pillar sidewall is primarily determined by the thickness of the polysilicon spacer. This process is CMOS compatible and, hence, facilitates the integration of a sub-100-nm vertical MOSFET in a planar CMOS technology using mature lithography. The fabricated transistors have a subthreshold slope of 95 mV/dec (at VDS=1 V) and a drain-induced barrier lowering of 0.12 V