Showing papers on "Drain-induced barrier lowering published in 2007"

Gate Injection Transistor (GIT)—A Normally-Off AlGaN/GaN Power Transistor Using Conductivity Modulation

Abstract: We have developed a normally-off GaN-based transistor using conductivity modulation, which we call a gate injection transistor (GIT). This new device principle utilizes hole-injection from the p-AlGaN to the AlGaN/GaN heterojunction, which simultaneously increases the electron density in the channel, resulting in a dramatic increase of the drain current owing to the conductivity modulation. The fabricated GIT exhibits a threshold voltage of 1.0 V with a maximum drain current of 200 mA/mm, in which a forward gate voltage of up to 6 V can be applied. The obtained specific ON-state resistance (RON . A) and the OFF-state breakdown voltage (BV ds) are 2.6 mOmega . cm2 and 800 V, respectively. The developed GIT is advantageous for power switching applications.

Graphene-based transistor

Abstract: A graphene layer is formed on a surface of a silicon carbide substrate. A dummy gate structure is formed over the fin, in the trench, or on a portion of the planar graphene layer to implant dopants into source and drain regions. The dummy gate structure is thereafter removed to provide an opening over the channel of the transistor. Threshold voltage adjustment implantation may be performed to form a threshold voltage implant region directly beneath the channel, which comprises the graphene layer. A gate dielectric is deposited over a channel portion of the graphene layer. After an optional spacer formation, a gate conductor is formed by deposition and planarization. The resulting graphene-based field effect transistor has a high carrier mobility due to the graphene layer in the channel, low contact resistance to the source and drain region, and optimized threshold voltage and leakage due to the threshold voltage implant region.

Analytical Model of the Threshold Voltage and Subthreshold Swing of Undoped Cylindrical Gate-All-Around-Based MOSFETs

Abstract: Analytical physically based models for the threshold voltage, subthreshold swing, and drain-induced barrier lowering (DIBL) of undoped cylindrical gate-all-around MOSFETs have been derived based on an analytical solution of 2-D Poisson's equation (in cylindrical coordinates) in which the mobile charge term has been included. Using the new model, threshold voltage, DIBL and subthreshold swing sensitivities to channel length, and channel thickness have been investigated. The models for DIBL, subthreshold swing, and threshold voltage rolloff parameters have been verified by comparison with 3-D numerical simulations; close agreement with the numerical simulations has been observed

MOS transistor with elevated source and drain structures and method of fabrication thereof

Abstract: A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.

Normally Off AlGaN/GaN Low-Density Drain HEMT (LDD-HEMT) With Enhanced Breakdown Voltage and Reduced Current Collapse

Abstract: We report a low-density drain high-electron mobility transistor (LDD-HEMT) that exhibits enhanced breakdown voltage and reduced current collapse. The LDD region is created by introducing negatively charged fluorine ions in the region between the gate and drain electrodes, effectively modifying the surface field distribution on the drain side of the HEMT without using field plate electrodes. Without changing the device physical dimensions, the breakdown voltage can be improved by 50% in LDD-HEMT, and the current collapse can be reduced. No degradation of current cutoff frequency (ft) and slight improvement in power gain cutoff frequency (fmax) are achieved in the LDD-HEMT, owing to the absence of any additional field plate electrode

Two-Dimensional Analytical Threshold Voltage and Subthreshold Swing Models of Undoped Symmetric Double-Gate MOSFETs

Abstract: We have developed analytical physically based models for the threshold voltage [including the drain-induced barrier lowering (DIBL) effect] and the subthreshold swing of undoped symmetrical double-gate (DG) MOSFETs The models are derived from an analytical solution of the 2-D Poisson equation in which the electron concentration was included The models for DIBL, subthreshold swing, and threshold voltage roll-off have been verified by comparison with 2-D numerical simulations for different values of channel length, channel thickness, and drain-source voltage; very good agreement with the numerical simulations has been observed

Impact of fin width on digital and analog performances of n-FinFETs

Abstract: This paper examines the impact of an important geometrical parameter of FinFET devices, namely the fin width. From static and low-frequency measurements on n-FinFETs ( I – V , C – V and 1/ f noise), transistor Figures of Merit in the near-threshold region (like threshold voltage, subthreshold slope, and drain induced barrier lowering); linear region (mobility, series resistance, 1/ f noise) and saturation region (normalized transconductance, early voltage) are analyzed as a function of fin width. In the near-threshold region, fin width is seen to strongly impact the coupling between the back and front gates, while in the above threshold region, the most important impact of fin width is on the parasitic source/drain resistance, which affects different strong inversion parameters to different extents. With the help of analytical expressions, the impact of series resistance on these device parameters is studied, and the contribution from series resistance is de-embedded, enabling extraction of intrinsic device parameters. Significant differences are observed between the intrinsic and extrinsic parameters, especially for short and narrow devices, which also underlines the need for accounting for series resistance effects at every stage of FinFET characterization.

Ambipolar organic light emitting field effect transistors with modified asymmetric electrodes

Abstract: The authors report on gate-controlled light emission from an organic field effect transistor composed of a vapor-deposited thin film of α,ω-bis(biphenyl-4-yl)-terthiophene (BP3T) with an electron injection layer of pentacene for the drain electrode. A n-triacontane thin film vapor deposited on a Si∕SiO2 wafer was used as a buffer layer for the gate dielectric. The location of emission zones within the channel where both injected carriers recombine was controlled by the gate voltage. The insertion of the pentacene and n-triacontane layers improved the threshold voltage and mobility for electrons, resulting in balanced ambipolar carrier injection and transport.

Gallium nitride high electron mobility transistor having inner field-plate for high power applications

Abstract: A gallium nitride high electron mobility transistor, in which an inner field-plate is disposed between the gate and drain of the high electron mobility transistor, so that an electric field is distributed between gate and drain regions to reduce a peak value and to reduce gate leakage current while maintaining high frequency performance, thus obtaining a high breakdown voltage, reducing the capacitance between the gate and the drain attributable to a shielding effect, and improving linearity and high power and high frequency characteristics through variation in the input voltage of the inner field-plate.

Substrate engineering for high-performance surface-channel III-V metal-oxide-semiconductor field-effect transistors

Abstract: High-performance inversion-type enhancement-mode n-channel In0.65Ga0.35As metal-oxide-semiconductor field-effect transistors (MOSFETs) with atomic-layer-deposited Al2O3 as gate dielectric are demonstrated. A 0.5μm gate-length MOSFET with an Al2O3 gate oxide thickness of 10nm shows a gate leakage current less than 5×10−6A∕cm2 at 4V gate bias, a threshold voltage of 0.40V, a maximum drain current of 670mA∕mm, and transconductance of 230mS∕mm at drain voltage of 2V. More importantly, a model is proposed to ascribe this 80% improvement of device performance from In0.53Ga0.47As MOSFETs mainly to lowering the energy level difference between the charge neutrality level and conduction band minimum for In0.65Ga0.35As. The right substrate or channel engineering is the main reason for the high performance of the devices besides the high-quality oxide-semiconductor interface.

A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory

Abstract: In this letter, a polycrystalline silicon thin-film transistor consisting of silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire (NW) channels was investigated for the applications of transistor and nonvolatile memory. The proposed device, which is named as NW SONOS-TFT, has superior electrical characteristics of transistor, including a higher drain current, a smaller threshold voltage (Vth) , and a steeper subthreshold slope. Moreover, the NW SONOS-TFT also can exhibit high program/erase efficiency under adequate bias operation. The duality of both transistor and memory device for the NW SONOS-TFT can be attributed to the trigate structure and channel corner effect.

AlN∕AlGaN∕GaN metal-insulator-semiconductor high-electron-mobility transistor on 4in. silicon substrate for high breakdown characteristics

Abstract: AlN∕AlGaN∕GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) grown on 4in. silicon substrate have been demonstrated. The heterostructure exhibited high sheet carrier density with small surface roughness. AlN∕AlGaN∕GaN MIS-HEMT exhibited maximum drain current density (IDSmax) of 361mA∕mm and maximum extrinsic transconductance (gmmax) of 152mS∕mm. Due to the increase of sheet carrier density, the 2DEG channel shifts towards the AlGaN/GaN interface resulting in positive shift of the threshold voltage (−2.6to−1.8V). Two orders of magnitude low gate leakage current and reduced drain current collapse with high breakdown voltage of 230V have been observed on AlN∕AlGaN∕GaN MIS-HEMTs.

Threshold voltage in tunnel FETs: physical definition, extraction, scaling and impact on IC design

Abstract: This work reports on the physical definition and extraction of threshold voltage in tunnel FETs based on numerical simulation data. It is shown that the tunnel FET has the outstanding property of having two threshold voltages: one in terms of gate voltage, VTG, and one in terms of drain voltage, VTD. These threshold voltages can be physically defined based on the saturation of the barrier width narrowing with respect to VG or VD. The extractions of VTG and VTD are performed based on the transconductance change method in the double gate tunnel FET with a high-k dielectric, and a systematic comparison with the constant current method is reported. The effect of gate length scaling on these threshold voltages, current, conductance characteristics, gm/ID and gm/gds of the tunnel FET is investigated for the first time.

Impact of graded channel (GC) design in fully depleted cylindrical/surrounding gate MOSFET (FD CGT/SGT) for improved short channel immunity and hot carrier reliability

Abstract: In the present paper, a two-dimensional (2-D) analytical model for graded channel fully depleted cylindrical/surrounding gate MOSFET (GC FD CGT/SGT) has been developed by solving the Poisson’s equation in cylindrical coordinates. An abrupt transition of silicon film doping at the interface has been assumed and the effects of the doping and the lengths of the high and low doped regions have been taken into account. The model is used to obtain the expressions of surface potential and electric field in the two regions. The analysis is extended to obtain the expressions for threshold voltage (Vth) and subthreshold swing. It is shown that a graded doping profile in the channel leads to suppression of short channel effects (SCEs) like threshold voltage roll-off, drain induced barrier lowering (DIBL) and hot carrier effects. The results so obtained have been compared with simulated results obtained using the device simulator ATLAS 3D and are found to be in good agreement.

Semiconductor memory device using only single-channel transistor to apply voltage to selected word line

Abstract: A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other.

Tuning the threshold voltage of organic field-effect transistors by an electret encapsulating layer

Abstract: Here, the authors present a technique to adjust the threshold voltage of an organic field-effect transistor (OFET) using a design similar to a dual-gate structure with an insulating Teflon-based electret layer as a second gate The threshold voltage of a pentacene bottom gate OFET was shifted from +131to−23V by depositon of a 17μm thick electret layer, proving the principal feasibility of this approach This controlled tuning of the threshold voltage compensates one of the main drawbacks of organic electronics and even allows switching from a depletion to an enhancement-type transistor behavior

Mos device and process having low resistance silicide interface using additional source/drain implant

Abstract: An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm−3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.

Field effect transistor containing a wide band gap semiconductor material in a drain

Abstract: A field effect transistor comprising a silicon containing body is provided. After formation of a gate dielectric, gate electrode, and a first gate spacer, a drain side trench is formed and filled with a wide band gap semiconductor material. Optionally, a source side trench may be formed and filled with a silicon germanium alloy to enhance an on-current of the field effect transistor. Halo implantation and source and drain ion implantation are performed to form various doped regions. Since the wide band gap semiconductor material as a wider band gap than that of silicon, impact ionization is reduced due to the use of the wide band gap semiconductor material in the drain, and consequently, a breakdown voltage of the field effect transistor is increased compared to transistors employing silicon in the drain region.

Field effect transistor devices and methods

Abstract: A field-effect transistor device is provided, including: a substrate; a vertically stacked layered semiconductor structure on the substrate including the following layers: a first quantum well layer having laterally spaced-apart drain and source regions that are each delta-doped with a dopant of a first conductivity type, the drain and source regions being laterally separated by a channel region; and a second quantum well layer vertically spaced from the first quantum well layer by a gate spacing layer, the second quantum well layer having a gate region, above the channel region, which is delta-doped with a dopant; and couplings for applying electrical potentials with respect to said source, drain, and gate regions.

MOS devices having elevated source/drain regions

Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate electrode. The elevated metallized source/drain region adjoins the silicide region.

Depletion width measurement in an organic Schottky contact using a metal-semiconductor field-effect transistor

Abstract: Although the capacitance measurement is a common method to obtain the depletion width in a Schottky contact, the method is challenging in an organic Schottky junction since the capacitance is a combination of the capacitances associated with the trapped charges, bulk semiconductor, and the depletion region. The authors have implemented a metal-semiconductor field-effect transistor structure in order to estimate the depletion width in an organic Schottky contact. In the transistor the depletion width is calculated from the drain current at a small drain-source voltage. The result indicates a nonquadratic relation between the voltage and the depletion width.

Field effect transistor, logic circuit including the same and methods of manufacturing the same

Abstract: Provided are a field effect transistor, a logic circuit including the same and methods of manufacturing the same. The field effect transistor may include an ambipolar layer that includes a source region, a drain region, and a channel region between the source region and the drain region, wherein the source region, the drain region, and the channel region may be formed in a monolithic structure, a gate electrode on the channel region, and an insulating layer separating the gate electrode from the ambipolar layer, wherein the source region and the drain region have a width greater than that of the channel region in a second direction that crosses a first direction in which the source region and the drain region are connected to each other.

Asymmetric field effect transistor structure and method

Abstract: Disclosed are embodiments of an asymmetric field effect transistor structure (200a-c) and a method of forming the structure in which both series resistance in the source region (204, 304) (Rs) and gate (210, 310) to drain ((205, 305) capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay) Specifically, different heights (214, 215) of the source (204) and drain regions (205) and/or different distances (351, 352) between the source (304) and drain regions (305) and the gate (210, 310) are tailored to minimize series resistance in the source region (204, 305) (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate (210, 310) to drain (205, 305) capacitance (i.e., in order to simultaneously ensure that gate ( 210, 310) to drain (205, 305) capacitance is less than a predetermined capacitance value).

Method for forming a transistor having gate dielectric protection and structure

Abstract: A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure.

Nanowire tunneling transistor

Abstract: A transistor comprises a nanowire (22, 22') having a source (24) and a drain (29) separated by an intrinsic or lowly doped region (26, 28). A potential barrier is formed at the interface of the intrinsic or lowly doped region (26, 28) and one of the source (24) and the drain (29). A gate electrode (32) is provided in the vicinity of the potential barrier such that the height of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode (32).

Method and Apparatus for Dynamic Threshold Voltage Control of MOS Transistors in Dynamic Logic Circuits

Abstract: Metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, that are area efficient, and that exhibit improved drive strength and leakage current that are disclosed. A dynamic threshold voltage control scheme is used that does not require a change to existing MOS technology processes. Threshold voltage of the transistor is controlled, such that in the Off state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. The advantages provided by apply to dynamic logic, as well as in the specific well separation imposed by design rules because well potential difference are lower than the supply voltage swing.

Monolithically Integrated Logic nor Gate Based on GaAs/AlGaAs Three-Terminal Junctions

Abstract: Room-temperature operation of a logic NOR gate is demonstrated. The NOR gate is based on three three-terminal junctions (TTJs) monolithically integrated in a modulation-doped GaAs/AlGaAs heterostructure without any external load resistance. For the logic NOR gate, one of the TTJs serves as load transistor, whereas the other two are used as inputs. Each TTJ has a 90-nm-wide channel and shows clear transistor characteristics with drain currents up to 10 muA for a drain voltage of 1 V. Furthermore, voltage amplification is demonstrated for the logic NOR-gate function.

Design Structures Incorporating Semiconductor Device Structures with Reduced Junction Capacitance and Drain Induced Barrier Lowering

Abstract: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconductor device structure of the design structure includes a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant.