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Showing papers on "Drain-induced barrier lowering published in 2009"


Proceedings ArticleDOI
01 Dec 2009
TL;DR: In this paper, a self-aligned top-gate amorphous oxide TFTs for large size and high resolution displays are presented, where Ar plasma is exposed on the source/drain region of active layer to minimize the source and drain series resistances.
Abstract: We have demonstrated self-aligned top-gate amorphous oxide TFTs for large size and high resolution displays. The processes such as source/drain and channel engineering have been developed to realize the self-aligned top gate structure. Ar plasma is exposed on the source/drain region of active layer to minimize the source/drain series resistances. To prevent the conductive channel, N 2 O plasma is also treated on the channel region of active layer. We obtain a field effect mobility of 5.5 cm2/V·s, a threshold voltage of 1.1 V, and a sub-threshold swing of 0.35 V/decade at sub-micron a-GIZO TFTs with the length of 0.67#x00B5;m. Furthermore, a-IZO TFTs fabricated for gate and data driver circuits on glass substrate exhibit excellent electrical properties such as a field effect mobility of 115 cm2/V·s, a threshold voltage of 0.2 V, a sub-threshold swing of 0.2 V/decade, and low threshold voltage shift less than 1 V under bias temperature stress for 3 hr.

957 citations


Journal ArticleDOI
TL;DR: In this article, the authors describe a metaloxide-semiconductor MOS transistor concept in which there are no junctions and the channel doping is equal in concentration and type to the source and drain extension doping.
Abstract: This paper describes a metal-oxide-semiconductor MOS transistor concept in which there are no junctions. The channel doping is equal in concentration and type to the source and drain extension doping. The proposed device is a thin and narrow multigate field-effect transistor, which can be fully depleted and turned off by the gate. Since this device has no junctions, it has simpler fabrication process, less variability, and better electrical properties than classical MOS devices with source and drain PN junctions.

903 citations


Journal ArticleDOI
TL;DR: It is shown that at a certain gate bias, the impact of the metal on the channel potential profile extends into the channel for more than one-third of the total channel length from both source and drain sides; hence, most of the channel is affected by the metal.
Abstract: We measure the channel potential of a graphene transistor using a scanning photocurrent imaging technique. We show that at a certain gate bias, the impact of the metal on the channel potential profile extends into the channel for more than one-third of the total channel length from both source and drain sides; hence, most of the channel is affected by the metal. The potential barrier between the metal-controlled graphene and bulk graphene channel is also measured at various gate biases. As the gate bias exceeds the Dirac point voltage, VDirac, the original p-type graphene channel turns into a p-n-p channel. When light is focused on the p-n junctions, an impressive external responsivity of 0.001 A/W is achieved, given that only a single layer of atoms are involved in photon detection.

597 citations


Journal ArticleDOI
TL;DR: In this article, a lateral strained double-gate TFET (SDGTFET) is presented, which has a higher on-current, low leakage, low threshold voltage, excellent sub-threshold slope, and good short channel effects.
Abstract: Tunnel field effect transistor (TFET) devices are attractive as they show good scalability and have very low leakage current. However they suffer from low on-current and high threshold voltage. In order to employ the TFET for circuit applications, these problems need to be tackled. In this paper, a novel lateral strained double-gate TFET (SDGTFET) is presented. Using device simulation, we show that the SDGTFET has a higher on-current, low leakage, low threshold voltage, excellent subthreshold slope, and good short channel effects and also meets important ITRS guidelines.

128 citations


Journal ArticleDOI
TL;DR: In this paper, the bias stress effect in pentacene organic thin-film transistors has been investigated and it was found that when a drain-source voltage is applied to the transistor during gate bias stress, the tilting of the HOMO and LUMO bands along the channel creates a pathway for the fast release of trapped carriers.
Abstract: The bias stress effect in pentacene organic thin-film transistors has been investigated. The transistors utilize a thin gate dielectric based on an organic self-assembled monolayer and thus can be operated at low voltages. The bias stress-induced threshold voltage shift has been analyzed for different drain-source voltages. By fitting the time-dependent threshold voltage shift to a stretched exponential function, both the maximum (equilibrium) threshold voltage shift and the time constant of the threshold voltage shift were determined for each drain-source voltage. It was found that both the equilibrium threshold voltage shift and the time constant decrease significantly with increasing drain-source voltage. This suggests that when a drain-source voltage is applied to the transistor during gate bias stress, the tilting of the HOMO and LUMO bands along the channel creates a pathway for the fast release of trapped carriers.

104 citations


Journal ArticleDOI
TL;DR: In this paper, the surrounding field effect in a multi-mesa channel (MMC) with an AlGaN/GaN structure, in which a periodic trench structure is fabricated directly under a gate electrode, was successfully observed.
Abstract: The surrounding-field effect in a multi-mesa-channel (MMC) with an AlGaN/GaN structure, in which a periodic trench structure is fabricated directly under a gate electrode, was successfully observed. This effect resulted in a shallower threshold voltage, a smaller subthreshold slope, and a higher current drivability of a high electron mobility transistor (HEMT) than those of a standard planar-type HEMT. In addition, the MMC HEMT showed a low knee voltage, even with a wide spacing between the gate and drain electrodes. Excellent current stability in the saturation region of the MMC HEMT, probably due to the effective radiation of heat from both mesa sides of the channel, was also observed. Both planar and MMC HEMTs showed similar breakdown voltages under off-state operation, indicating no significant degradation in the breakdown characteristics of AlGaN/GaN HEMTs with a periodic trench structure in the gate region.

92 citations


Patent
30 Jun 2009
TL;DR: In this article, three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas (211D, 211S), the fins (210) and isolation structures (208A) in a self-aligned manner within a bulk semiconductor material.
Abstract: Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas (211D, 211S), the fins (210) and isolation structures (208A) in a self- aligned manner within a bulk semiconductor material. After defining the basic fin structures (210), highly efficient manufacturing techniques of planar transistor configurations may be used, thereby even further enhancing overall performance of the three-dimensional transistor configurations.

85 citations


Journal ArticleDOI
TL;DR: In this paper, a physically based continuous potential distribution model was proposed for a short-channel undoped body symmetrical double-gate transistor, which is valid from weak to strong inversion regimes and from the channel center to the surface.
Abstract: A new physically based classical continuous potential distribution model, particularly considering the channel center, is proposed for a short-channel undoped body symmetrical double-gate transistor. It involves a novel technique for solving the 2-D nonlinear Poisson's equation in a rectangular coordinate system, which makes the model valid from weak to strong inversion regimes and from the channel center to the surface. We demonstrated, using the proposed model, that the channel potential versus gate voltage characteristics for the devices having equal channel lengths but different thicknesses pass through a single common point (termed ldquocrossover pointrdquo). Based on the potential model, a new compact model for the subthreshold swing is formulated. It is shown that for the devices having very high short-channel effects (SCE), the effective subthreshold slope factor is mainly dictated by the potential close to the channel center rather than the surface. SCEs and drain-induced barrier lowering are also assessed using the proposed model and validated against a professional numerical device simulator.

59 citations


Journal ArticleDOI
TL;DR: In this article, bottom-contact n-channel C60 thin-film transistors with drain/source electrodes modified by benzenethiol derivatives have been fabricated to investigate the influence of the modification on the transistor characteristics.
Abstract: Bottom-contact n-channel C60 thin-film transistors (TFTs) with drain/source electrodes modified by benzenethiol derivatives have been fabricated to investigate the influence of the modification on the transistor characteristics. Modification using methylbenzenethiol, aminobenzenethiol, and (dimethylamino)benzenethiol having electron-donating groups causes threshold voltages to shift to low voltages. In addition, the modification provides no significant decrease in saturation mobilities. A C60 TFT with (dimethylamino)benzenethiol-modified electrodes has a low threshold voltage of 5.1 V as compared to that of 16.8 V for a TFT with nonmodified electrodes. The threshold-voltage shift is probably because the modification reduces electron-injection barrier height and improves electron injection into organic semiconductors.

57 citations


Journal ArticleDOI
TL;DR: In this paper, the DC currentvoltage characteristics of an n-channel silicon MOSFET with an effective gate length of about 60 nm were analyzed and interpreted in terms of scattering theory.
Abstract: The DC current-voltage characteristics of an n-channel silicon MOSFET with an effective gate length of about 60 nm are analyzed and interpreted in terms of scattering theory. The experimental results are found to be consistent with the predictions of scattering theory - the drain current is closer to the ballistic limit under high drain bias than under low drain bias, and the on-current in strong inversion is limited by a small portion of the channel near the source. The question of how the low- and high- V DS drain currents are related to the near-equilibrium, long-channel mobility is also addressed. In the process of this analysis, theoretical and experimental uncertainties that make it difficult to extract numerically precise values of the scattering parameters are identified.

48 citations


Patent
Chung-Hsun Lin1, Josephine B. Chang1
28 Aug 2009
TL;DR: In this article, the authors proposed reducing the fin height external to the gate structure to reduce parasitic resistance in a multi-gate transistor, which can be referred to as a FinFET.
Abstract: A transistor, which can be referred to as a multi-gate transistor or as a FinFET, includes a gate structure having a length, a width and a height. The transistor further includes at least one electrically conductive channel or fin between a source region and a drain region that passes through the width of the gate structure. The channel has a first height (h 1 ) within the gate structure that is less than the height of the gate structure, and has a second height (h 2 ) external to the gate structure, where h 2 is less than h 1 . The transistor further includes a silicide layer disposed at least partially over the at least one channel external to the gate structure. Reducing the fin height external to the gate structure is shown to beneficially reduce parasitic resistance.

Patent
Shu-Wei Vanessa Chung1, Kuo-Feng Yu1
28 Aug 2009
TL;DR: In this article, a semiconductor device is provided which includes a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of a gate, the source and drain having a first type of conductivity and a lightly doped region formed in a substrate and aligned with a side of gate structure.
Abstract: A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first type of conductivity, a lightly doped region formed in the substrate and aligned with a side of the gate structure, the lightly doped region having the first type of conductivity, and a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity.

Journal ArticleDOI
TL;DR: In this article, a numerical investigation on the behavior of a rugged LDMOS transistor operating in the high current-voltage pulsed regime is carried out with the aim of clarifying the physical origin of the current enhancement that is visible in the output characteristics at high drain and gate biases.
Abstract: In this paper, a numerical investigation on the behavior of a rugged LDMOS transistor operating in the high current-voltage pulsed regime is carried out with the aim of clarifying the physical origin of the current "enhancement" that is visible in the output characteristics at high drain and gate biases. The investigation shows that the output characteristics are significantly affected by the "quasi-saturation" effect at low drain voltages. The impact-ionization rate in the drain extension at high drain voltages reduces the series resistance of the drift region and, hence, raises the electrostatic potential near the channel end, thus driving the intrinsic MOSFET into a saturation condition. The analysis provides a clear insight on the "quasi-saturation" and current "enhancement" effects, which is instrumental for the development of compact models that are particularly useful for circuit-design tools.

Journal ArticleDOI
TL;DR: In this paper, a dual material gate (DMG)-CNTFET was proposed and simulated using quantum simulation that is based on self-consistent solution between two-dimensional Poisson equation and Schrodinger equation with open boundary conditions, within the nonequilibrium Green's function (NEGF) framework.
Abstract: For the first time, a new type of carbon nanotube field-effect transistor (CNTFET), the dual material gate (DMG)-CNTFET, is proposed and simulated using quantum simulation that is based on self-consistent solution between two-dimensional Poisson equation and Schrodinger equation with open boundary conditions, within the nonequilibrium Green's function (NEGF) framework. The proposed structure is similar to that of the conventional coaxial CNTFET with the exception that the gate of the DMG-CNTFET consists of two laterally contacting metals with different work functions. Simulation results show DMG-CNTFET significantly decreases leakage current, drain conductance and subthreshold swing, and increases on–off current ratio and voltage gain as compared to conventional CNTFET. We demonstrate that the potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed short-channel effects like the drain-induced barrier lowering (DIBL) and hot-carrier effect.

Journal ArticleDOI
TL;DR: In this paper, a folded-accumulation LDMOS (FALDMOS) was proposed, in which the silicon-substrate surface is trenched to form a folded shape from the channel to the drain electrode and the gate is extended to drain.
Abstract: A new lateral power MOSFET structure [folded-accumulation LDMOS (FALDMOS)] is proposed, in which the silicon-substrate surface is trenched to form a folded shape from the channel to the drain electrode and the gate is extended to the drain. The majority-carrier accumulation layer is formed as the device is in on state due to the extended gate in the drift region whose concentration is higher than that in a conventional LDMOS at the same breakdown voltage (BV), resulting from the additional electric-field modulation, and an extra majority carrier is introduced on the sidewall of the trench, which reduced the on-resistance of the drift region further. In addition, the channel density is doubled because of trenching the folded channel, which reduced the channel on-resistance. It indicates by simulation that the specific on-resistance of 4.6 mOmegamiddotmm2 with a BV of 27.4 V in FALDMOS is lower than that of the previously reported lowest one.

Patent
17 Apr 2009
TL;DR: In this paper, the authors describe a tunneling transistor with a gate stack including a metallic gate electrode and a gate dielectric, and a junction that is substantially parallel to an interface between the metallic gate electrodes and the gate dieslectric.
Abstract: Several embodiments of a tunneling transistor are disclosed. In one embodiment, a tunneling transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a gate stack including a metallic gate electrode and a gate dielectric, and a tunneling junction that is substantially parallel to an interface between the metallic gate electrode and the gate dielectric. As a result of the tunneling junction that is substantially parallel with the interface between the metallic gate electrode and the gate dielectric, an on-current of the tunneling transistor is substantially improved as compared to that of a conventional tunneling transistor. In another embodiment, a tunneling transistor includes a heterostructure that reduces a turn-on voltage of the tunneling transistor.

Journal ArticleDOI
TL;DR: In this paper, the authors show that the current at the onset of saturation in a metaloxide-semiconductor field effect transistor (MOSFET) is limited by the drain velocity that increases toward its saturation value with the increase in the drain voltage.
Abstract: The current at the onset of saturation in a metal-oxide-semiconductor field-effect transistor (MOSFET) is shown to be limited by the drain velocity that increases toward its saturation value with the increase in the drain voltage. The saturation of velocity crops up as randomly oriented velocity vectors in equilibrium realign themselves to become unidirectional in the presence of an extremely high electric field. The intrinsic velocity, the ultimate saturation velocity, is the function of carrier concentration and temperature, consistent with the predictions of the ballistic transport. The presence of a quantum emission either by emission of a phonon or photon lowers the saturation velocity below its intrinsic value. Channel conduction beyond the quasisaturation point enhances due to the drain velocity overshoot as a result of enhanced drain electric field as drain voltage is increased. The excellent agreement with experimental data on an 80 nm channel, without using any artificial parameters, confirms the value of ballistic transport in a high electric field.

Journal ArticleDOI
TL;DR: In this paper, the authors presented the unique features exhibited by a proposed structure of coaxially gated carbon nanotube field effect transistor (CNTFET) with doped source and drain extensions using the self-consistent and atomistic scale simulations, within the nonequilibrium Green's function formalism.
Abstract: In this paper, we present the unique features exhibited by a proposed structure of coaxially gated carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions using the self-consistent and atomistic scale simulations, within the nonequilibrium Green's function formalism. In this novel CNTFET structure, three adjacent metal cylindrical gates are used, where two side metal gates with lower workfunction than the main gate as an extension of the source/drain on either side of the main metal gate are biased, independent of the main gate, to create virtual extensions to the source and the drain and also to provide an effective electrical screen for the channel region from the drain voltage variations. We demonstrate that the proposed structure of CNTFET shows improvement in device performance focusing on leakage current, on-off current ratio, and voltage gain. In addition, the investigation of short-channel effects for the proposed structure shows improved drain-induced barrier lowering, hot-carrier effect, and subthreshold swing, all of which can affect the reliability of CMOS devices.

Journal ArticleDOI
TL;DR: A CMOS-compatible self-aligning process for the large-scale-integration of high-performance nanowire field effect transistors with well-saturated drain currents, steep subthreshold slopes at low drain voltage and a large on/off current ratio.
Abstract: In this work we present a CMOS-compatible self-aligning process for the large-scale-integration of high-performance nanowire field effect transistors with well-saturated drain currents, steep subthreshold slopes at low drain voltage and a large on/off current ratio (>10(7)). The subthreshold swing is as small as 45 mV/dec, which is substantially beyond the thermodynamic limit (60 mV/dec) of conventional planar MOSFETs. These excellent device characteristics are achieved by using a clean integration process and a device structure that allows effective gate-channel-source coupling to tune the source/drain Schottky barriers at the nanoscale.

Patent
Masaki Aoki1
05 Mar 2009
TL;DR: In this paper, when a write voltage is applied to the resistance memory element via the second transistor to switch the memory element from a low resistance state to a high resistance state, a voltage is controlled to be a value which is not less than reset voltage and less than a set voltage.
Abstract: In the semiconductor memory device having a resistance memory element, a first transistor having a drain terminal connected to one end of the resistance memory element and a source terminal connected to a ground voltage, and a second transistor having source terminal connected to the resistance memory element, when a write voltage is applied to the resistance memory element via the second transistor to switch the resistance memory element from a low resistance state to a high resistance state, a voltage is controlled to be a value which is not less than a reset voltage and less than a set voltage by applying to a gate terminal of the second transistor a voltage which is not less than a total of the reset voltage and a threshold voltage of the second transistor and is less than a total of the set voltage and the threshold voltage.

Journal ArticleDOI
TL;DR: In this article, the degradation caused by applying gate voltage and drain voltage stress was investigated and the authors concluded that two degradation mechanisms occur under gate and drain voltages under different conditions.
Abstract: Degradation of Ga2O3–In2O3–ZnO (GIZO) thin-film transistors (TFTs), which are promising for driving circuits of next-generation displays, was studied. We evaluated degradation caused by applying gate voltage and drain voltage stress. A parallel shift of the transfer curve was observed under gate voltage stress. The amount of threshold voltage shift when applying gate and drain voltage stress was smaller than that in the case of only gate voltage stress. Joule heating caused by the drain current was observed. We reproduced this degradation of transfer curve change by device simulation. When we assumed the trap level as the density of state (DOS) model and increased two kinds of trap density, we obtained properties that show the same trends as the experimental results. We concluded that two degradation mechanisms occur under gate and drain voltage stress conditions. # 2009 The Japan Society of Applied Physics

Patent
Andres Bryant1, Edward J. Nowak1
21 Sep 2009
TL;DR: In this paper, an integrated circuit device having series-connected planar or non-planar field effect transistors (FETs) with integrated voltage equalization and a method of forming the device is presented.
Abstract: Disclosed is an integrated circuit device having series-connected planar or non-planar field effect transistors (FETs) with integrated voltage equalization and a method of forming the device. The series-connected FETs comprise gates positioned along a semiconductor body to define the channel regions for the series-connected FETs. Source/drain regions are located within the semiconductor body on opposing sides of the channel regions such that each portion of the semiconductor body between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor. Integrated voltage equalization is achieved through a conformal conductive layer having a desired resistance and positioned over the series-connected FETs such that it is electrically isolated from the gates, but in contact with the source/drain regions within the semiconductor body.

Journal ArticleDOI
TL;DR: In this article, a model based on multiple trapping and thermal release was developed to account for the sub-threshold regime of the transistors, which assumes that charge transport is limited by a single level of shallow traps located close to the transport band edge.
Abstract: Organic field-effect transistors were fabricated with vapor-grown rubrene single crystals in a staggered top-contact configuration. The devices were electrically characterized by measuring the transfer curves at low drain voltage. In parallel to these measurements, a model is developed to account for the subthreshold regime of the transistors. The model is based on the multiple trapping and thermal release concept, which assumes that charge transport is limited by a single level of shallow traps located close to the transport band edge. It is shown that the threshold voltage no longer establishes at the transition between the depletion and accumulation regimes. Instead, the threshold corresponds to the point at which traps are filled. This results in a subthreshold current that varies linearly with gate voltage. Moreover, the subthreshold current at low drain voltages increases with drain voltage. These finding are in good agreement with the experimental data.

Journal ArticleDOI
TL;DR: In this article, an explicit charge-based compact model for lightly doped FinFETs is proposed, which takes short-channel effects, subthreshold slope degradation, drain-induced barrier lowering, drain saturation voltage with velocity saturation, channel length modulation, and quantum mechanical effects into account.
Abstract: An explicit charge-based compact model for lightly doped FinFETs is proposed. This design-oriented model is valid and continuous in all operating regimes (subthreshold, linear, and saturation) for channel lengths (L) down to 25 nm, Fin widths (W Si) down to 3 nm, and Fin heights (H Si) down to 50 nm with a single set of parameters. It takes short-channel effects, subthreshold slope degradation, drain-induced barrier lowering, drain saturation voltage with velocity saturation, channel length modulation, and quantum mechanical effects into account.

Patent
25 Jun 2009
TL;DR: In this article, the inverter includes a driving transistor and a loading transistor having channel regions with different thicknesses, where the driving transistor region is thinner than the channel region of the load transistor.
Abstract: The inverter includes a driving transistor and a loading transistor having channel regions with different thicknesses. The channel region of the driving transistor may be thinner than the channel region of the load transistor. A channel layer of the driving transistor may have a recessed region between a source and a drain which contact both ends of the channel layer. The driving transistor may be an enhancement mode transistor and the load transistor may be a depletion mode transistor.

Patent
17 Jun 2009
TL;DR: A low voltage transient voltage suppressing (TVS) device supported by a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) is proposed in this paper.
Abstract: A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer thereon The TVS device further includes a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate wherein the drain region interfaces with the body region constituting a junction diode and the drain region encompassed in the body region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal The gate may be shorted to the drain for configuring the BS-MOSFET transistor into a two terminal device with a gate-to-source voltage equal to a drain-to-source voltage The drain/collector/cathode terminal disposed on top of the trench gate turns on the BS-MOSFET upon application of a threshold voltage of the BS-MOSFET thus triggering the bipolar transistor for clamping and suppressing a transient voltage substantially near a threshold voltage of the BS-MOSFET

Patent
18 Dec 2009
TL;DR: In this article, a global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time.
Abstract: A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.

Patent
Suman Datta1, Justin K. Brask1, Been-Yih Jin1, Jack T. Kavalieros1, Mantu K. Hudait1 
14 Aug 2009
TL;DR: Enhancement mode transistors are described in this article where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel, and the drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.
Abstract: Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.

Proceedings ArticleDOI
27 May 2009
TL;DR: In this article, the authors focus on the determination of the valid device domain for the use of the top of the barrier (ToB) model to simulate quantum transport in nanowire MOSFETs in the ballistic regime.
Abstract: This work focuses on the determination of the valid device domain for the use of the Top of the barrier (ToB) model to simulate quantum transport in nanowire MOSFETs in the ballistic regime. The presence of a proper Source/Drain barrier in the device is an important criterion for the applicability of the model. Long channel devices can be accurately modeled under low and high drain bias with DIBL adjustment. Keywords-component; nanowires; top of the barrier; MOSFET; ballistic transport model; DIBL; tunneling current; top-of-the- barrier; subthreshold- slope; Tight-Binding;Short channel effects .

Journal ArticleDOI
Xiaoyun Wei1, Guofu Niu1, Ying Li1, Ming-Ta Yang2, Stewart S. Taylor3 
TL;DR: In this article, the authors presented measured, simulated and calculated third-order intercept point (IP3) on a 90-nm RF CMOS technology, which is actually at a V GS lower than zero K 3g m point.
Abstract: This paper presents measured, simulated and calculated third-order intercept point (IP3) on a 90-nm RF CMOS technology. The IP3 sweet spot is actually at a V GS lower than zero K 3g m point. This V GS difference is attributed to the nonlinear output conductance and the cross terms using a Volterra-series-based IP3 expression. The impact of these nonlinearities is quantified using simulated I-V and device small-signal parameters extracted from S -parameter simulation. The scaling factors of the nonlinearities causes a decrease of IP3 sweet spot J DS as device size increases. The IP3 expression can accurately predicts the device size dependence of IP3 sweet spot. The frequency dependence of IP3 is determined by the small signal capacitance. Thus, the frequency dependence is very weak and negligible for a small device. For a large device, not only gate-source capacitance and drain-bulk capacitance, but also gate-drain capacitance are important. To determine the value of IP3 accurately, a more complete equivalent circuit of the MOS transistor must be used in Volterra-series analysis. The V DS dependence of the IP3 sweet spot V GS is primarily due to drain induced barrier lowering.