Showing papers on "Drain-induced barrier lowering published in 2010"

A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET - Two-dimensional Analytical Modeling and Simulation

Abstract: In this paper, we present the unique features exhibited by modified asymmetrical Double Gate (DG) silicon on insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the front gate consists of two materials. The resulting modified structure, Dual Material Double Gate (DMDG) SOI MOSFET, exhibits significantly reduced short channel effects when compared with the DG SOI MOSFET. Short channel effects in this structure have been studied by developing an analytical model. The model includes the calculation of the surface potential, electric field, threshold voltage and drain induced barrier lowering. A model for the drain current, transconductance, drain conductance and voltage gain is also discussed. It is seen that short channel effects in this structure are suppressed because of the perceivable step in the surface potential profile, which screens the drain potential. We further demonstrate that the proposed DMDG structure provides a simultaneous increase in the transconductance and a decrease in the drain conductance when compared with the DG structure. The results predicted by the model are compared with those obtained by two-dimensional simulation to verify the accuracy of the proposed analytical model.

Multi-gate semiconductor device with self-aligned epitaxial source and drain

Abstract: A channel strained multi-gate transistor with low parasitic resistance and method of manufacturing the same. A gate stack may be formed over a semiconductor fin having a gate-coupled sidewall height (Hsi), an etch rate controlling dopant may be implanted into a source/drain region of the semiconductor fin adjacent to the gate stack and into a source/drain extension region of the semiconductor fin. The doped fin region may be etched to remove a thickness of the semiconductor fin equal to at least Hsi proximate a channel region and form a source/drain extension undercut. A material may be grown on the exposed semiconductor substrate to form a regrown source/drain fin region filling the source/drain extension undercut region.

High-Performance Integrated Dual-Gate AlGaN/GaN Enhancement-Mode Transistor

Abstract: In this letter, we present a new AlGaN/GaN enhancement-mode (E-mode) transistor based on a dual-gate structure. The dual gate allows the transistor to combine an E-mode behavior with low on-resistance and very high breakdown voltage. The device utilizes an integrated gate structure with a short gate controlling the threshold voltage and a long gate supporting the high-voltage drop from the drain. Using this new dual-gate technology, AlGaN/GaN E-mode transistors grown on a Si substrate have demonstrated a high threshold voltage of 2.9 V with a maximum drain current of 434 mA/mm and a specific on-resistance of 4.3 m Ω·cm2 at a breakdown voltage of 643 V.

Electronic circuit, method of driving the same, electronic device, electro-optical device, electronic apparatus, and method of driving the electronic device

Abstract: A gate of a driving transistor is set to a offset level corresponding to the threshold of the driving transistor by an initializing current flowing between a source and a drain of the driving transistor or a compensating transistor for the driving transistor. A conduction state of the driving transistor is set according to a gate voltage of the gate of the driving transistor that corresponds to a data signal and the threshold of the driving transistor. A current of which a level corresponds to the conduction state and of which the direction is opposite to the direction of the initializing current flows through driving transistor.

Integrated circuit memory devices having selection transistors with nonuniform threshold voltage characteristics

Abstract: Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

Method for driving semiconductor device

Abstract: To provide a method for driving a semiconductor device, by which influence of variation in threshold voltage and mobility of transistors can be reduced. The semiconductor device includes an n-channel transistor, a switch for controlling electrical connection between a gate and a first terminal of the transistor, a capacitor electrically connected between the gate and a second terminal of the transistor, and a display element. The method has a first period for holding the sum of a voltage corresponding to the threshold voltage of the transistor and an image signal voltage in the capacitor; a second period for turning on the switch so that electric charge held in the capacitor in accordance with the sum of the image signal voltage and the threshold voltage is discharged through the transistor; and a third period for supplying a current to the display element through the transistor after the second period.

III-Nitride Devices and Circuits

Abstract: A Ill-nitride based high electron mobility transistor is described that has a gate-connected grounded field plate The gate-connected grounded field plate device can minimize the Miller capacitance effect The transistor can be formed as a high voltage depletion mode tiansistor and can be used in combination with a low voltage enhancement-mode transistor to form an assembly that operates as a single high voltage enhancement mode transistor.

Transistor with enhanced channel charge inducing material layer and threshold voltage control

Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.

Tunnel Field-Effect Transistor with Narrow Band-Gap Channel and Strong Gate Coupling

Abstract: A semiconductor device and the methods of forming the same are provided. The semiconductor device includes a low energy band-gap layer comprising a semiconductor material; a gate dielectric on the low energy band-gap layer; a gate electrode over the gate dielectric; a first source/drain region adjacent the gate dielectric, wherein the first source/drain region is of a first conductivity type; and a second source/drain region adjacent the gate dielectric. The second source/drain region is of a second conductivity type opposite the first conductivity type. The low energy band-gap layer is located between the first and the second source/drain regions.

Tunnel field effect transistor with improved subthreshold swing

Abstract: The present invention provides a tunnel field effect transistor (TFET) device comprising at least following segments: - A highly doped drain region (3), - A lowly doped up to undoped channel region (2) being in contact with said drain region (3), the channel region (2) having a longitudinal direction, - A highly doped source region (1) in contact with said channel (2) region, the contact between the source region (1) and the channel region (2) forming a source-channel interface (12), - A gate dielectric (10) and a gate electrode (9) covering along the longitudinal direction at least part of the source (1) and channel (2) regions, said gate electrode (9) being situated onto said gate dielectric (10), not extending beyond said gate dielectric (10), wherein the effective gate dielectric thickness t gd,eff of the gate dielectric (10) is smaller at the source-channel interface (12) than above the channel (2) at a distance from the source-channel interface (12), the increase in effective gate dielectric thickness t gd,eff being obtained by means of at least changing the physical thickness t gd of the gate dielectric (10).

A two-dimensional model for the potential distribution and threshold voltage of short-channel double-gate metal-oxide-semiconductor field-effect transistors with a vertical Gaussian-like doping profile

Abstract: A two-dimensional (2D) model for the threshold voltage of the short-channel double-gate (DG) metal-oxide-semiconductor field-effect transistors (MOSFETs) with a vertical Gaussian-like doping profile is proposed in this paper. The evanescent mode analysis has been used to solve the 2D Poisson’s equation to obtain the channel potential function of the device. The minimum surface potential has been used to model the threshold voltage of the DG MOSFETs. Threshold voltage variations against channel length for different device parameters have been demonstrated. The validity of the proposed model is shown by comparing the results with the numerical simulation data obtained by using the commercially available ATLAS™, a 2D device simulator from SILVACO.

Intrinsic Gain in Self-Aligned Polysilicon Source-Gated Transistors

Abstract: Thin-film self-aligned source-gated transistors (SGTs) have been made in polysilicon. The very high output impedance of this type of transistor makes it suited to analog circuits. Intrinsic voltage gains of greater than 1000 have been measured at particular drain voltages. The drain voltage dependence of the gain is explained based on the device physics of the SGT and the fact that a pinchoff occurs at both the source and the drain. The results obtained from these devices, which are far from optimal, suggest that, with a proper design, the SGT is well suited to a wide range of analog applications.

Forming abrupt source drain metal gate transistors

Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.

Multiple Vt Field-Effect Transistor Devices

Abstract: Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.

A shift register circuit having threshold voltage compensation

Abstract: A shift register circuit comprises a plurality of stages, each stage being for providing an output signal to an output load and comprising a pull up transistor for pulling the output signal up to a high voltage rail and a pull down transistor for pulling the output signal down to a low voltage rail. Each stage comprises a circuit for sampling the threshold voltage of at least one of the pull up and pull down transistors and for adding the sampled threshold voltage to a control voltage offset, to provide a threshold-voltage-compensated signal for controlling the gate of the at least one of the pull up and pull down transistors. This provides threshold voltage sampling, in particular for the thin film transistor whose threshold voltage drift must be compensated (for example the pull-down thin film transistor).

Schottky-Ohmic Drain AlGaN/GaN Normally Off HEMT With Reverse Drain Blocking Capability

Abstract: In this letter, we propose an AlGaN/GaN normally off high-electron mobility transistor (HEMT) with reverse drain blocking capability. The device features a Schottky-ohmic drain electrode in which a Schottky-controlled normally off channel is inserted between the gate and the conventional ohmic drain contact. Under negative reverse drain bias, the normally off channel provides an energy barrier that effectively blocks the reverse current conduction while contributing only 0.55 V onset voltage in the forward-biased on state. In a device with a gate-drain distance of 9 m, a reverse blocking voltage of -321 V was obtained at VGS = 0 V, comparable with the forward blocking voltage of 351 V; at VGS = 3 V, the reverse blocking voltage was -276 V. The new HEMT also exhibits no degradation in drain saturation current and does not need extra photomask or process steps to fabricate. When forward biased at VGS = 3 V , the proposed device achieved a specific on resistance of 1.97 mΩ · m2.

Gate-First Integration of Tunable Work Function Metal Gates of Different Thicknesses Into High- $k$ /Metal Gates CMOS FinFETs for Multi- $V_{\rm Th}$ Engineering

Abstract: Gate-first integration of tunable work function metal gates of different thicknesses (3-20 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ~40 mV/V), nearly symmetric VTh, low Tinv (~1.4 nm), and high Ion (~780 ?A/?m) for N/PMOS without any intentional strain enhancement.

Transistors with isolation regions

Abstract: A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a plurality of channel access regions in the semiconductor material on either side of the gate, a channel in the semiconductor material having an effective width in the gate region and in the channel access regions, and an isolation region in the gate region. The isolation region serves to reduce the effective width of the channel in the gate region without substantially reducing the effective width of the channel in the access regions. Alternatively, the isolation region can be configured to collect holes that are generated in the transistor device. The isolation region may simultaneously achieve both of these functions.

Voltage regulator circuit

Abstract: A voltage regulator circuit includes a transistor and a capacitor. The transistor includes a gate, a source, and a drain, a first signal is inputted to one of the source and the drain, a second signal which is a clock signal is inputted to the gate, an oxide semiconductor layer is used for a channel formation layer, and an off-state current is less than or equal to 10 aA/μm. The capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a high power source voltage and a low power source voltage are alternately applied to the second electrode.

High Voltage Word Line Driver

Abstract: A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.

Transistors, methods of manufacturing a transistor and electronic devices including a transistor

Abstract: Transistors, methods of manufacturing a transistor, and electronic devices including a transistor are provided, the transistor includes a channel layer, a source and a drain respectively contacting opposing ends of the channel layer, a gate corresponding to the channel layer, a gate insulating layer between the channel layer and the gate, and a first passivation layer and a second passivation layer sequentially disposed on the gate insulating layer. The first passivation layer covers the source, the drain, the gate, the gate insulating layer and the channel layer. The second passivation layer includes fluorine (F).

Process variation study of Ground Plane SOI MOSFET

Abstract: In this paper, the variations of the main characteristics in three SOI device structures due to channel length and thin-film thickness variations are investigated. The structures are studied in a 32nm technology and include SOI-GPS (Ground-Plane in Substrate), SOI-GPB (Ground-Plane in BOX), and SOI-WGP (Without Ground Plane). For this study, we assume normal distributions for the channel length and thin-film thickness of the transistors and then obtain the distributions for the threshold voltage, leakage, DIBL coefficient, and subthreshold swing. The results show that the GPS structure is more resistant against the variations when compared to the other two structures.

A Binary Tunnel Field Effect Transistor with a Steep Sub-threshold Swing and Increased ON Current

Abstract: A variant tunnel field effect transistor structure called the binary tunnel field effect transistor (BTFET) for low voltage and near ideal switching characteristics is proposed. The BTFET relies on a binary tunneling distance (HIGH and LOW) for its operation to achieve a steep sub-threshold swing with a predicted range of 5 mV/dec. The transition of tunneling distance from HIGH to LOW state is a step-function of the gate voltage with the threshold voltage as a transition voltage. BTFET has a high on-current due to the high gate electric field and a large tunneling cross section area. An orientation dependent non-local band-to-band tunneling model was used to analyze the DC characteristics of the device.

Pulsed- IV Pulsed-RF Cold-FET Parasitic Extraction of Biased AlGaN/GaN HEMTs Using Large Signal Network Analyzer

Abstract: A new pulsed-IV pulsed-RF cold field-effect transistor (cold-FET) technique is presented to extract the parasitics of AlGaN/GaN HEMTs under various quiescent dc-biasing points. The measurement system implemented with a large signal network analyzer applies the technique of multiple recording to acquire pulsed-RF small-signal S-parameters with no loss of dynamic range as the pulse duty cycle decreases. These cold-FET measurements are performed on unpassivated and silicon nitride (SiN) passivated devices by turning the device off for 1 ?s with a 1% duty cycle to analyze the impact of slow thermal and trapping effects on the device parasitics. The parasitic fringe capacitances extracted are found to be bias independent, except for the gate to drain capacitance in devices without SiN passivation. In unpassivated devices, the drain parasitic resistance is found to rapidly increase with increasing drain bias at negative gate to source voltages. On the contrary, in devices with SiN passivation, the dependence of the resistance with the drain bias voltage is much less significant. A simple physical model is used to fit the functional dependence of the 2-D electron gas (2DEG) concentration upon the gate-to-source and gate-to-drain voltages, which is then proposed for fitting the measured data. The analysis indicates that the variation of the resistance with bias voltage in the device studied with SiN passivation and also for the unpassivated device at V GS=0 V is well accounted for by the reduction of the mobility with increased temperature due to self-heating, whereas for the device studied without SiN passivation, the increase of the drain resistance with drain voltages at negative gate bias principally arises from the decrease of the 2DEG population in a narrow region near the gate contact. An equivalent circuit is also introduced to explain the decrease of the source and drain parasitic inductances with increasing drain voltages at large negative gate bias, which is observed in unpassivated devices.

High voltage mos transistor

Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS) and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. One portion of the second well surrounds the source and the other portion of the second well extends laterally from the first portion in the first well.

Mosfet with gate pull-down

Abstract: A pull-down MOSFET (110) is coupled between a drain and gate of a MOSFET main switch transistor (102) in a switching type DC-to-DC power converter. A gate of the pull-down MOSFET (110) is coupled to the drain of the main switch transistor (102) by a capacitor 118 and is connected to a source of the main switch transistor (102) by a resistor (120). The pull-down MOSFET (110) is operated by capacitive coupling to the voltage drop across the main switch transistor (102) and can be used to hold the gate of the main switch transistor (102) at or near its source potential to avoid or reduce unintentional turn-on of the main switch transistor (102) by the Miller effect.

Asymmetric channel MOSFET

Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

Reference voltage generator having a two transistor design

Abstract: An improved voltage reference generator is provided. The voltage reference generator comprises: a first transistor having a gate electrode biased to place the first transistor in a weak inversion mode; and a second transistor connected in series with said first transistor and having a gate electrode biased to place the second transistor in a weak inversion mode, where the threshold voltage of the first transistor is smaller than the threshold voltage of the second transistor and the gate electrode of the second transistor is electrically coupled to a drain electrode of the second transistor and the source electrode of the first transistor to form an output for a reference voltage.