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Showing papers on "Drain-induced barrier lowering published in 2012"


Journal ArticleDOI
TL;DR: In this paper, a single-crystal gallium oxide (Ga2O3) metal-semiconductor field effect transistors (MESFETs) with a gate length of 4 μm and a source-drain spacing of 20 μm is presented.
Abstract: We report a demonstration of single-crystal gallium oxide (Ga2O3) metal-semiconductor field-effect transistors (MESFETs). A Sn-doped Ga2O3 layer was grown on a semi-insulating β-Ga2O3 (010) substrate by molecular-beam epitaxy. We fabricated a circular MESFET with a gate length of 4 μm and a source–drain spacing of 20 μm. The device showed an ideal transistor action represented by the drain current modulation due to the gate voltage (VGS) swing. A complete drain current pinch-off characteristic was also obtained for VGS < −20 V, and the three-terminal off-state breakdown voltage was over 250 V. A low drain leakage current of 3 μA at the off-state led to a high on/off drain current ratio of about 10 000. These device characteristics obtained at the early stage indicate the great potential of Ga2O3-based electrical devices for future power device applications.

1,273 citations


Journal ArticleDOI
TL;DR: The fabrication of a low-voltage field-effect transistor with a vertical vacuum channel etched into a metal-oxide-semiconductor substrate is reported, which could enable a new class of low-power, high-speed transistors.
Abstract: High-speed electronic devices rely on short carrier transport times, which are usually achieved by decreasing the channel length and/or increasing the carrier velocity. Ideally, the carriers enter into a ballistic transport regime in which they are not scattered. However, it is difficult to achieve ballistic transport in a solid-state medium because the high electric fields used to increase the carrier velocity also increase scattering. Vacuum is an ideal medium for ballistic transport, but vacuum electronic devices commonly suffer from low emission currents and high operating voltages. Here, we report the fabrication of a low-voltage field-effect transistor with a vertical vacuum channel (channel length of ~20 nm) etched into a metal-oxide-semiconductor substrate. We measure a transconductance of 20 nS µm(-1), an on/off ratio of 500 and a turn-on gate voltage of 0.5 V under ambient conditions. Coulombic repulsion in the two-dimensional electron system at the interface between the oxide and the metal or the semiconductor reduces the energy barrier to electron emission, leading to a high emission current density (~1 × 10(5) A cm(-2)) under a bias of only 1 V. The emission of two-dimensional electron systems into vacuum channels could enable a new class of low-power, high-speed transistors.

143 citations


Journal ArticleDOI
TL;DR: In this article, the junctionless tri-gate transistor with a gate length of 20-nm showed excellent electrical characteristics with a high Ion/Ioff ratio (>106), good sub-threshold slope (∼79mV/dec), and low drain-induced barrier lowering.
Abstract: We have fabricated n-channel junctionless nanowire transistors with gate lengths in the range of 20–250 nm, and have compared their electrical performances with conventional inversion-mode nanowire transistors. The junctionless tri-gate transistor with a gate length of 20 nm showed excellent electrical characteristics with a high Ion/Ioff ratio (>106), good subthreshold slope (∼79 mV/dec), and low drain-induced barrier lowering (∼10 mV/V). The simpler fabrication process without junction formation results in improved short-channel characteristics compared to the inversion-mode devices, and also makes the junctionless nanowire transistor a promising candidate for sub 22-nm technology nodes.

138 citations


Journal ArticleDOI
TL;DR: An analytical threshold voltage model for short-channel junctionless (JL) double-gate MOSFETs is developed for the first time in this article, which explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage degradation.
Abstract: Based on the bulk conduction mode of the quasi-2-D scaling theory, an analytical threshold voltage model for short-channel junctionless (JL) double-gate MOSFETs is developed for the first time. The model explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage degradation. The model can also be extended to modeling accumulation/inversion operation mode for JL/junction-based double-gate MOSFETs. The model is verified by 2-D device simulations and can be easily used to explore the threshold voltage behavior of the JL double-gate MOSFETs due to its simple formula and computational efficiency.

129 citations


Journal ArticleDOI
TL;DR: In this article, a surface-potential-based model for the symmetric long-channel junctionless double-gate MOSFET was developed, where the relationship between surface potential and gate voltage were derived from some effective approximations to Poisson's equation for deep depletion, partial depletion, and accumulation conditions.
Abstract: A surface-potential-based model is developed for the symmetric long-channel junctionless double-gate MOSFET. The relationships between surface potential and gate voltage are derived from some effective approximations to Poisson's equation for deep depletion, partial depletion, and accumulation conditions. Then, the Pao-Sah integral is carried out to obtain the drain current. It is shown that the model is in good agreement with numerical simulations from subthreshold to saturation region. Finally, we discuss the strengths and limitations (i.e., threshold voltage shifts) of the JLFET, which has been recently proposed as a promising candidate for the JFET.

90 citations


Journal ArticleDOI
TL;DR: Based on the quasi-2D scaling equation, a new threshold voltage model for short-channel junctionless (JL) cylindrical surrounding gate (JLCSG) MOSFETs is developed in this paper.
Abstract: Based on the quasi-2-D scaling equation, a new threshold voltage model for short-channel junctionless (JL) cylindrical surrounding gate (JLCSG) MOSFETs is developed. The model explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage behavior. The model can also be extendable to its counterpart of junction-based cylindrical surrounding gate (JBCSG) MOSFETs. The model is verified by its calculated results matching well with those of the 3-D numerical simulator and can be easily used to explore the threshold voltage characteristics of JLCSG MOSFETs for its simple formula and computational efficiency.

73 citations


Patent
12 Nov 2012
TL;DR: In this paper, a memory circuit including a memory element to which writing can be performed with a small current and a low voltage, i.e., low power consumption, and provides a nonvolatile storage device that can easily reduce a chip size by using this memory circuit.
Abstract: The present invention provides a memory circuit including a memory element to which writing can be performed with a small current and a low voltage, i.e., low power consumption, and provides a non-volatile storage device that can easily reduce a chip size by using this memory circuit. A memory element 1 is a memory transistor having a transistor structure including a source electrode 14 , a drain electrode 15 , a gate electrode 11 , and, a source region, a drain region, and a channel region made of a metal oxide semiconductor layer 13 . The resistance property between the source and the drain shows a low resistance, and the memory transistor is changed to have an ohmic resistance property, regardless of a voltage application state of the gate electrode, by allowing a writing current with a density not less than a predetermined value to flow in the channel region to generate Joule heat. The memory circuit stores information between a state indicating the ohmic resistance property after the writing and a state indicating a current-voltage characteristic as a transistor depending upon the voltage application state to the gate electrode before the writing.

70 citations


Patent
17 Dec 2012
TL;DR: In this article, the authors proposed a method for forming a CMOS integrated circuit device, the method including; providing a semiconductor substrate, forming a gate layer overlying the semiconductor substrategies, patterning the gate layer to form NMOS and PMOS gate structures including edges; forming a first dielectric layer overlaying the gate structures to protect the edges; etching a first source region and a first drain region adjacent to the PMOS germanium gate structure using the first masking layer as a protective layer for the first region adjacent the NMOS gate structure
Abstract: A method for forming a CMOS integrated circuit device, the method including; providing a semiconductor substrate, forming a gate layer overlying the semiconductor substrate, patterning the gate layer to form NMOS and PMOS gate structures including edges; forming a first dielectric layer overlying the NMOS and PMOS gate structures to protect the NMOS and PMOS gate structures including the edges, forming a first masking layer overlying a first region adjacent the NMOS gate structure; etching a first source region and a first drain region adjacent to the PMOS gate structure using the first masking layer as a protective layer for the first region adjacent the NMOS gate structure, and depositing a silicon germanium material into the first source and drain regions to cause the channel region between the first source and drain regions of the PMOS gate structure to be strained in a compressive mode.

65 citations


Journal ArticleDOI
TL;DR: In this paper, a hybrid Schottky-ohmic drain structure is proposed for AlGaN/GaN high-electron-mobility transistors on a Si substrate, which forms a Γ-shaped electrode to smooth the electric field distribution at the drain side, which improves the breakdown voltage and lowers the leakage current.
Abstract: In this letter, a hybrid Schottky-ohmic drain structure is proposed for AlGaN/GaN high-electron-mobility transistors on a Si substrate. Without additional photomasks and extra process steps, the hybrid drain design forms a Γ-shaped electrode to smooth the electric field distribution at the drain side, which improves the breakdown voltage and lowers the leakage current. In addition, the hybrid drain provides an auxiliary current path and decreases the on-resistance, in contrast to the devices with a pure Schottky drain. Compared with the conventional ohmic drain devices, the breakdown voltage could be improved up to 64.9%, and the leakage current is suppressed by one order of magnitude without degradation of the specific on-resistance.

54 citations


Patent
26 Apr 2012
TL;DR: In this article, the authors describe a Fin Field Effect Transistor (FinFET) which includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a source/drain region, and an additional semiconductor region between the source and drain regions.
Abstract: A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.

51 citations


Journal ArticleDOI
TL;DR: In this paper, the influence of the passivation thickness on the device characteristics of InAlGaN/GaN high-electron-mobility transistors with a gate length between sub-30 and 70 nm was studied.
Abstract: This letter studies the influence of the passivation thickness on the device characteristics of InAlGaN/GaN high-electron-mobility transistors with a gate length between sub-30 and 70 nm. As the Al2O3 passivation thickness increases, the current collapse in 80-μs pulsed-I -V measurements decreases from 30% to 13%, while dc characteristics are almost unchanged with the exception of increasing drain-induced barrier lowering. The thicker passivation increases the fringing gate capacitance, which can be about 30% of the total gate capacitance in the devices with a gate length below 35 nm. This capacitance results in a significant drop of current-gain cutoff frequency (fT), and its effect is more important in the shorter gate length devices.

Patent
05 Oct 2012
TL;DR: In this article, the depletion-mode transistor has a higher breakdown voltage than the enhancement mode transistor, and the depletion mode transistor can be electrically connected to a source of the enhancement modes transistor.
Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.

Journal ArticleDOI
TL;DR: In this article, a self-aligned top-gate amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors with phosphorus-doped source/drain regions are developed.
Abstract: Self-aligned top-gate amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with phosphorusdoped source/drain regions are developed in this letter. The resulting a-IGZO TFT exhibits high thermal stability and good electrical performance, including field-effect mobility of 5 cm2/V · s, a threshold voltage of 5.6 V, a subthreshold swing of 0.5 V/dec, and an on/off current ratio of 6 × 107. With scaling down of the channel length, good characteristics are also obtained with a small shift in the threshold voltage and no degradation in the subthreshold swing.

Patent
13 Jun 2012
TL;DR: In this article, a gate driver for a power transistor comprising a first charging path operatively connected between a first voltage supply and a gate terminal of the power transistor for charging the gate terminal to a first gate voltage.
Abstract: The present invention relates to a gate driver for a power transistor comprising a first charging path operatively connected between a first voltage supply and a gate terminal of the power transistor for charging the gate terminal to a first gate voltage. A second charging path is connectable between the gate terminal of the power transistor and a second supply voltage to charge the gate terminal from the first gate voltage to a second gate voltage larger or higher than the first gate voltage. A voltage of the second voltage supply is higher than a voltage of the first voltage supply.

Patent
10 May 2012
TL;DR: In this article, a back gate metal layer was placed below the active region of the channel to reduce the electric field strength from the gate to the drain of a HEMT.
Abstract: The present invention reduces the dynamic on resistance in the channel layer of a GaN device by etching a void in the nucleation and buffer layers between the gate and the drain This void and the underside of the device substrate may be plated to form a back gate metal layer The present invention increases the device breakdown voltage by reducing the electric field strength from the gate to the drain of a HEMT This electric field strength is reduced by placing a back gate metal layer below the active region of the channel The back gate metal layer may be in electrical contact with the source or drain

Journal ArticleDOI
TL;DR: The atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer.
Abstract: The junctionless nanowire transistor is a promising alternative for a new generation of nanotransistors. In this letter the atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer. The etching process was developed and optimized in the present work compared to our previous works. The output, transfer characteristics and drain conductance of both structures were compared. The trend for both devices found to be the same but differences in subthreshold swing, ‘on/off’ ratio, and threshold voltage were observed. The devices are ‘on’ state when performing as the pinch off devices. The positive gate voltage shows pinch off effect, while the negative gate voltage was unable to make a significant effect on drain current. The charge transmission in devices is also investigated in simple model according to a junctionless transistor principal.

Proceedings ArticleDOI
06 Mar 2012
TL;DR: In this article, the authors derived an analytical two-dimensional model to calculate the potential within ultra-scaled junctionless double-gate MOSFETs valid in sub-threshold region.
Abstract: We derived an analytical two-dimensional model to calculate the potential within ultra-scaled junctionless double-gate MOSFETs (DG MOSFETs) valid in subthreshold region. We propose an approach how to calculate the threshold voltage of such devices, and present our first results. Compared to conventional MOSFETs, the proposed junctionless transistor has no pn-junctions. Its type of doping in the channel region is the same as in the source/drain. The device is turned on by creating a conducting channel in the center of the silicon, and turned off by depleting it. To ensure a safe switching behavior, the investigation of the subthreshold region is therefore important. A Comparison of our model with numerical simulation results confirms its validity for ultra-scaled devices having a channel length about 22 nm.

Journal ArticleDOI
TL;DR: In this paper, the combination of the Dynamic Threshold (DT) voltage technique with a nonplanar structure is experimentally studied in triple-gate FinFETs, and the drain current, transconductance, resistance, threshold voltage, subthreshold swing and Drain Induced Barrier Lowering (DIBL) is analyzed in the DT mode and the standard biasing configuration.
Abstract: In this paper, the combination of the Dynamic Threshold (DT) voltage technique with a non-planar structure is experimentally studied in triple-gate FinFETs. The drain current, transconductance, resistance, threshold voltage, subthreshold swing and Drain Induced Barrier Lowering (DIBL) will be analyzed in the DT mode and the standard biasing configuration. Moreover, for the first time, the important figures of merit for the analog performance such as transconductance-over-drain current, output conductance, Early voltage and intrinsic voltage gain will be studied experimentally and through three-dimensional (3-D) numerical simulations for different channel doping concentrations in triple-gate DTMOS FinFETs. The results indicate that the DTMOS FinFETs always yield superior characteristics and larger transistor efficiency. In addition, DTMOS devices with a high channel doping concentration exhibit much better analog performance compared to the normal operation mode, which is desirable for high performance low-power/low-voltage applications.

Patent
Jeffrey B. Johnson1, Ramachandran Muralidhar1, P. Oldiges1, Viorel Ontalus1, Kai Xiu1 
16 Jan 2012
TL;DR: In this article, a method for forming a stressed channel field effect transistor (FET) with source/drain buffers is proposed, which includes etching cavities in a substrate on either side of a gate stack located on the substrate.
Abstract: A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.

Journal Article
TL;DR: The impact of channel engineering on double gate MOSFET is investigated by using different channel doping and it is observed in the results that the threshold voltage can be changed by changing the channel doping.
Abstract: Double gate MOSFET is one of the most promising and leading contender for nano regime devices. In this paper we investigate the impact of channel engineering on double gate MOSFET by using different channel doping. Sentaurus TCAD simulator is used to analyze the channel engineering of double gate MOSFET. It is observed in the results that we can change the threshold voltage by changing the channel doping. The impact of channel engineering also observed on performance parameters of the DG-MOSFET such as on current, off current, drain induced barrier lowering, subthreshold slope and carrier mobility. Thus, an optimized value of the channel doping will be projected for future reference in context of leakage power. Thus channel engineering will play an important role in optimizing the device parameters. General Terms Integrated Circuit, VLSI, MOS Device Modeling.

Journal ArticleDOI
TL;DR: In this paper, the Schottky barrier at both source and drain contacts was analyzed in fully printed p-channel OTFTs with Au source-drain contacts and the effects of field-induced barrier lowering.

Journal ArticleDOI
TL;DR: In this article, the authors proposed a novel nanoscale fully depleted silicon-on-insulator metal-oxide-semiconductor field effect transistor (SOI-MOSFET) with modified current mechanism for leakage current reduction.

Patent
15 May 2012
TL;DR: In this article, a field effect transistor (FET) with a gate contact on a barrier layer over the channel layer and a field plate comprising a sloped sidewall in the space between the gate contact and the drain contact is considered.
Abstract: A field effect transistor (FET) having a source contact to a channel layer, a drain contact to the channel layer, and a gate contact on a barrier layer over the channel layer, the (FET) including a dielectric layer on the barrier layer between the source contact and the drain contact and over the gate contact, and a field plate on the dielectric layer, the field plate connected to the source contact and extending over a space between the gate contact and the drain contact and the field plate comprising a sloped sidewall in the space between the gate contact and the drain contact.

Journal ArticleDOI
TL;DR: In this article, a pseudo-2D model applying Gauss's law in the cylindrical channel depletion region for undoped or lightly doped surrounding gate (SRG) silicon metal oxide semiconductor field effect transistor (MOSFETs) working in sub-threshold regime is presented.
Abstract: For the first time, a pseudo-two-dimensional (2D) approach is extended from a rectangular device structure to a cylindrical one. A pseudo-2D model applying Gauss's law in the cylindrical channel depletion region for undoped or lightly doped surrounding gate (SRG) silicon metal oxide semiconductor field effect transistor (MOSFETs) working in subthreshold regime is presented. From this pseudo-2D analysis, electrostatic potentials, current characteristics, the threshold voltage roll-off, the drain-induced barrier lowering and the subthreshold swing are explicitly modelled. The obtained analytical model has been extended to develop a model for transconductance-to-drain current ratio (g m/I d) in weak inversion regime. Analogue figures of merit of SRG MOSFETs are studied, including transconductance efficiency g m/I d, intrinsic gain and output resistance. The trends related to their variations along the downscaling of dimension are provided. In order to validate our model, the modelled expressions are compared...

Journal ArticleDOI
TL;DR: In this article, a carbon nanotube field effect transistor with symmetric graded double halo channel (GDH-CNTFET) is presented for suppressing band to band tunneling and improving the device performance.

Journal ArticleDOI
TL;DR: In this article, a gate-all-around MOSFET (GAA SNFET) was proposed for high-performance silicon-nanowire gate-and-pin-type ICs.
Abstract: We demonstrate high-performance silicon-nanowire gate-all-around MOSFETs (GAA SNWFETs) fabricated on bulk Si by a novel top-down complementary MOS-compatible method. The fabricated nand p-type GAA SNWFETs of ~50-nm gate length and of ~6-nm diameter show superior device performance, i.e., driving capability of 2.6 × 103/2.9 × 103 μA/μm at |VD| = |VG - Vt| = 1.0 V, Ion/Ioff ratio as high as 5 × 108/109, and excellent short-channel-effect immunity with subthreshold slope of 67/64 mV/dec and drain-induced barrier lowering of 6 mV/V, respectively. GAA SNWFETs and FinFETs fabricated on bulk Si were also compared by the investigation of both experiments and Technology Computer Aided Design simulation. The superiority of GAA SNWFETs over FinFETs is evidenced in this paper.

Journal ArticleDOI
TL;DR: In this article, the impact of different Buried OXide (BOX) configurations on the scaling of extremely thin SOI devices (ET-FDSOI) to sub-32nm nodes using a Multi-Subband Ensemble Monte Carlo simulator (MS-EMC).
Abstract: This work presents a thorough study of the impact of different Buried OXide (BOX) configurations on the scaling of extremely thin SOI devices (ET-FDSOI, also known as UTSOI) to sub-32 nm nodes using a Multi-Subband Ensemble Monte Carlo simulator (MS-EMC). Standard thick BOX, ultra thin BOX (UTBOX) and UTBOX with ground plane (UTBOX + GP) solutions have been considered in order to check their influence on Short Channel Effects (SCEs). Simulations show that for channel lengths shorter than 20 nm, silicon thickness thinner than 5 nm are needed to control Drain Induced Barrier Lowering (DIBL) below 100 mV/V. However, thickness variability and mobility reduction could play an important role for so small thickness. Nevertheless, we show that with the appropriate combination of UTBOX and GP it is possible to use thicker Si layers, even for channels shorter than 20 nm, and keeping SCEs under control, i.e., DIBL below 100 mV/V.

Patent
Jun-Youn Kim1, Joong S. Jeon1
02 May 2012
TL;DR: In this article, a CMOS transistor formed using Ge condensation and a method of fabricating the same is presented, provided that a method to fabricate the same can be found.
Abstract: Provided is a CMOS transistor formed using Ge condensation and a method of fabricating the same. The CMOS transistor may include an insulating layer, a silicon layer on the insulating layer and including a p-MOS transistor region and an n-MOS transistor region, a first gate insulating layer and a first gate on a channel region of the p-MOS transistor region, and a second gate insulating layer and a second gate on a channel region of the n-MOS transistor region, wherein a source region and a drain region of the p-MOS transistor region may be tensile-strained due to Ge condensation, and the channel region of the n-MOS transistor region may be tensile-strained due to the Ge condensation.

Patent
28 Mar 2012
TL;DR: In this article, a light emitting device connected in series with a drain of a dual gate transistor, a switching transistor configured to apply a data voltage to a first gate of the dual-gate transistor in response to a scan signal, a capacitor connected between the first gate and the drain of the primary transistor, and a conductor for supplying a control voltage to the second-stage transistor.
Abstract: An apparatus includes a circuit branch electrically connected to a voltage rail and including a light emitting device connected in series with a drain of a dual gate transistor, a switching transistor configured to apply a data voltage to a first gate of the dual gate transistor in response to a scan signal, a capacitor connected between the first gate of the dual gate transistor and the drain of the dual gate transistor, and a conductor for supplying a control voltage to a second gate of the dual gate transistor. A method of operating the circuit is also described.

Journal ArticleDOI
TL;DR: In this article, the authors developed a procedure to include in device simulators the barrier lowering (BL) effects that appear in the drain and source contacts of Schottky barrier MOSFETs.
Abstract: In this paper, we develop a procedure to include in device simulators the barrier lowering (BL) effects that appear in the drain and source contacts of Schottky barrier MOSFETs (SB-MOSFETs). We have checked it reproducing experimental results of 20-nm gate-length SB-MOSFETs with NiSi and epitaxial NiSi2 S/D contacts. We make use of the Wentzel-Kramers-Brillouin (WKB) approximation to get the tunneling probabilities through the lowered barriers along with an appropriate calibration of the effective masses which compensates to a large extent the lack of accuracy of the WKB model when diverting from the “wide barrier” assumption. A vertical discretization of the channel is also included to allow the barrier height dependence on the depth inside the channel. We show that corrected simulations including this effect describe in a very accurate way the behavior of these devices. We also check that the striking experimental observation of tunneling current reduction at very short gate lengths is also obtained, in contrast to the scaling behavior of conventional MOSFETs. We successfully explain this fact invoking the modification of the potential inside the channel, i.e., the overlapping of source and drain potential profiles leads to an increase of its total value even though BL mechanisms tend to decrease it in the vicinity of the contacts.