Showing papers on "Drain-induced barrier lowering published in 2013"

FinFET with bottom SiGe layer in source/drain

Abstract: A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer.

Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime

Abstract: In this paper, we propose an approximate solution to solve the two dimensional potential distribution in ultra-thin body junctionless double gate MOSFET (JL DG MOSFET) operating in the subthreshold regime. Basically, we solved the 2D-Poisson equation along the channel, while assuming a parabolic potential across the silicon thickness, which in turn leads to some explicit relationships of the subthreshold current, subthreshold slope (SS) and drain induced barrier lowering (DIBL). This approach has been assessed with Technology Computer Aided Design (TCAD) simulations, confirming that this represents an interesting solution for further implementation in generic JL DG MOSFETs compact models.

Semianalytical Model of the Subthreshold Current in Short-Channel Junctionless Symmetric Double-Gate Field-Effect Transistors

Abstract: A 2-D semianalytical solution for the electrostatic potential valid for junctionless symmetric double-gate field-effect transistors in subthreshold regime is proposed, which is based on the parabolic approximation for the potential and removes previous limitations. Based on such a solution, a semi-analytical expression for the current is derived. The potential and current models are validated through comparisons with TCAD simulations and are used to evaluate relevant short-channel effect parameters, such as threshold roll-off, drain-induced barrier lowering, and inverse subthreshold slope. The implications of different possible definitions of threshold voltage, either based on the potential in the channel or on a fixed current level, are discussed. Finally, a fully analytical simplification for the current is suggested, which can be used in compact models for circuit simulations.

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Revisited parameter extraction methodology for electrical characterization of junctionless transistors

Abstract: Several electrical parameters characterize device performance, electron transport and doping level in MOS transistors. In this paper, Junctionless Transistors (JLTs) fabricated on (100) silicon on insulator (SOI) wafer with 145 nm thick BOX and 9 nm silicon thickness were considered. Parameter extraction methodologies were revisited in order to account for the unique electrical properties of JLT devices. The deduced parameters, such as threshold voltage, flat-band voltage, drain induced barrier lowering (DIBL), low field mobility and channel doping level, are shown to reveal the specific features of JLT compared to conventional inversion-mode transistors.

A Semi-Floating Gate Transistor for Low-Voltage Ultrafast Memory and Sensing Operation

Abstract: As the semiconductor devices of integrated circuits approach the physical limitations of scaling, alternative transistor and memory designs are needed to achieve improvements in speed, density, and power consumption. We report on a transistor that uses an embedded tunneling field-effect transistor for charging and discharging the semi-floating gate. This transistor operates at low voltages (≤2.0 volts), with a large threshold voltage window of 3.1 volts, and can achieve ultra–high-speed writing operations (on time scales of ~1 nanosecond). A linear dependence of drain current on light intensity was observed when the transistor was exposed to light, so possible applications include image sensing with high density and performance.

Impact of high-k spacer on device performance of a junctionless transistor

Abstract: The impact of spacer dielectric on both sides of gate oxide on the device performance of a symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The digital and analog performance parameters of the device considered in this study are drain current (I D ), ON-state to OFF-state current ratio (I ON /I OFF ), subthreshold slope (SS), drain induced barrier lowering (DIBL), intrinsic gain (G m R O ), output conductance (G D ), transconductance/drain current ratio (G m /I D ) and unity gain cut-off frequency (f T ). The effects of varying the spacer dielectric constant (k sp ) on the electrical characteristics of the device are studied. It is observed that the use of a high-k dielectric as a spacer brings an improvement in the OFF-state current by more than one order of magnitude thereby making the device more scalable. However, the ON-state current is only marginally affected by increasing dielectric constant of spacer. The effects of spacer width (W sp ) on device performance are also studied. ON-state current marginally decreases with spacer width.

Threshold voltage, and 2D potential modeling within short-channel junctionless DG MOSFETs in subthreshold region

Abstract: This report focuses on the development of an analytical two-dimensional model to calculate the potential within ultra-scaled junctionless double-gate MOSFETs (DG MOSFETs), which is valid in the subthreshold regime. From that we derive an expression for calculating the threshold voltage of such devices, and present our first results. Compared to conventional MOSFETs, the proposed junctionless transistor has no pn-junctions. Its type of doping in the channel region is the same as in the source/drain regions. The device is turned on by creating a conducting channel in the center of the silicon film, and turned off by depleting it. To achieve good I on / I off ratios, and to ensure a safe switching behavior, the investigation of the subthreshold region is therefore important. The analytical model is compared with numerical simulation results from TCAD Sentaurus. Its validity is confirmed for long-channel, as well as for ultra-scaled devices having a channel length about 22 nm. Since the junctionless device is still in its infancy, an analytical model, especially for short-channel devices, can provide help to understand its electrostatic characteristics.

UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regime

Abstract: In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) SOI MOSFETs. Based on experimental devices, both n- and p-type GP configurations are considered and compared with standard no-GP substrates. In a standard single-gate (SG) regime, the effect of GP implementation on analog FoM (related to slightly higher body factor and improved gate-to-channel coupling) is negligible. Moreover, p-GP implementation allows higher intrinsic gain at high frequency compared with no-GP and n-GP substrates. Furthermore, we demonstrate that application of an asymmetric double-gate (ADG) (i.e. front-gate to back-gate/substrate connection) regime allows better control of short-channel effects in terms of drain induced barrier lowering, subthreshold slope and threshold voltage control, due to improved gate(s)-to-channel coupling. Application of an ADG mode is shown to enhance analog FoM such as transconductance, drive current and intrinsic gain of UTBB SOI MOSFETs. Finally, simulations predict that improvements of analog FoM provided by ADG mode can be obtained in the whole dynamic operation range. Moreover, ADG mode provides elimination of the high-frequency substrate coupling effects.

Mosfet with recessed channel film and abrupt junctions

Abstract: MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.

Cascoded semiconductor devices

Abstract: The invention provides a cascode transistor circuit with a depletion mode transistor and a switching device. A gate bias circuit is connected between the gate of the depletion mode transistor and the low power line. The gate bias circuit is adapted to compensate the forward voltage of a diode function of the switching device. The depletion mode transistor and the gate bias circuit are formed as part of an integrated circuit.

A simple compact model for long-channel junctionless Double Gate MOSFETs

Abstract: This paper presents a simple explicit compact model for the drain current of long channel symmetrical junctionless Double Gate MOSFETs. Our approach leads to very simple equations compared to other models, while retaining high accuracy and physical consistency. Explicit and analytical solutions are also given. Compared to TCAD simulations, the model gives excellent results in accumulation regime. Although the accuracy decreases in depletion regime for very high doping and semiconductor thicknesses, it still remains very good and it is shown that this issue can be neglected because it can only be seen on devices with both high doping and semiconductor thicknesses, that are unlikely to be used as a real device, because of their negative threshold voltage. Finally, it is shown that the model reproduces the two observed different conduction modes, related to accumulation and depletion regimes and that the effective gate capacitance and threshold voltage are different in those regimes, which explains the change of slope observed in the I d ( V g ) characteristics.

RF Switch Branch Having Improved Linearity

Abstract: Disclosed is a radio frequency (RF) switch branch having a reduced nonlinearity and an associated method for reducing nonlinearity in a RF switch branch. The RF switch branch includes a primary transistor, a first transistor having power terminals electrically connected between a drain node and a body node of the primary transistor, and a second transistor having power terminals electrically connected between the body node and a source node of the primary transistor. The RF switch may further include a body resistor electrically connected between the body node of the primary transistor and ground, and a gate resistor electrically connected between a gate of the primary transistor and a gate voltage source. A gate of each of the first transistor and the second transistor is electrically connected to the gate voltage source such that the first transistor and the second transistor are ON only when the primary transistor is ON.

Threshold Voltage Sensitivity to Metal Gate Work-Function Based Performance Evaluation of Double-Gate n-FinFET Structures for LSTP Technology

Abstract: This paper investigates the threshold voltage sensitivity to metal gate work-function for n-channel double gate fin field-effect transistor (FinFET) structures and evaluates the short channel performance of the device using threshold voltage dependence on metal gate work-function analysis. We carried out the study for a double gate n-channel fin field-effect transistor (n-FinFET) with parameters as per the projection report of International Technology Roadmap for Semiconductors, ITRS-2011 for low standby power (LSTP) 20 nm gate length technology node. In the present study device simulation have been carried out using PADRE simulator from MuGFET, which is based on the drift-diffusion theory. Our results show the accuracy and validity of classical drift-diffusion simulation results for transistor structures with lateral dimensions 10nm and above. The subthreshold behavior of device improves with increased metal gate work-function. The results also show that a higher gate work-function (≥5 eV) can fulfill the tolerable off-current as projected in ITRS 2011 report. The SCE in FinFET can reasonably be controlled and improved by proper adjustment of the metal gate work-function. DIBL is reduced with the increase in gate work function.

On the Origin of Kink Effect in Current–Voltage Characteristics of AlGaN/GaN High Electron Mobility Transistors

Abstract: An explanation for the observed drain current collapse in AlGaN/GaN high electron mobility transistors is presented. The drain current-voltage (I-V) characteristics which show this undesirable behavior have been modeled using the physics-based ATLAS device simulator by Silvaco. A basic theory for the determination of virtual gate length for a three terminal device has been developed and used in the simulation. The simulated I-V characteristics closely match the experimental results. This paper suggests a model based on formation of a high resistance region under the virtual gate in the 2-D electron gas channel. The resistance of this region changes abruptly at a critical lateral electric field due to application of drain-source voltage. This abrupt change has been found to be a function of channel temperature. The dynamic behavior of this high resistance region has been proposed to be the cause of drain current collapse.

Subthreshold analysis of nanoscale FinFETs for ultra low power application using high-k materials

Abstract: Fin Field Effect Transistors (FinFETs) are used for Complementary Metal Oxide Semiconductor applications beyond the 45 nm node of the Semiconductor Industry Association (SIA) roadmap because of their excellent scalability and better immunity to short channel effects. This article examines the impact of high-k dielectrics on FinFETs. The FinFET device performance is analysed for On Current, Off Current, I on/I off ratio, drain induced barrier lowering, electrostatic potential along the channel, electric field along the channel, transconductance, output resistance, intrinsic gain, gate capacitance and transconductance generation factor, by replacing the conventional silicon dioxide gate dielectric material, with various high dielectric constant materials. Nanosize ZrO2 (zirconium-di-oxide) is found out to be the best alternative for SiO2 (silicon-di-oxide). It is also observed that the integration of high-k dielectrics in the devices significantly reduces the short channel effects and leakage current. The s...

N-polar III-nitride transistors

Abstract: An N-polar III-N transistor includes a III-N buffer layer, a first III-N barrier layer, and a III-N channel layer, the III-N channel layer having a gate region and a plurality of access regions on opposite sides of the gate region. The compositional difference between the first III-N barrier layer and the III-N channel layer causes a conductive channel to be induced in the access regions of the III-N channel layer. The transistor also includes a source, a gate, a drain, and a second III-N barrier layer between the gate and the III-N channel layer. The second III-N barrier layer has an N-face proximal to the gate and a group-III face opposite the N-face, and has a larger bandgap than the III-N channel layer. The lattice constant of the first III-N barrier layer is within 0.5% of the lattice constant of the buffer layer.

Ambipolar silicon nanowire field effect transistor

Abstract: This invention describes a novel electronic device consisting of one—or more—vertically stacked gate-all-around silicon nanowire field effect transistor (SNWFET) with two independent gate electrodes. One of the two gate electrodes, acting on the central section of the transistor channel, controls on/off behavior of the channel. The second gate, acting on the regions in proximity to the source and the drain of the transistor, defines the polarity of the devices, i.e. p or n type. The electric field of the second gate acts either at the interface of the nanowire-to-source/drain region or anywhere in close proximity to the depleted region of the SiNW body, modulating the bending of the Schottky barriers at the contacts, eventually screening one type of charge carrier to pass through the channel of the transistor. This is achieved by controlling the majority carriers passing through the transistor channel by regulating the Schottky barrier thicknesses at the source and drain contacts.

Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications

Abstract: In this paper, the authors propose novel metal-oxide-semiconductor field-effect transistor (MOSFET) types featuring additional L-shaped counterdoped areas in the source and/or drain regions of silicon-on-insulator (SOI) MOSFETs to reduce drain-induced barrier lowering (DIBL) through the buried oxide (BOX) layer. The L-shaped region in the drain area shields the BOX layer from penetration by the drain electric field, thereby reducing DIBL in the body region. Simulation of the electrical characteristics of these novel MOSFETs demonstrated more remarkable DIBL suppression and subthreshold slope performance in short-channel regions than in conventional SOI MOSFETs. In addition to this suppression, these novel MOSFETs suppress breakdown voltage more effectively than conventional SOI MOSFETs. The authors concluded that the proposed devices are capable of contributing to the scaling of SOI MOSFETs in ultralarge-scale integration circuits.

An analytical model of threshold voltage for short-channel double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs

Abstract: In this paper, an analytical short-channel threshold voltage model is presented for double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs. The threshold voltage model is based on the "virtual cathode" concept which is determined by the two-dimensional (2D) channel potential of the device. The channel potential has been determined by solving 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed Si1?x Ge x layer. The effects of various device parameters like Ge mole fraction, Si film thickness, SiGe thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been estimated. The validity of the present 2D analytical model is verified by using ATLAS?, a 2D device simulator from Silvaco.

Source/drain extension control for advanced transistors

Abstract: A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×10 19 atoms/cm 3 ′, or alternatively, less than one-quarter the dopant concentration of the source and the drain.

New methodology for drain current local variability characterization using Y function method

Abstract: Y function is well known to overcome the influence of source/drain series resistance (Rsd) in MOSFETs. In this work we present a new methodology for drain current local variability characterization using Y function method. Thus, we show that the study of Y function statistical variability permits the extraction of threshold voltage (VTH) and current gain factor (β) local variability without the influence of Rsd values. We also demonstrate a simple drain current local variability model taking into account the influence of Rsd and its variability in strong inversion regime. This new VTH and β extraction method, and drain current variability model were applied with success to advanced FDSOI and Bulk devices with different dimensions.

Semiconductor device and driving method thereof, and electronic device

Abstract: A driving method of a semiconductor device for compensating variation in threshold voltage and mobility of a transistor is provided. A driving method of a semiconductor device including a transistor and a capacitor electrically connected to a gate of the transistor includes a first period where voltage corresponding to threshold voltage of the transistor is held in the capacitor, a second period where a total voltage of video signal voltage and threshold voltage is held in the capacitor holding the threshold voltage, and a third period where charge held in the capacitor in accordance with the total voltage of the video signal voltage and the threshold voltage in the second period is discharged through the transistor.

A novel graphene nanoribbon field effect transistor for integrated circuit design

Abstract: In this work, we present a novel structure of Graphene NanoRibbon Field-Effect Transistor (GNR FET) to reduce short channel effects. In this structure, two side metal gates with lower work-function than the main gate are used in a conventional double-gate (DG) GNR FET topology to provide virtual extensions to source/drain regions while these are biased constant, independent of the main gate. The proposed GNR FET structure improves drain-induced barrier lowering (DIBL), which can reduce the short-channel effects (SCE) in device performance such as on/off current ratio, off-state current and subthreshold slope to make it a more suitable configuration than the normal GNR FET for digital integrated circuit design.

Multi-Threshold Voltage FETs

Abstract: A multi-threshold voltage (V t ) field-effect transistor (FET) formed through strain engineering is provided. An embodiment integrated circuit device includes a first transistor including a first channel region over a first buffer, the first channel region formed from a III-V semiconductor material and a second transistor including a second channel region over a second buffer, the second channel region formed from the III-V semiconductor material, the second buffer and the first buffer having a lattice mismatch. A first strain introduced by a lattice mismatch between the III-V semiconductor material and the first buffer is different than a second strain introduced by a lattice mismatch between the III-V semiconductor material and the second buffer. Therefore, the threshold voltage of the first transistor is different than the threshold voltage of the second transistor.

Performance limits of transition metal dichalcogenide (MX2) nanotube surround gate ballistic field effect transistors

Abstract: We theoretically analyze the performance of transition metal dichalcogenide (MX2) single wall nanotube (SWNT) surround gate MOSFET, in the 10 nm technology node. We consider semiconducting armchair (n, n) SWNT of MoS2, MoSe2, WS2, and WSe2 for our study. The material properties of the nanotubes are evaluated from the density functional theory, and the ballistic device characteristics are obtained by self-consistently solving the Poisson-Schrodinger equation under the non-equilibrium Green's function formalism. Simulated ON currents are in the range of 61–76 μA for 4.5 nm diameter MX2 tubes, with peak transconductance ∼175–218 μS and ON/OFF ratio ∼0.6 × 105–0.8 × 105. The subthreshold slope is ∼62.22 mV/decade and a nominal drain induced barrier lowering of ∼12–15 mV/V is observed for the devices. The tungsten dichalcogenide nanotubes offer superior device output characteristics compared to the molybdenum dichalcogenide nanotubes, with WSe2 showing the best performance. Studying SWNT diameters of 2.5–5 nm, it is found that increase in diameter provides smaller carrier effective mass and 4%–6% higher ON currents. Using mean free path calculation to project the quasi-ballistic currents, 62%–75% reduction from ballistic values in drain current in long channel lengths of 100, 200 nm is observed.

High-voltage semiconductor switch and method for switching high voltages

Abstract: A high voltage semiconductor switch includes a first field-effect transistor having a source, a drain and a gate, and being adapted for switching a voltage at a rated high-voltage level, the first field-effect transistor being a normally-off enhancement-mode transistor, a second field-effect transistor having a source, a drain and a gate, connected in series to the first field-effect transistor, the second field-effect transistor being a normally-on depletion-mode transistor; and a control unit connected to the drain of the first field-effect transistor and to the gate of the second field-effect transistor and being operable for blocking the second field-effect transistor if a drain-source voltage across the first field-effect transistor exceeds the rated high-voltage level.