Showing papers on "Drain-induced barrier lowering published in 2017"

Enhancement-mode Ga2O3 MOSFETs with Si-ion-implanted source and drain

Abstract: Enhancement-mode β-Ga2O3 metal–oxide–semiconductor field-effect transistors with low series resistance were achieved by Si-ion implantation doping of the source/drain contacts and access regions. An unintentionally doped Ga2O3 channel with low background carrier concentration that was fully depleted at a gate bias of 0 V gave rise to a positive threshold voltage without additional constraints on the channel dimensions or device architecture. Transistors with a channel length of 4 µm delivered a maximum drain current density (I DS) of 1.4 mA/mm and an I DS on/off ratio near 106. Nonidealities associated with the Al2O3 gate dielectric as well as their impact on enhancement-mode device performance are discussed.

Ferroelectric transistor model based on self-consistent solution of 2D Poisson's, non-equilibrium Green's function and multi-domain Landau Khalatnikov equations

Abstract: We present a physics-based model for ferroelectric/negative capacitance transistors (FEFETs/ NCFETs) without an inter-layer metal between ferroelectric and dielectric in the gate stack The model self-consistently solves 2D Poisson's equation, non-equilibrium Green's function (NEGF) based charge and transport equations, and multi-domain Landau Khalatnikov (LK) equations with the domain interaction term The proposed simulation framework captures the variation of ferroelectric (FE) polarization (P) along the gate length due to non-uniform electric field (E) along the channel To calibrate the LK equations, we fabricate and characterize 10nm HZO films Based on the calibrated model, we analyze the gate/drain voltage dependence of P distribution in the FE and its effect on the channel potential and current-voltage characteristics Our results highlight the importance of larger domain interaction to boost the benefits of FEFETs with subthreshold swing (SS) as small as ∼50mV/decade achieved at room temperature As domain interaction increases, the characteristics of FEFETs without inter-layer metal (SS, negative drain induced barrier lowering (DIBL), negative output conductance) approach those of FEFETs with inter-layer metal

Nanoscale MOSFET Modeling: Part 1: The Simplified EKV Model for the Design of Low-Power Analog Circuits

Abstract: This article presents the s implified charge-based Enz-Krummenacher-Vittoz (EKV) [11] metal-oxide-semiconductor field-effect transistor (MOSFET) model and shows that it can be used for advanced complementary metal-oxide-semiconductor (CMOS) processes despite its very few parameters. The concept of an inversion coefficient (IC) is first introduced as an essential design parameter that replaces the overdrive voltage VG-VT0 and spans the entire range of operating points from weak via moderate to strong inversion (SI), including the effect of velocity saturation (VS). The simplified model in saturation is then presented and validated for different 40- and 28-nm bulk CMOS processes. A very simple expression of the normalized transconductance in saturation, valid from weak to SI and requiring only the VS parameter mc, is described. The normalized transconductance efficiency Gm/ID, which is a key figure-of-merit (FoM) for the design of low-power analog circuits, is then derived as a function of IC including the effect of VS. It is then successfully validated from weak to SI with data measured on a 40-nm and two 28-nm bulk CMOS processes. It is then shown that the normalized output conductance Gds/ID follows a similar dependence with IC than the normalized Gm/ID characteristic but with different parameters accounting for drain induced barrier lowering (DIBL). The methodology for extracting the few parameters from the measured ID-VG and ID-VD characteristics is then detailed. Finally, it is shown that the simplified EKV model can also be used for a fully depleted silicon on insulator (FDSOI) and Fin-FET 28-nm processes.

Liquid-solid Dual-gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing

Abstract: Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid–liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the “sensing channel” can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchy...

2-D Analytical Threshold Voltage Model for Dielectric Pocket Double-Gate Junctionless FETs by Considering Source/Drain Depletion Effect

Abstract: This paper proposes an analytical threshold voltage model for the dielectric pocket double gate (DP-DG) junctionless FETs (JLFETs). The channel potential function has been obtained by solving 2-D Poisson’s equation using an evanescent mode analysis with suitable boundary conditions. The potential function has then been used for modeling the threshold voltage to investigate the effects of the DP thickness and length on the short-channel effects of the structure. The effects of source and drain depletion regions have been included for improving the accuracy of the model. The model results of DP-DG JLFETs have been compared with the simulation data obtained from the 2-D TCAD ATLAS device simulator.

3-D analytical modeling of high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual-material bottom gate for suppressing short channel effects

Abstract: This paper presents a detailed study of the response of a new structure namely, high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual material bottom gate, towards various short channel effects, namely, drain-induced barrier lowering, threshold voltage roll-off, hot carrier effect and subthreshold swing Based on the 3-D Poisson’s equation, the surface potential of the device is calculated along with its threshold voltage and electric field The impact on the device performance due to the variation of different device parameters is also studied The analytical results are verified using the simulated results obtained from ATLAS, a 3-D device simulator from SILVACO

Physics-Based Generalized Threshold Voltage Model of Multiple Material Gate Tunneling FET Structure

Abstract: A generalized 2-D analytical model of gate threshold voltage for multiple material gate Tunneling FET (TFET) structures is derived. The model can also be used for calculating threshold voltage of a single metal gate TFET. Surface potential model of a triple material double gate TFET has been developed by applying Gauss's law in the device. From the potential model, physics-based model of gate threshold voltage has been derived by exploring the transition between linear to quasi-exponential dependence of drain current on applied gate bias. The model includes the effect of gate and drain bias, gate material workfunction, oxide thickness, silicon film thickness, gate dielectric, and other device parameters. The accuracy of the proposed model is verified by comparing the results predicted by the proposed model to the results of the numerical model developed in Silvaco, Atlas.

A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects

Abstract: In this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.

Amended Electric Field Distribution: A Reliable Technique for Electrical Performance Improvement in Nano scale SOI MOSFETs

Abstract: To achieve reliable transistors, we propose a new silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET) with an amended electric field in the channel for improved electrical and thermal performance, with an emphasis on current leakage improvement. The amended electric field leads to lower electric field crowding and thereby we assume enhanced reliability, leakage current, gate-induced drain leakage (GIDL), and electron temperature. To modify the electric field distribution, an additional rectangular metal region (RMR) is utilized in the buried oxide of the SOI MOSFET. The location and dimensions of the RMR have been carefully optimized to achieve the best results. The electrical, thermal, and radiofrequency characteristics of the proposed structure were analyzed using two-dimensional (2-D) numerical simulations and compared with the characteristics of the conventional, fully depleted SOI MOSFET (C-SOI). Also, critical short-channel effects (SCEs) such as threshold voltage, drain-induced barrier lowering (DIBL), subthreshold slope degradation, hot-carrier effect, GIDL, and leakage power consumption are improved. According to the results obtained, the proposed nano SOI MOSFET is a reliable device, especially for use in low-power and high-temperature applications.

2-D analytical modeling for electrostatic potential and threshold voltage of a dual work function gate Schottky barrier MOSFET

Abstract: A two-dimensional analytical model for the surface potential and threshold voltage of a dual work function Schottky barrier (SB) MOSFET is presented. The developed model considers the effects of the varying gate metal work function, gate and drain voltages, and different doping concentrations, gate dielectric permittivity, and silicon thickness. For solving the electrostatic potential of the SB-MOSFET by using Poisson’s equation with appropriate boundary conditions, parabolic approximation has been considered. The proposed device has also incorporated the effect of barrier height lowering at the metal/semiconductor contacts. The results of our modeled surface potential and the threshold voltage, match with technology computer aided design simulations.

Schottky-MOS Hybrid Anode AlGaN/GaN Lateral Field-Effect Rectifier With Low Onset Voltage and Improved Breakdown Voltage

Abstract: For devices with a 15 micron anode-to-cathode distance, nearly 1.5 times increase in the blocking (breakdown) voltage (from 692 to 1030 V) has been achieved by replacing the alloyed Ohmic contact at the anode electrode of the conventional MOS gated hybrid-anode lateral field-effect rectifier (CMLFER) with a low barrier Schottky contact. The new Schottky-MOS hybrid-anode lateral field-effect rectifier is found to offer comparable low onset voltage ( ${V}_{{\textbf {ON}}}$ of 0.68±0.13 versus 0.65±0.11 V for CMLFER) independent of the anode-to- cathode distance. The immunity of the punch through caused by drain induced barrier lowering effect is obtained through the low barrier Schottky contact in anode, which is believed to be responsible for the reduction in the leakage current, and the improvement of rectifier breakdown voltage.

Trilayer TMDC Heterostructures for MOSFETs and Nanobiosensors

Abstract: Two dimensional materials such as transition metal dichalcogenides (TMDC) and their bi-layer/tri-layer heterostructures have become the focus of intense research and investigation in recent years due to their promising applications in electronics and optoelectronics. In this work, we have explored device level performance of trilayer TMDC heterostructure (MoS2/MX2/MoS2; M = Mo or, W and X = S or, Se) metal oxide semiconductor field effect transistors (MOSFETs) in the quantum ballistic regime. Our simulation shows that device ‘on’ current can be improved by inserting a WS2 monolayer between two MoS2 monolayers. Application of biaxial tensile strain reveals a reduction in drain current which can be attributed to the lowering of carrier effective mass with increased tensile strain. In addition, it is found that gate underlap geometry improves electrostatic device performance by improving sub-threshold swing. However, increase in channel resistance reduces drain current. Besides exploring the prospect of these materials in device performance, novel trilayer TMDC heterostructure double gate field effect transistors (FETs) are proposed for sensing Nano biomolecules as well as for pH sensing. Bottom gate operation ensures these FETs operating beyond Nernst limit of 59 mV/pH. Simulation results found in this work reveal that scaling of bottom gate oxide results in better sensitivity while top oxide scaling exhibits an opposite trend. It is also found that, for identical operating conditions, proposed TMDC FET pH sensors show super-Nernst sensitivity indicating these materials as potential candidates in implementing such sensor. Besides pH sensing, all these materials show high sensitivity in the sub-threshold region as a channel material in nanobiosensor while MoS2/WS2/MoS2 FET shows the least sensitivity among them.

Leakage current conduction in metal gate junctionless nanowire transistors

Abstract: In this paper, the experimental off-state drain leakage current behavior is systematically explored in n- and p-channel junctionless nanowire transistors with HfSiON/TiN/p + -polysilicon gate stack. The analysis of the drain leakage current is based on experimental data of the gate leakage current. It has been shown that the off-state drain leakage current in n-channel devices is negligible, whereas in p-channel devices it is significant and dramatically increases with drain voltage. The overall results indicate that the off-state drain leakage current in p-channel devices is mainly due to trap-assisted Fowler-Nordheim tunneling of electrons through the gate oxide of electrons from the metal gate to the silicon layer near the drain region.

Controlling ambipolarity with improved RF performance by drain/gate work function engineering and using high $$\kappa $$ κ dielectric material in electrically doped TFET: proposal and optimization

Abstract: This article proposes a novel device structure of electrically doped tunnel FET with drain/gate work function engineering by using hetero-dielectric material for the suppression of ambipolar behavior with improved DC and RF characteristics. For this, a P–I–N type structure was formed over an intrinsic silicon wafer by applying negative and positive voltages to create source and drain regions, respectively. Formation of source and drain regions by the concept of electrical doping is useful for reduction of random doping fluctuations and fabrication complexity. For suppression of ambipolar behaviour, the drain electrode is split into two different metal work functions ( $$\phi _\mathrm{DE1}$$ < $$\phi _\mathrm{DE2}$$ ), which alters the carrier concentration and increases the tunneling barrier at the drain/channel interface. Consequently, the proposed modification in terms of dual work functionality at the drain terminal offers better performance in terms of suppression of negative conductance (ambipolar current) and parasitic capacitances. However, the presence of dual work functionality at the drain electrode causes degradation in ON-state current and RF figures of merit. To resolve these problems, the control gate electrode is further split into two different work functions and uses hetero gate dielectric material, where the gate work function near the source/channel interface is greater than the gate work function near the drain/channel interface. It assists tunneling of carriers at the source/channel junction and improves ON-state current with RF performance. Apart from this, the use of hetero gate dielectric material provides further enhancement in DC and high frequency behaviour of the device.

A unified analytical drain current model for Double-Gate Junctionless Field-Effect Transistors including short channel effects

Abstract: In this paper, a unified analytical model for the drain current of a symmetric Double-Gate Junctionless Field-Effect Transistor (DG-JLFET) is presented. The operation of the device has been classified into four modes: subthreshold, semi-depleted, accumulation, and hybrid; with the main focus of this work being on the accumulation mode, which has not been dealt with in detail so far in the literature. A physics-based model, using a simplified one-dimensional approach, has been developed for this mode, and it has been successfully integrated with the model for the hybrid mode. It also includes the effect of carrier mobility degradation due to the transverse electric field, which was hitherto missing in the earlier models reported in the literature. The piece-wise models have been unified using suitable interpolation functions. In addition, the model includes two most important short-channel effects pertaining to DG-JLFETs, namely the Drain Induced Barrier Lowering (DIBL) and the Subthreshold Swing (SS) degradation. The model is completely analytical, and is thus computationally highly efficient. The results of our model have shown an excellent match with those obtained from TCAD simulations for both long- and short-channel devices, as well as with the experimental data reported in the literature.

Drain Extended Tunnel FET—A Novel Power Transistor for RF and Switching Applications

Abstract: For the first time, a novel drain-extended tunnel FET (DeTFET) device is disclosed in this paper, while addressing the need for high-voltage/high-power devices for system-on-chip and automotive applications in beyond FinFET technology nodes. Operation of the proposed DeTFET device is presented with physics of band-to-band tunneling and associated carrier injection. Device’s intrinsic (dc/switching), analog, and RF performance is compared with the state-of-the-art drain-extended nMOS (DeNMOS) device. The proposed device for 11 V breakdown voltage offers $15\times $ better subthreshold slope, $8\times $ lower off-state leakage, $2\times $ higher ON current, and absence of channel length modulation and drain induced barrier lowering, while keeping $2.5\times $ lower threshold voltage. This results into significantly better ON resistance for a range of gate voltages, higher transconductance, orders of magnitude higher intrinsic transistor gain, and better RF characteristics, when compared with the DeNMOS device. Finally, device design guidelines are presented and scalability, without affecting breakdown voltage, of the proposed device is compared with the DeNMOS device.

Modeling and simulation of enhancement mode p-GaN Gate AlGaN/GaN HEMT for RF circuit switch applications

Abstract: An enhancement mode p-GaN gate AlGaN/GaN HEMT is proposed and a physics based virtual source charge model with Landauer approach for electron transport has been developed using Verilog-A and simulated using Cadence Spectre, in order to predict device characteristics such as threshold voltage, drain current and gate capacitance. The drain current model incorporates important physical effects such as velocity saturation, short channel effects like DIBL (drain induced barrier lowering), channel length modulation (CLM), and mobility degradation due to self-heating. The predicted I d - V ds , I d - V gs , and C - V characteristics show an excellent agreement with the experimental data for both drain current and capacitance which validate the model. The developed model was then utilized to design and simulate a single-pole single-throw (SPST) RF switch.

Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET

Abstract: Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio ( ), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for device simulation. Simulation result shows that fin shape has great impact on FinFET performance and triangular fin shape leads to reduction in leakage current and SCEs. Comparative analysis of simulation results has been investigated to observe the impact of process parameters on the performance of designed FinFET.

Effect of high- k dielectric on the performance of Si, InAs and CNT FET

Abstract: The important issue of selection of gate dielectrics to reduce short channel effects (SCEs) is presented along with the study of different channel materials in transistors. A comparative study of performance was carried out of silicon dioxide (SiO2), aluminium oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O3) and titanium dioxide (TiO2) as gate dielectrics for Si double gate field-effect transistor (FET), Si gate all around (GAA) nanowire FET (NWFET), indium arsenide GAA NWFET and carbon nanotube (CNT) FETs within non-equilibrium Green's function formalism. Simulated results show that TiO2 is better gate dielectric as compared with SiO2, Al2O3, HfO2 and La2O3, with near ideal subthreshold swing (60 mV/decade), lower I off, improved drain-induced barrier lowering and high transconductance (gm ). Also, the gate capacitance (C g), cut-off frequency (f T) and switching time (τ) improve with the high-k dielectric materials. Furthermore, the study of different channel material shows that CNT has better SCEs, smaller C g with τ ranging from 13.5 to 12.5 fs suitable for digital applications and f T of about 7–9 THz.

Downscaling Metal—Oxide Thin-Film Transistors to Sub-50 nm in an Exquisite Film-Profile Engineering Approach

Abstract: We report an exquisite, film-profile-engineering approach for producing nanometer-scale channel-length (L) ZnO thin-film transistors (TFTs). The scheme is based on a unique laminated structure in conjunction with a well-designed etching process for building a slender, suspending bridge that shadows the subsequent deposition of pivotal thin films of ZnO and gate oxide as well as simultaneously defines L of the TFTs. With the approach, we have ingeniously downscaled L of ZnO TFTs to as short as 10 nm. The experimental ZnO TFTs of L = 50 and 30 nm, respectively, exhibit excellent performance in terms of high on/off current ratio of $7.9 \times 10^{\mathrm {\mathbf {7}}}$ and $4.2 \times 10^{\mathrm {\mathbf {7}}}$ , superior subthreshold swing of 92 and 95 mV/decade, and small drain induced barrier lowering of 0.1 and 0.29 V/V. Remarkably the nanometer-scale ZnO TFTs possess excellent device uniformity. Furthermore, the precise control over the geometrical sizes for the channel length enables the fabrication of ultrashort ZnO TFTs of L as short as 10 nm with reasonable gate transfer characteristics.