Showing papers on "Drain-induced barrier lowering published in 2019"

Improving the electrical characteristics of nanoscale triple-gate junctionless FinFET using gate oxide engineering

Abstract: This paper is about the compared performance investigation of various structures of Hetero-Dielectric (HD) triple-gate FinFETs with different gate oxides in terms of Double Hetero Gate Oxide (DHGO), Triple Hetero Gate Oxide (THGO) and Quadruple Hetero Gate Oxide (QHGO) to produce lower leakage current, higher Ion/Ioff ratio, higher gm/gd and also lower Drain Induced Barrier Lowering (DIBL) than those of a conventional triple-gate FinFET. Among all of them, the best results are explored for the DHGO FinFET structure. In DHGO FinFET structure, a high-κ dielectric (κ = 22) is used on the top oxide to increase the gate control and a low-k dielectric (κ = 3.9) is used over silicon body owing to the compatibility of lattice constant of SiO2 and silicon. Mode-space drift-diffusion (DD_MS) model coupled with Schrodinger equation has been utilized in order to analyze the proposed and conventional structures in three dimensional (3D) simulation domain. Interestingly, by decreasing the thickness of the oxide layer and increasing the permittivity coefficient, the leakage current decreases, thus increasing the Ion/Ioff ratio. The DHGO FinFET structure is found to exhibit higher Ion/Ioff, lower DIBL and higher gm/gd ratio, thus proving performance superiority over the other conventional junctionless FinFET and also MOSFETs.

Effect of strain in silicon nanotube FET devices for low power applications

Abstract: In this paper, we have presented an analysis on the performance of a strained silicon channel in silicon nanotube FET (Si-NTFET) device. Si-NTFET devices have tube-shaped channel region and because of this conduction in the channel can be controlled in two ways from outside the tube and from inside (from hollow side) the tube which results in better control over the short channel effects (SCEs). Bi-axial strain induced into the device by the inclusion of silicon-–germanium layer in between the channel. Three-dimensional simulations of the structure are carried out using ATLAS TCAD simulator and the model is calibrated with respect to previously published experimental data. The transfer characteristics, drain induced barrier lowering (DIBL), threshold voltage, I on and I off , subthreshold swing of the Si-NTFET and strained Si-NTFET devices are investigated. It is seen that in strained Si-NTFET, the drive capability and inversion charge density is much higher compared to that of Si-NTFET. Evaluation of electrical performances confirms that the DIBL and other SCEs are either reduced or remains the same. However, the use of strained Si-NTFET is more suited for high speed and low power applications.

Shallow Extension Engineered Dual Material Surrounding Gate (SEE-DM-SG) MOSFET for improved gate leakages, analysis of circuit and noise performance

Abstract: The leakages in off state, particularly Gate Induced Drain Leakage (GIDL) has been addressed and reduced by proposing a Shallow Extension Engineered Dual Material Surrounding Gate (SEE-DM-SG) MOSFET. The shallow extensions create an insulating layer, which acts as a diffusion stopper and thereby suppresses the off state leakages. It is done by comparing the off-state performance of SEE-DM-SG MOSFET with Dual Metal Surrounding Gate (DM-SG) MOSFET and Surrounding Gate (SG) MOSFET. GIDL current is being reduced to an order of 10−12 A. Drain Induced Barrier Lowering (DIBL) has been curtailed to a greater extent in SEE-DM-SG MOSFET when compared with DM-SG MOSFET and SG MOSFET. GIDL has been extensively investigated for different drain voltages and temperatures; in order to study their impact on it. It was so found that GIDL was minimal for SEE-DM-SG MOSFET under different bias and temperature conditions. Arrhenius plot has also been plotted and deeply investigated as it instigates the GIDL activation energy (EA). It has been so found that SEE-DM-SG MOSFET poses higher EA and thereby suggests minimal BTBT (Band To Band Tunneling). So as to enhance the device applicability for low noise amplifier, the noise performance of SEE-DM-SG MOSFET has also been deeply investigated. Noise conductance (NC) and Noise Figure (NF) have been significantly curtailed in SEE-DM-SG MOSFET over DM-SG and SG MOSFET. A CMOS inverter has also been designed using SEE-DM-SG MOSFET and the output characteristics have also been compared for the aforesaid device architectures and higher Noise Margin has been observed in SEE-DM-SG MOSFET, making it more immune to noise.

On the Physical Mechanism of Transient Negative Capacitance Effect in Deep Subthreshold Region

Abstract: We have investigated the physical mechanism of steep subthreshold slope (SS) in ferroelectric FET (FeFET) based on a dynamic ferroelectric (FE) model without traversing the negative capacitance (NC) region of the S-shaped polarization-voltage predicted by Landau theory. The dynamic FE model is applied to an FE-dielectric (FE-DE) series capacitor as well as FeFET after calibration and verification by transient measurement of an FE-HfO2 capacitor. By investigating current through the FE-DE series capacitor and the gate capacitor of FeFET, we find that incomplete screening of spontaneous polarization charge results in transient NC and sub-60 mV/dec SS. Also, it should be noted that, for FeFET, small depletion layer capacitance has an important role to cause strong depolarization effect and thus steep SS. Moreover, reverse drain induced barrier lowering happens even with this FE model. The model presented in this paper provides a reasonable interpretation for the previously reported steep SS of NC FETs.

Influence of the Threshold Voltage Hysteresis and the Drain Induced Barrier Lowering on the Dynamic Transfer Characteristic of SiC Power MOSFETs

Abstract: This paper focuses on dynamic transfer characteristics of SiC MOSFETs, which are derived from the actual switching operation and are different from the usual static characteristics. A new approach to measure the parasitic common source elements is shown, using a non-harmful short circuit pulse. This is important for the correction of the measured gate source voltage, especially in packages without Kelvin source. The resulting transfer characteristics show the threshold voltage hysteresis of SiC MOSFETs and additionally the interaction with the drain induced barrier lowering (DIBL) effect. Finally, the effect of different off-state times on the transfer characteristics and the turn-on process is shown.

Subthreshold Characteristic Analysis and Models for Tri-Gate SOI MOSFET s Using Substrate Bias Induced Effects

Abstract: This paper proposes the substrate bias voltage dependent subthreshold models of channel potential, threshold voltage, current, drain induced barrier lowering, and subthreshold swing for tri-gate silicon-on-insulator (SOI) MOSFET s (TG- MOSFET s). The substrate induced surface potential effect has also been included in the derived models. A quasi-three-dimensional (3-D) approach has been used to derive the minimum of channel potential, which is later used to derive models of threshold voltage, current, drain induced barrier lowering, and swing. The analytical results of TG-SOI MOSFET have been compared with the simulation results obtained from the Visual TCAD, a 3-D device simulator from Cogenda Pvt. Ltd.

Performance Analysis of 10 nm FinFET with Scaled Fin-Dimension and Oxide Thickness

Abstract: This research work presents the performance analysis of multi-gate FinFET structure simulated at 10-nm technology node. The device electrical parameters have been extracted at different Fin dimensions to analyze the effect of Fin-scaling and oxide thickness variation onto the device performances. The designed device has been simulated at different heights and widths of the Fin. Thereafter, the oxide thickness has been varied for the structure. The effects of Fin height, width, and oxide thickness variation have been reported. The minimum value of Drain Induced Barrier Lowering (DIBL) has been observed at H fin of 27 nm with I ON /I OFF ratio as 1.89×104 to 3.1×104. The lowest Subthreshold Swing (SS) of 59.5 mV/decade is obtained at H fin of 40 nm. At different Fin-width values, it has been observed that the DIBL reduces with the reduction in Fin-width but the drain current increases only with higher Fin-width and hence, ON current increases. This research work provides a better understanding to the scaling of the complex structure design of FinFETs.

Hetero-Dielectric oxide engineering on dopingless gate all around nanowire MOSFET with Schottky contact source/drain

Abstract: In proposed work, gate oxide engineered Schottky Barrier (SB) Hetero-Dielectric (HD) Single Metal (SM) Gate All around Nanowire MOSFET is purposed for low power digital circuitry. Proposed device has an asymmetric oxide geometry having high-k (HfxTi1-xO2) on source side and SiO2 on drain side with Schottky Source/Drain regions. Leakage currents are reduced to an order of 10−15 over 10−9 A as compared to conventional GAA MOSFET. Device is simpler in fabrication in contrast to Junctionless (JL) NWFETs due to its dopingless design. Also, it has almost negligible gate induced drain leakage (GIDL) current value. An extensive comparison is outlined between the subthreshold performance of Single metal, Dual metal Hetero-Dielectric (HD) and Gate Stack (GS) SB-SM-GAA NWFET configurations. An improvement is observed in ON to OFF-state current ratio by 68.05% and an impressive decline in drain induced barrier lowering (DIBL) by 48.15% in HD-SB-SM-GAA NWFET as compared to Gate stack structure at same physical dimensions. Further, SM device has been found to have better ION/IOFF ratio, higher transconductance, lowered DIBL and an optimum subthreshold slope as compared to DM device.

GaN-based Double Gate-Junctionless (DG-JL) MOSFET for Low Power Switching Applications

Abstract: In this paper, GaN-based double gate-junctionless(DG-JL) MOSFETs with a gate length of 20 nm have been designed and performance have been evaluated for low power switching device. The values of subthreshold (SS) and drain induced barrier lowering (DIBL)are found to be 64.78 mY/dec and 32.81 mV/V, respectively. These values are lower than that of GaN-based double gate (DG) MOSFET. The static power dissipation is very low as $\pmb{4.2\times 10^{-5}\mu} \mathbf{W}/\pmb\mu \mathbf{m}$ . These results indicate that GaN-based DG-JL MOSFET is a suitable candidate for future ultra-low-power switching applications.

Si 3 N 4 :HfO 2 dual-k spacer bulk planar junctionless transistor for mixed signal integrated circuits

Abstract: For the first time halfnium oxide (HfO 2 ) is being incorporated in the dual-k spacers and has been used in bulk planar junctionless transistor (BPJLT). It has been found that incorporating HfO 2 in spacers not only improves the electrostatic integrity but also improves digital/analogue circuit performance of the BPJLT. Further, the increased effective gate length due to fringing electric field through HfO 2 to thin body reduces OFF-state leakage, subthreshold swing and drain-induced barrier lowering by ~60, ~15 and ~30%, respectively. Although the presence of HfO 2 inner spacer layer at source/drain increases the parasitic capacitances, the significant improvement in ON-state drive current reduces the intrinsic gate delay of the device. Further, the analogue circuit figures of merit such as transconductance, transconductance generation factor and the intrinsic gain of the proposed device are found to be significantly improved over the conventional BPJLT device. The mixed mode device/circuit simulation results of an inverter and the common source amplifier show that leakage power dissipation, propagation delay and the open-circuit voltage gain of the proposed device are improved significantly over the conventional BPJLT device. The fabrication process flow of this novel device has also been proposed.

Modeling of Inner Fringing Charges and Short Channel Effects in Negative Capacitance MFIS Transistor

Abstract: We propose a compact model for bias dependent inner fringing (IF) charges and the short channel effects (SCEs) for the Metal-Ferroelectric-Insulator-Semiconductor Double Gate Negative Capacitance Field Effect Transistor (MFIS DG-NCFET) using a novel capacitor network approach. We extensively validate the unconventional SCEs stemming from inner fringing field lines including threshold voltage roll-up $(V_{th}$ roll-up), negative drain induced barrier lowering (NDIBL), and steep sub-threshold swing (SS) for the sub-threshold region using TCAD results. The proposed model is implemented in Verilog-A, which captures the SCEs for different channel lengths through a single set of parameters.

Compact modeling of the subthreshold characteristics of junctionless double-gate FETs including the source/drain extension regions

Abstract: With the gate length shrinking to a few tens of nanometers, junctionless double-gate field-effect transistors (JL DG FETs) have become widely studied. In the subthreshold region, the electrical characteristics of JL DG FETs are sensitive to device parameters such as channel length, channel thickness, oxide thickness, doping concentration, and whether there are source/drain (S/D) extension regions or not. Therefore, it is essential for device engineers to develop compact models to run circuit simulations. In this paper, a compact JL DG FET model including S/D extension regions in the subthreshold region is proposed. Based on the superposition of the 1D Poisson equation and the 2D Laplace equation, the potential model is developed with and without S/D extension regions. Moreover, the subthreshold current, subthreshold slope, threshold voltage, and the drain induced barrier lowering are extracted without numerical iteration. The modeling results were verified with an ATLAS TCAD simulator and compared with a conventional undoped DG FET. We showed that the JL DG FET using the proposed compact model has better short-channel characteristics than the undoped DG FET with S/D extension regions, and we recommend that the doping concentration in the JL DG FET should be lighter for better subthreshold characteristics.

Effects of the physical parameter on gate all around FET

Abstract: As the devices are getting compact, the size of transistors reduces day by day; however, with certain limitations. Due to miniaturization, the characteristics of the transistor change due to quantum mechanical effects and the present scenario, analytically modeled surface potential-based gate all around (GAA) FET model by solving 1-D Poisson’s equation, approximation method and using necessary boundary condition. Here, the change in channel material (Si, InP, GaAs, InAs and Ge), channel radius (varied from 6 nm to 10 nm), oxide thickness (changed from 2 nm to 5 nm), drain to source voltage (varied from −0.5 V to 0.5 V), Source/Drain doping (varied from 1017 to 1022/cm3) and temperature (from 0 to 300 K) of the transistor, surface potential changes from −1.6 V to 1.3 V approx. respectively, considered as the GAA FET parameters. The proposed novel model exhibits better control over hot carrier effect, Drain Induced Barrier Lowering (DIBL), reduced threshold voltage and other such short channel effects in the GAA FET. Moreover, the I–V characteristics of the GAA FET were analyzed. The MATLAB code is used for modeling of the GAA FET nanowire transistor.

Experimental observation of zero DIBL in short-channel hysteresis-free ferroelectric-gated FinFET

Abstract: The experimental investigation for the drain-induced-barrier-lowering (DIBL) in nanometer scale hysteresis-free 100 nm-long ferroelectric-gated FinFET (which employs the voltage-amplifying attribute of Pb(Zr0.52Ti0.48)O3-based ferroelectric capacitor) is done to verify the DIBL improvement. The DIBL of the ferroelectric-gated FinFET (which is evaluated at 10−7 A/μm of drain current) is improved from ∼48 mV/V to ∼32 mV/V. When the DIBL is evaluated at 10−6 A/μm, it is reduced from 22.89 mV/V to ∼0 mV/V. The physical origin of the DIBL enhancement can be understood due to negative DIBL. The negative DIBL effect [a.k.a., drain-induced-barrier-rising (DIBAR)] is originated from a decrease of internal gate voltage, which takes place due to a gate charge reduction with increased drain voltage.

Investigation of impact of gate underlap/overlap on the analog/RF performance of composite channel double gate MOSFETs

Abstract: The influence of gate overlap and underlap on the DC/RF behavior of a composite channel based double gate MOSFET (DG MOSFET) that can be used for RF/analog applications is investigated using the 2D Sentaurus TCAD tool in this work. An InAs-inserted In07Ga0.3As composite channel, double silicon delta doping technology, n+-In0.53Ga0.47As source and drain regions, and Si3N4 passivation are some of the key features of the proposed device. 2D-Sentaurus Technology Computer Aided Design (TCAD) simulation has been performed using the hydrodynamic model. Interface trap models have also been incorporated to increase the accuracy of TCAD simulations carried out at room temperature. Key RF/analog figures of merit such as drain current (ID), transconductance (gm), gate leakage current (IGS), subthreshold current, drain induced barrier lowering, electron velocity in the quantum well, cutoff frequency (fT), and maximum oscillation frequency (fmax) have been explored to analyze the RF/analog performance of the proposed device. TCAD simulations reveal the fact that reducing the gate length and employing a gate underlap strategy can improve the analog and RF performance of the proposed DG MOSFET.The influence of gate overlap and underlap on the DC/RF behavior of a composite channel based double gate MOSFET (DG MOSFET) that can be used for RF/analog applications is investigated using the 2D Sentaurus TCAD tool in this work. An InAs-inserted In07Ga0.3As composite channel, double silicon delta doping technology, n+-In0.53Ga0.47As source and drain regions, and Si3N4 passivation are some of the key features of the proposed device. 2D-Sentaurus Technology Computer Aided Design (TCAD) simulation has been performed using the hydrodynamic model. Interface trap models have also been incorporated to increase the accuracy of TCAD simulations carried out at room temperature. Key RF/analog figures of merit such as drain current (ID), transconductance (gm), gate leakage current (IGS), subthreshold current, drain induced barrier lowering, electron velocity in the quantum well, cutoff frequency (fT), and maximum oscillation frequency (fmax) have been explored to analyze the RF/analog performance of the proposed d...

Asymmetric gated Ge-Si0.7Ge0.3 nHTFET and pHTFET for steep subthreshold characteristics

Abstract: The miniaturisation of transistors imposes thermal limits on MOSFET structures due to increase in leakage current and static power consumption per unit area of chip below 20 nm technology node. Tunnel FET has potential to reduce static power consumption to design below 20 nm technology within thermal limits thus increases the scope of future scaling trends. A new asymmetric Ge-Si0.7Ge0.3 hetero-junction tunnel FET (HTFET) is proposed with different oxide thickness from source and drain side. The asymmetric Ge-Si0.7Ge0.3 HTFET has steep subthreshold characteristic, low DIBL with high ION/IOFF current ratio for operating voltage less than 1V. The proposed design can be fabricated easily due to the similar lattice structure of Ge and Si. The ION/IOFF current ratio greater than 108 is achieved for gate length of 15 nm in nHTFET having Pt/HfO2 as gate contact and oxide material. The lowering of parasitic BJT effect in OFF state condition is also achieved in the same.

Performance investigation of electrode work-function engineered hetero-dielectric buried oxide vertical TFET

Abstract: For enhancement of and in tunnel field-effect transistors (TFETs), it is important to choose novel materials and structures. Here, the authors design a hetero-dielectric buried oxide vertical TFET (HDB VTFET) and its device characteristics has been investigated. This proposed device reveals the tremendous improvement in terms of sub-threshold slope, drain-induced barrier lowering, on-current and suppresses the ambipolar behaviour up to V gs = −1.0 V by maintaining very low off-current. Hence, the concept of hetero-dielectric buried oxide (BOX) and two metal electrodes having different work-functions are used here to obtain better results in terms of the current driving capability, steep subthreshold slope (SS) and drain-induced barrier lowering (DIBL). This device is a promising candidate for low-power consumption applications.

Evaluation of an InAs HEMT with source-connected field plate for high-speed and low-power logic applications

Abstract: In this study, we have presented a source-connected field plate (SCFP) InAs high electron mobility transistor (HEMT) and evaluated its potential for using in high-speed and low-power logic applications. The fabricated device demonstrated good electrical characteristics including low subthreshold swing (SS) of 76 mV/decade, drain induced barrier lowering (DIBL) of 44 mV/V, ION/IOFF ratio of 2.4 × 104, an off-state gate leakage current of less than 5 × 10−6 A/mm and a Gm,max of 1100 mS/mm at VDS = 0.5 V. When increasing the drain-source bias (VDS) to 1.0 V, the Gm,max increased to 1750 mS/mm with a cut-off frequency of 113 GHz. These results revealed that the fabrication of source-connected field plate InAs HEMTs achieved excellent device performance for high-speed and low-power logic applications.

Mole Fraction Dependency Electrical Performances of Extremely Thin SiGe on Insulator Junctionless Channel Transistor (SG-OI JLCT)

Abstract: In this paper, the single-gate junctionless (JL) MOSFET with extremely thin silicon germanium (SiGe) device layer on insulator (ETSG-OI) is explored to identify the short channel effects (SCEs) and electrical behavior of the device. The device incorporates various engineering schemes (channel and spacer engineering scheme) with JL topology on SOI platform. The influence of the SiGe device layer with mole fraction (x) variation (x = 0.25, 0.5, 0.75) is investigated to understand the bandgap differences of the device. Depending on the change in Ge mole fraction, the energy potential, electric field, and drain induced barrier lowering (DIBL) performances are analyzed. From the simulation results at x = 0.25, the ETSG-OI JLCT shows reasonable improvement in ON current (ION) and DIBL at both linear and saturation drain voltages. For different values of x, the energy bandgap tends to vary from 0.6−1.1 eV. It is observed that at x = 0.25 the bandgap is 0.8 eV which is almost near to the bandgap of Si material due to the 25% existence of Ge material.

Performance Optimization of Vertical Gaussian Doped SOI Junctionless FET with Substrate Bias Effects

Abstract: This paper presents a TCAD simulation based study of channel potential, threshold voltage, drain induced barrier lowering and subthreshold swing of vertical Gaussian doped SOI Junctionless FET with back bias effects. The subthreshold characteristics of the proposed structure are optimized using the straggle parameter and substrate bias voltage. It is shown that controlling the doping concentration in the channel and substrate bias improves the channel electrostatics in SOI Junctionless FET, thus, enhances the subthreshold performance.

Optimization of Dual-K Gate Dielectric and Dual Gate Heterojunction SOI FinFET at 14 nm Gate Length

Abstract: Modification of process parameters of the Fin shaped Field Effect Transistor (FinFET) is the field of research which has drawn attention after it has been inferred that these transistors diminish t...

Influence of Structural Parameters on the Behavior of an Asymmetric Linearly Graded Workfunction Trapezoidal Gate SOI MOSFET

Abstract: This paper presents a dual metal trapezoidal recessed channel metal oxide semiconductor field effect transistor (MOSFET) embedded with asymmetric stack gate with linearly graded metal work-function technique to improve the carrier transport efficiency and device switching performance. The analytical model for the proposed asymmetric-linearly graded trapezoidal gate (ASY–LGTG) silicon on insulator (SOI) MOSFET has been developed considering parabolic approximation of 2-D Poisson’s equation. The threshold voltage of the device is extracted using minimum surface potential. The simulation work has been carried out using a Silvaco TCAD tool to validate the results of the analytical model. This grooved structure exhibits the corner effect, which plays a dynamic role in the improvement of the device performance. However, the impact of the corner effect can be controlled by the groove corner angle and doping concentration. We have also investigated the impact of different structural parameters such as negative junction depth (NJD), corner angle, substrate doping and stack gate features (upper oxide permittivity and oxide thickness ratio) on the performance of minimum surface potential, sub-threshold slope (SS), drain induced barrier lowering (DIBL), threshold voltage and device switching characteristics.

Bottom-up fabrication of InAs-on-nothing MOSFET using selective area molecular beam epitaxy

Abstract: In this paper we report on the fabrication and electrical characterization of InAs-on-nothing metal-oxide-semiconductor field-effect transistor composed of a suspended InAs channel and raised InAs n+ contacts. This architecture is obtained using 3D selective and localized molecular beam epitaxy on a lattice mismatched InP substrate. The suspended InAs channel and InAs n+ contacts feature a reproducible and uniform shape with well-defined 3D sidewalls. Devices with 1 μm gate length present a saturation drain current (I Dsat) of 300 mA mm-1 at V DS = 0.8 V and a trans-conductance (GM ) of 120 mS mm-1 at V DS = 0.5 V. In terms of electrostatic control, the devices display a minimal subthreshold swing of 110 mV dec-1 at V DS = 0.5 V and a small drain induced barrier lowering of 50 mV V-1.

A Trapezoidal Cross-Section Stacked Gate FinFET with Gate Extension for Improved Gate Control

Abstract: An improved trapezoidal pile gate bulk FinFET device is implemented with an extension in the gate for enhancing the performance. The novelty in the design is trapezoidal cross-section FinFET with stacked metal gate along with extension on both sides. Such improved device structure with additional process cost exhibits significant enhancement in the performance metrics specially in terms of leakage current behavior. The simulation study proves the suitability of the device for low power applications with improved on/off current ratio, subthreshold swing (SS), drain induced barrier lowering (DIBL), Gate Induced Drain Leakage (GIDL) uniform distribution of electron charge density along the channel and effects of Augur recombination within the channel.

Impact of structural parameters on DC performance of recessed channel SOI-MOSFET

Abstract: With the concept of groove gate and implementing the idea of silicon on insulator (SOI), a new analytical model is developed for the rectangular recessed channel silicon on insulator (RRC-SOI) metal oxide semiconductor field effect transistor (MOSFET). This analytical model is formulated using 2D Poisson's equation and develops a compact equation for threshold voltage using minimum surface potential. This paper analyses the effect of negative junction depth (NJD) on device parameters, such as minimum surface potential, threshold voltage, sub-threshold slope (SS), and drain induced barrier lowering (DIBL). The impact of oxide thickness variation on the above parameters has also been evaluated. Further, the linearity performance in terms of figure of merits (FOM) and device parameters like drain current and trans-conductance of the proposed model is compared with the simulated results of rectangular recessed channel (RRC) MOSFET. The validity of the proposed model has been verified with simulation results performed on Sentaurus TCAD device simulator.

Reduced variability of drain-induced barrier lowering and subthreshold slope at high temperature in bulk and silicon-on-thin-buried-oxide (SOTB) MOSFETs

Abstract: The temperature dependence of the variability of drain-induced barrier lowering (DIBL) and subthreshold slope (SS) is experimentally investigated in bulk and fully depleted silicon-on-thin-buried-oxide MOSFETs. Measurement results show that variability of both DIBL and SS is reduced at high temperature. The origins of these new findings are explained and confirmed by device simulations. It is found that reduced variability of DIBL at high temperature originates from randomness along the channel length direction (source–drain asymmetry), while reduced variability of SS at high temperature is mainly influenced by randomness along the channel width direction.

Metal Grain Granularity Induced Variability in Gate-All-Around Si-Nanowire Transistors at 1nm Technology Node

Abstract: As predicted, 5nm technology is not going to be ready for production until 2025 and it will be some sort of FinFET (possibly gate-all-around silicon nanowire or similar type of devices). It is time to search for advanced device structures such as nanowires. In this work, TCAD simulations are performed for the first time to evaluate the potential of 1nm gate length cylindrical Si channel nanowire field effect transistors (NW-FET) at extreme scaling limits. Effects of metal grain granularity (MGG) of the gate-all-around (GAA) NW-FET device have been studied to understand variability of the performance metrics such as, the threshold voltage, on-current, off-current, sub-threshold slope and drain induced barrier lowering. It is shown that the gate-all-around NW-FETs have the potential to replace FinFETs in future technology nodes because of their better channel electrostatic control.

Analytical modelling and performance analysis of gate‐ and channel‐engineered trapezoidal trigate MOSFET

Abstract: Here, the authors propose an analytical model to evaluate the performance of an advanced trigate MOSFET structure called trapezoidal trigate MOSFET on silicon-on-nothing (TTMSON). The model is based on the solution of Poisson's partial differential equation in three dimensions. The expression for potential distribution has been used to model other device parameters like electric field distribution, quantum inversion charge, and threshold voltage. The TTMSON device immunity to various short channel effects (SCEs), such as drain-induced barrier lowering (DIBL) and sub-threshold swing, has been examined. A detailed analysis of the gate and channel engineering techniques like dual material gate, graded channel, and dual material gate with graded channel has also been carried out to choose the best device structural configuration for enhancing the device performance and mitigating SCEs in nano-regime. In addition, the effect of inclination angle on different performance parameters has been considered. The proposed analytical model of TTMSON has been verified by comparing the model results with the simulation results using the numerical device simulator ATLAS.