Showing papers on "Drain-induced barrier lowering published in 2020"

A Holistic Approach on Junctionless Dual Material Double Gate (DMDG) MOSFET with High k Gate Stack for Low Power Digital Applications

Abstract: The 2D analytical models for electrostatic potential, threshold voltage, subthreshold swing, Drain Induced Barrier Lowering (DIBL) and drain current of the Dual Material Double Gate junctionless transistor with high k gate structure is revealed. The electric field is obtained by solving Poisson equation with the help of parabolic approximation technique. The high k gate stack engineered (JL DMDG stack MOSFET) exaggerate the ION current of 10−4 (A/μm) and IOFF current of 10−14(A/μm) gives a remarkable amount of leakage current reduction. The short channel effects are quashed with the symmetric high k gate stack structure to a good extent. The device characteristics have been analyzed for various different high k materials. The significant outcomes of analytical solutions are mapped with the numerical solutions from Synopsys TCAD device simulator to affirm and validate the device structure. The JL DMDG Stack MOSFET based inverter circuit was also implemented to empower the device performance in digital applications. The voltage transfer characteristics, noise margin, delay and power dissipation of the JL DMDG stack MOSFET inverter circuit is assessed through numerical simulator with the help of Verilog-A language show substantial improvement due to this gate stack engineering model.

A Journey from Bulk MOSFET to 3 nm and Beyond

Abstract: To overcome scaling issues such as controlling gate leakage, drain induced barrier lowering, higher subthreshold conduction, polysilicon gate depletion, and other short channel effects various engineering proposed. The gate dielectric, metal work function, and device structural engineering enabled the semiconductor industry to make a transition from the conventional planar MOSFET towards a revolutionary 3D tri-gate structure called FinFET. FinFET is one of the fundamental invention in the semiconductor industry, which replaced the planar CMOS technology around 22 nm technology. By following Moore’s law, it accelerated the scaling to 7 nm, but at 5 nm, in the same way, GAAFET replaced FinFET due to technological hurdles. Nanosheet, which is one type of GAAFET are in the recent trend. But researchers are trying to explore the possibilities to continue the miniaturization beyond 3 nm by combining the effect of non-silicon channel material such as Ge, InGaAs, or 2D materials with nanosheet, which will improve the functionality of the device while going down in the technology node. In this survey, an attempt has been made for the structure present till 7 nm process. Also, a few new proposals in research to take the scaling up to 3 nm and beyond are included. The future innovations may put an intercept on the slowing down of Moore’s law, and bring the miniaturization back in the track.

Investigation of Short Channel Effects (SCEs) and Analog/RF Figure of Merits (FOMs) of Dual-Material Bottom-Spacer Ground-Plane (DMBSGP) FinFET

Abstract: FinFETs are popular and forefront runner in integrated circuits (ICs) technology due to exceptional scalability and suppressed short channel effects (SCEs). The bottom spacer (BP) concept is adopted in FinFET to achieve ameliorated short-channel, reduced self heating issues and to solve width quantization effect. The dual-material-gate (DMG) concept provides novel features like threshold voltage roll-up, transconductance enhancement and suppression of SCEs by work function engineering. Further, the ground-plane (GP) concept is also introduced to minimize the interaction between source and drain region which results in suppressed drain induced barrier lowering (DIBL). This paper investigates the systematic analysis of novel DMBSGP FinFET. The electrical performance parameters are extracted for different bottom spacer height (BSH) and workfunction differences (∆W). The analog/RF figure of merits (FOMs) such as transconductance (gm), output conductance (gd), transconductance generation factor (gm/ID), early voltage (VEA), intrinsic gain (AV), cut-off frequency (fT), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP) are examined for different BSH of DMBSGP FinFET using 3-D ATLAS device simulator.

Impact of high-k gate dielectric with different angles of coverage on the electrical characteristics of gate-all-around field effect transistor: A simulation study

Abstract: In this paper, we consider the electrical performance of a circular cross section gate all around-field effect transistor (GAA-FET) in which gate dielectric coverage with high-k dielectric (HfO2) over the channel region has been varied. Our simulations show the fact that as high-k dielectric coverage over the channel increases, ION/IOFF ratio and transconductance over drain current (gm/ID) will be enhanced. Moreover, we investigate the impact of channel length scaling on these devices. The obtained results show that subthreshold slope (SS), drain induced barrier lowering (DIBL) and threshold voltage (VTH) roll-off will be reduced as a result of scaling. In this work TCAD simulator was concisely calibrated against experimental data of a GAA-FET from IBM. The Schrodinger equation is solved in the transverse direction and quantum mechanical confinement effects are taken into account.

All MOCVD grown Al0.7Ga0.3N/Al0.5Ga0.5N HFET: An approach to make ohmic contacts to Al-rich AlGaN channel transistors

Abstract: We report a gate recessed Al0.7Ga0.3N/Al0.5Ga0.5N heterostructure field effect transistor (HFET) with a graded contact cap layer grown by metal organic chemical vapor deposition (MOCVD) on AlN/Sapphire substrate. A low specific contact resistivity ρc of 2.1 × 10−5 Ω·cm2 is demonstrated with current injection from the top of the Al0.7Ga0.3N barrier to the Al0.5Ga0.5N channel. The device with a gate length of 160 nm exhibits a drain current density at gate shorted to source (ID,SS) of 420 mA/mm, a cutoff frequency fT of 20 GHz, and a maximum oscillation frequency (fmax) of 40 GHz. The same device has a three terminal off-state gate-to-drain breakdown voltage of 170 V, corresponding to an average breakdown field (FBR) of 2.8 MV/cm between the gate and drain, due to drain induced barrier lowering effect. Devices with a gate length of 1 µm demonstrate a gate to drain breakdown voltage of 195 V or an average breakdown field of 3.9 MV/cm. This work provides a way to make ohmic contacts to Al-rich AlGaN channel heterojunction transistors for high power and high frequency applications.

Low-Power Efficient p+ Si 0.7 Ge 0.3 Pocket Junctionless SGTFET with Varying Operating Conditions

Abstract: A new low-power Si1−xGex pocket junctionless single-gate tunnel field-effect transistor (JLSGTFET) is designed to achieve steep subthreshold performance and a better ION/IOFF ratio (∼ 108) in sub-20-nanometer technology node. The mole fraction of Ge represented by x is kept at 0.3 for the SiGe pocket region. The proposed JLSGTFET shows better performance with a Ge mole fraction value x = 0.3. The mole fraction value affects various electrical parameters in terms of leakage current, junction capacitance and transconductance of the channel region. The device exhibits reduced switching capacitance due to the smaller-bandgap pocket region between the source and channel. Analysis of the JLSGTFET is carried out for DC and AC parameters at room temperature. Temperature analysis plays a vital role in determining reliable ON- and OFF-state performance in transistors. Therefore, the proposed pocket JLSGTFET is investigated under harsh temperature conditions to characterize the performance for DC and subthreshold parameters. The sensitivity of the device is analyzed under different temperature conditions over a range of 250–400 K to observe subthreshold performance including transfer characteristics, output characteristics, ION/IOFF ratio, subthreshold slope (SS) and drain-induced barrier lowering (DIBL). The JLSGTFET demonstrates a small variation in DC and subthreshold parameters, indicating good prospects for future analog and digital applications. All the analysis of the proposed JLSGTFET is carried out on a 2D/3D VisualTCAD device simulator.

Benefitting from High-κ Spacer Engineering in Balistic Triple-Gate Junctionless FinFET- a Full Quantum Study

Abstract: In this paper, a numerically comprehensive investigation have been performed in order to propose a high-κ spacer triple-gate junctionless FinFET (HKS TG JL FinFET) in three dimensional (3D) simulation domain. In the proposed structure, a high dielectric insulator called as HfO2 is used on the both sides of the source and the drain regions as the spacers. The spacer located on the drain side, extends into the channel region and the other spacer is only on the channel region. Mode Space Non-Equilibrium Green’s Function method has been utilized in order to analyze the nanoscale proposed structure. The modification of the electric field along the channel region is introduced as the main reason for the improvement of the electrical characteristics. Also, the explored results about role of different thicknesses of the proposed structure spacers on the electrical performance are discussed in the last section. The explored results have revealed that the leakage current is successfully reduced about 20% and also Ion/Ioff experiences a 30% increase for the proposed structure. Also, the short channel effects in terms of subthreshod slope and drain induced barrier lowering (DIBL) is improved about 11.59% and 50% respectively. It is stated that the HKS JL TG FinFET can be a good candidate for future high speed applications.

Channel Length Scaling Pattern for Cylindrical Surrounding Double-Gate (CSDG) MOSFET

Abstract: The natural length of MOSFETs helps to describe the potential distribution in the Silicon substrate. This natural length varies in different device structures, from a single gate to multi-gate device geometry. To measure the short channel effects degree, the natural length should be known because various vital parameters such as OFF-current, Roll-off threshold voltage, and drain induced barrier lowering depend on it. In this research work, authors have presented a scaling theory for Cylindrical Surrounding Double-Gate (CSDG) MOSFET, which guide the device design. The scaling method has been derived, based on the application of the Poisson equation, in a cylindrical structure using Parabolic Potential Approximation (PPA) along the radial direction (substrate part only). Furthermore, a comparison with cylindrical surrounding-gate MOSFETs, Silicon-on-insulator, and double-gate device geometries has been obtained. The results obtained using the PPA model show that CSDG MOSFET has the least natural length, making it a better component for SCEs immunity.

Few-Layered MoS2 Field-Effect Transistors with a Vertical Channel of Sub-10 nm

Abstract: Few-layered molybdenum disulfide (MoS2) has demonstrated promising advantages for the integration of next-generation electronic devices. A vertical short-channel MoS2 transistor with a channel leng...

Impact of core thickness and gate misalignment on rectangular core–shell based double gate junctionless field effect transistor

Abstract: A rectangular core is inserted in double gate junctionless transistor (DGJLT) which separates the top shell and bottom shell in the device called as rectangular core–shell double gate junctionless transistor (RCS-DGJLT). The core doping and core thickness are optimized to improve the performance of RCS-DGJLT. The core thickness is optimized for different shell thicknesses in the device which has not been explored yet in the literature. An interesting observation is found that the core thickness should be equal to the shell thickness for smaller shell thicknesses, whereas the thicker core is required for larger shell thicknesses. RCS-DGJLT has shown remarkable improvement than DGJLT. Further, the effect of gate misalignment on either side (source/drain) of the channel in RCS-DGJLT and DGJLT is studied and compared on the basis of device performance. The study of gate misalignment becomes essential due to the complications on achieving perfectly aligned gates during the fabrication of double gate device. An RCS-DGJLT is found to have better tolerance to gate misalignment than DGJLT. The best parametric values like OFF current is ~10–16A, ON current is ~10–5A, subthreshold slope is nearly 66.2 mV/decade, ON/OFF current ratio is ~1010, drain induced barrier lowering is ~42.1 mV V−1 and threshold voltage ~0.56 V at perfectly aligned gate condition is obtained on keeping core and shell thickness at 3 nm each. As per the analysis, the gate misalignment up to 20% on either side of the channel does not impact the performance parameters much and hence reduces the stress of meeting the requirement of perfect gate alignment.

Analysis on Reverse Drain-Induced Barrier Lowering and Negative Differential Resistance of Ferroelectric-Gate Field-Effect Transistor Memory

Abstract: We demonstrate novel analysis on electrical characteristics of ferroelectric-gate field effect transistor (FeFET), especially reverse DIBL (RDIBL) and negative differential resistance (NDR) phenomena through measurements of fabricated FeFETs and technology computer-aided design (TCAD) simulations. The FeFETs are embodied by extracting the ferroelectric properties using metal-ferroelectric-metal (MFM) capacitors and applying it to the gate stack of n-type FeFETs. Then, the device and the model parameters of the FeFETs are calibrated by matching TCAD simulation results to measured electrical characteristics. By the TCAD simulations which reflect the Preisach model considering multi-domain ferroelectric characteristics, it is revealed that RDIBL and NDR result from the local conduction band energy rising at the drain-side with drain voltage increasing. Furthermore, it is found that gate-induced drain leakage (GIDL) accelerates RDIBL with the help of the injection of the generated holes by GIDL in the floating body of FeFETs.

Drain Current Modelling of Asymmetric Junctionless Dual Material Double Gate MOSFET with High K Gate Stack for Analog and RF Performance

Abstract: This paper presents the continuous 2D analytical modelling of electrostatic potential, threshold voltage (Vth), subthreshold swing, drain induced barrier lowering (DIBL) and drain current of asymmetric junctionless dual material double gate MOSFET with high K gate stack (AJDMDG Stack MOSFET). The electrostatic potential is achieved by solving Poisson’s equation with the help of the parabolic approximation method. Analytical results are verified by using ATLAS TCAD Device simulator. A comparative study of short channel effects (SCEs) of AJDMDG Stack MOSFET and asymmetric junctionless dual material double gate MOSFET with high K gate stack (SJDMDG Stack MOSFET) has been observed in order to show the efficacy of asymmetry condition such as gate oxide asymmetry, gate work function asymmetry etc. for suppressing SCEs. Further, analog/RF performance parameters such as transconductance (gm), output resistance (rout), intrinsic gain, transconductance generation factor (TGF), cut-off frequency (fT), maximum frequency (fmax), gain bandwidth product (GBW) etc. of AJDMDG Stack MOSFET are observed and compared the results with SJDMDG Stack MOSFET structure. Results reveal that AJDMDG Stack MOSFET has better efficacy for RF applications.

A new trench double gate junctionless FET: A device for switching and analog/RF applications

Abstract: In this work, a trench double-gate junctionless FET (TDG-JLFET) is proposed for switching and analog/RF applications. In TDG-JLFET, the gates are placed vertically in separate trenches for better control over the channel electrostatics. The performance of proposed structure is assessed using two dimensional (2D) numerical simulations in TCAD tool (ATLAS). At optimized device structural parameters, TDG-JLFET demonstrates subthreshold swing (SS), drain induced barrier lowering (DIBL) and ON-to-OFF current ratio ( I ON / I OFF ) of 69 mV/dec, 27 mV/V and 3.5 × 10 13 , respectively. Further, TDG-JLFET exhibits peak transconductance ( g m ) of 1478 μ S / μ m and unity gain cut-off frequency ( f T ) of 423 GHz at channel length of 20 nm.

Investigation of Single Event Transient Effects in Junctionless Accumulation Mode MOSFET

Abstract: The Junctionless Accumulation Mode Double Gate MOSFET (JAM DG MOSFET) is a promising novel architecture for future nano-scaled devices because of its outstanding electrical characteristics, e.g., lower subthreshold swing, lower drain induced barrier lowering, i.e., lower short channel effects and higher $\text{I}_{\mathrm{ ON}}/\text{I}_{\mathrm{ OFF}}$ ratio. In this paper, a comprehensive analysis of the effects of single-event transient on JAM DG MOSFET has been performed using the sentaurus TCAD simulator. The result shows that the transient drain current peak obtained after the heavy-ion strike for JAM DG MOSFET is small at lower value linear energy transfer (LET) and high for the larger value of LET. Collected charge at different LET values has also been investigated. Moreover, the sensitive region of the device, e.g., source to channel junction, channel, and channel to drain junction has been studied. It has been found that the drain to channel junction is more sensitive to the linear energy than the channel and source to channel junction. The electrical characteristics have also been compared with JL DG MOSFET.

Analysis of Threshold Voltage and Drain Induced Barrier Lowering in Junctionless Double Gate MOSFET Using High-κ Gate Oxide

Abstract: The change of threshold voltage and Drain Induction Barrier Lowering (DIBL) is observed when high dielectric constant material is used as gate oxide of the junctionless double gate (JLDG) MOSFET. For this purpose, an analytical threshold voltage model is proposed using the first term of the series-type potential model derived from the Poisson equation. The results of the model presented in this paper are in good agreement with threshold voltages derived from TCAD. Using this model, the threshold voltage and DIBL were observed for the channel length, the silicon thickness, and the gate oxide thickness with the dielectric constant as a parameter. As a result, when a high-κ material was used as a gate oxide, the threshold voltage increased but the rate of change with respect to channel size and oxide thickness decreased. The DIBL is inversely proportional to the dielectric constant, and the DIBL was as small as 20 mV/V even at a channel length of 15 nm when the dielectric constant was 30. In the case of using HfO2/ZrO2 (κ=25), the rate of change of threshold voltage for oxide thickness was about 1/5 smaller than SiO2 (κ=3.9). The rate of change of DIBL for oxide thickness in the case of La2O3 was about 1/4 smaller than SiO2 (κ=3.9). The use of the high-κ oxide film may increase the design margin for the oxide thickness variation. 

Reduction of Drain Induced Barrier Lowering in DM-HD-NA GAAFET for RF Applications

Abstract: In this research work, a dual-metal hetero-dielectric with nitride gate all around field effect transistor (DM-HD-NA GAAFET) has been proposed to address and mitigate an essential issue of drain induced barrier lowering and tunnelling leakage current. This device also provides better transconductance, output conductance, early voltage, and transforming growth factor so that it can also be used for radio-frequency (RF) applications. In this structure, silicon dioxide (SiO 2 ) is used at the source side while the silicon nitride (Si 3 N 4 ) is used at drain side to reduce tunnelling of charge. In DM-HD-NA GAAFET, gate material engineering (GME) technique is also being used in which higher work function metal is used at source side in order to accelerate charge carriers while lower work function metal is used at drain side so that it can increase ON-state current ( I ON ). The obtained results are compared with dual-metal hetero-dielectric with vacuum gate all around field effect transistor (DM-HD-VA GAAFET) to analyse its performance. In the proposed device structure, I ON increased by GME approach while I OFF decreased by hetero-dielectric method so it improves I ON / I OFF ratio for DM-HD-NA GAAFET compared to DM-HD-VA GAAFET device.

DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications

Abstract: The device dimensions have been consistently scaling down since many developing technologies need smaller and faster integrated circuits for advancement and improvement in both performance and device density. Device dimensions have been decreased drastically from micron to sub nanometer regime. Traditionally, miniaturizing and performance improvement was obtained by tweaking the MOSFET- reducing the channel lengths and gate oxide thickness, increasing dielectric constants etc. Unfortunately at 22nm node it reached a dead end. However, at 22 nm node the tri-gate FinFET introduced by Intel Corporation have provided many possibilities for scaling the dimensions with satisfactory device performance. Further, the gate all around (GAA) carbon nano tube field effect transistor (CNTFET) provides high gain, high trans-conductance, reduced short channel effects and conditions for scaling the technology to sub nano scale. Due to surround gate structure this GAA CNTFET offers better control with integration of high_k stacked dielectric wrapped around the channel. In this paper, first properties of Carbon nanotube (CNT) have been comprehensively studied for various chirality and diameter and parameters viz. Density of States (DoS) and Band gap (Eg) are extracted by using MedeA tool's VASP 5.3 module. The various CNT chirality have been optimized and the extracted parameters used to model and simulate CNTFET using Silvaco's Devedit3D, Atlas and Atlas3D modeling and simulation modules. The device input (ID-VGS ) and output (ID-VDS) characteristics have been intensively studied and parameters including ION /IOFF ratio, DIBL, sub threshold slope extracted and compared with the conventional devices. The GAA CNTFET device at 0.8 V supply voltage exhibits threshold voltage (VTH) 0.254 V, drain induced barrier lowering (DIBL) 72 mV/V, sub-threshold swing (SS) 63.29 mV/dec, and ION/ IOFF ratio 7.17e+06. The results demonstrate improvement in device parameters for the GAA CNTFET device as compared to bulk silicon and FinFET devices.

Comparison of LER Induced Mismatch in NWFET and NSFET for 5-nm CMOS

Abstract: Nanosheet field-effect transistors (NSFETs) have emerged as a novel device replacement for sub-7nm CMOS technology nodes. However, due to smaller fin thickness (Tfin = 5nm), NSFETs are more vulnerable to the process-induced variations. Among various types of process-induced variations, Line edge roughness (LER) is becoming a significant concern for multi-gate field-effect transistors (MugFETs) with smaller feature sizes. In this article, we have reported and compared the impact of LER on the electrical characteristics of NSFETs and nanowire field-effect transistors (NWFETs) for the sub-7nm technology node. We have generated a 3-D LER profile using 2-D Auto Covariance Function (ACVF) that considers two degrees of freedom for a realistic roughness analysis at advanced CMOS technology nodes. For a complete study of 3-D LER effect in NSFET, we have considered roughness along the nanosheet’s sidewalls as well as top and bottom surfaces. We have shown using 3D TCAD simulations that the sidewall roughness in NSFETs contributes to a negligible mismatch in threshold voltage and ON current. The mismatch performance of NSFET is compared with that of the NWFET for sub-7nm technology node. NSFET appears to be more immune to mismatch in ON current than NWFETs considered in this work. On the other hand, as compared with NSFET, owing to its superior gate all-around control, the NWFET achieves lower mismatch in drain induced barrier lowering (DIBL) and subthreshold slope (SS) in presence of LER. In addition to this, FETs with different channel doping modes such as inversion (IM) and Junction less (JL) mode have been compared for their matching performance against 3-D LER. It can be concluded from the results that IM FETs are more immune to 3-D LER as compared to JL FETs.

Impact of stress effect on triple material gate step-FinFET with DC and AC analysis

Abstract: Step-FinFET is an improvisation in various electrical characteristics with a modified mechanism. The gate length 20 nm, 15 nm, 20 nm has allowed an acceptable driving current and considerable power consumption which longer the battery life. The study consist of electron density, electron velocity, mobility, electric field, and surface potential to relate the improved device performance. The major variation of drain current due to stress effect, tunneling, saturation factor, and minority factor has been investigated. This paper analyzes the parameters like transconductance (Gm), Drain conductance (gd), input capacitance (Cgg), cut off frequency (fT), power consumption, etc., for verifying the RF and analog application. Various short channel effect (SCE) also studied in terms of threshold voltage (Vth), sub-threshold swing (SS), drain induced barrier lowering (DIBL) and On/Off ratio are investigated with different gate length and drain bias. As a result the minimum values of threshold voltage, SS and DIBL calculated for gate length of 15 nm are 0.2426 V, 69 mV/dec, 14.6 mV/V, respectively.

3-D Simulation of Novel High Performance of Nano-Scale Dual Gate Fin-FET Inserting the High-K Dielectric TiO2 at 5 Nm Technology

Abstract: The evolution of integrated circuit is based on the miniaturization of dimension in the transistor Mosfet, this reduction causes the undesirable effect: short channel effects (SCE) and hot carrier effect, the principal goal is to search for a device which can minimize this effects, thus, in this work we proposed a new device for the dual gate DG-FinFET with TiO2 material for smaller gate length Lg = 5 nm by using the TCAD-SILVACO simulator. Additionally, we explain the electrical characteristics of this device on various parameters such us: threshold voltage Vth, subthreshold slope (SS), the on-current (Ion), the off-current (Ioff), Ion/Ioff current ratio, the DIBL (drain induced barrier lowering), and the electrical field E. The results show that our structure gives excellent electrical characteristics. It requires the use of high-k dielectric of gate TiO2 and to the shorter gate length (Lg). Furthermore, the decreasing of the electrical field along the channel proves the suppressing of the hot carrier effect; we examine also the effect of variation of gate length (Lg) on this parameter. We obtained the following results: our simulation is improved for the smaller gate length Lg = 5 nm than (6, 8, 10 and 12) nm. So we noticed that the proposed device is the most compatible for increasing the performance of device (the reliability, the lower power and speeder circuit), also the TiO2 material is the best dielectric of gate with combination of metal gate TiN for the future of nanoscale device.

Impact of Hot-Carrier Degradation on Drain-Induced Barrier Lowering in Multifin SOI n-Channel FinFETs With Self-Heating

Abstract: Application of high-frequency ac stress in the place of conventional dc stress is known to decrease the damage caused by self-heating (SH)-induced hot-carrier injection (HCI) in highly scaled MOSFET devices. However, the effect of hot-carrier degradation on short-channel performance is less explored. In this article, a detailed examination of the drain-induced barrier lowering (DIBL) under hot-carrier stress is presented for 14-nm silicon-on-insulator (SOI) n-channel FinFETs. In particular, the influence of SH-enhanced HCI on DIBL is thoroughly investigated for devices with different geometrical parameters including a number of fins, gate length, and so on at different ac stress frequencies. The change in dominant degrading mechanism from bulk oxide trapping to interface state generation under dc and ac stress is shown to affect DIBL severely. Interestingly, the effect of SH on DIBL is in contrast to that in ON-current degradation. Furthermore, time evolution of DIBL degradation for asynchronous stress waveforms is studied for accurate reliability analysis for short-channel devices.

Impact of LER on Mismatch in Nanosheet Transistors for 5nm-CMOS

Abstract: In this paper, we have reported the impact of line edge roughness (LER) on the electrical characteristics of Nanosheet field effect transistors (NSFET). We have generated a 3-D LER profile using 2-D Auto Covariance Function (ACVF) that considers two degrees of freedom for a realistic roughness in fin-type, non-planar MOSFETs. For a complete study of 3-D LER effect in NSFET, we have considered roughness along the nanosheet's sidewalls as well as its top and bottom surfaces. We have shown using 3D TCAD simulations that the sidewall roughness contributes to a negligible mismatch in NSFET characteristics. The mismatch performance of NSFET is compared with that of the nanowire field effect transistor (NWFET) for 5nm technology node. NSFET appears to be more immune to mismatch in ON current than NWFETs considered in this work. On the other hand, as compared with NSFET, owing to its superior gate all-around control, the NWFET achieves lower mismatch in drain induced barrier lowering (DIBL) and subthreshold slope (SS) in presence of LER.

Design and Performance Analysis of FD Silicon on Insulator MOSFET

Abstract: In this work, Fully Depleted-Silicon on Insulator (FD-SOI) MOSFET is designed, and the impact of silicon thickness, source doping, and metal gate work function variations are investigated to analyze the various device performance parameters. Simulated results of ON current, OFF current, energy band diagram, gate capacitance, and drain capacitance are analyzed. In addition to this, drain induced barrier lowering (DIBL), the threshold voltage (Vth), sub-threshold slope (SS) variations are also evaluated. The results depict that the threshold voltage increases with the increment in Si surface thickness and source doping and it is 0.25V for 10 nm Si surface layer. The DIBL is 0.02 (V/V), and SS of 66.13 (mV/dec) is evaluated for the same Si surface layer thickness. Silvaco Atlas-2D TCAD simulator is used to estimate the various results.

TCAD Analysis and Modelling of Gate-Stack Gate All Around Junctionless Silicon NWFET Based Bio-Sensor for Biomedical Application

Abstract: In the present day, metallic oxide semiconductor field-effect transistor-based bio-sensors have been frequently used for various purposes due to their low cost and other properties. In this work, high-k Gate-Stack gate-all-around junctionless Silicon Nanowire FET (SiNWFET) is proposed for neutral biomolecule species detection and enhanced the device performance by introduced gate stack and high metal gate work-function. In particular, neutral biomolecule species like Streptavidin, Uricase, APTES, Protein and ChO x are considered in our study. Subthreshold slope, drain induced barrier lowering (DIBL), leakage current, transconductance, and shifting threshold voltage were considered for study the bio-sensor response. Effect of cavity thickness, cavity length, High-k dielectric thickness, and its length on the detection of the device has also become examined. The results in gate stack junctionless gate all around SiNWFET shows better performance in terms of DIBL, transconductance, leakage current, I ON /I OFF ratio and subthreshold slope. The high-k dielectric oxide (HfO 2 ) has been identified for chemical compatibility and thermal stability properties on metal oxide semiconductor transistor as a gate oxide to mitigate the gate tunneling current and short channel effects.

Parallel Gated Junctionless Field Effect Transistor

Abstract: The present work is a novel structure of Junctionless field effect transistor obtained by splitting the gate into two parts parallelly. The structure is termed as parallel gated structure. A simulation study on Cogenda VisualTCAD 2-D 1.8.2 device simulator is done to compare the electrical performance of the parallel gated structure with the conventional structure of Junctionless field effect transistor. A double gate structure has been considered for both proposed and conventional structure for this study. In case of the proposed structure there are total four sections of gate while in conventional structure there are two gates. While simulating identical gate potential is applied in all the gate sections of both of the structures. All the potentials considered for simulation are with reference to source potential. The simulation study shows that the parallel gated structure exhibits lower Drain Induced Barrier Lowering, better subthreshold characteristics, better carrier mobility and reduced leakage current compared to the conventional structure.

Superior Performance of a Negative-capacitance Double-gate Junctionless Field-effect Transistor with Additional Source-drain Doping

Abstract: In this work, we propose a negative-capacitance double-gate junctionless field-effect transistor (NC-JLFET) with additional source-drain doping for the first time. Superior performance of the NC-JLFET due to source and drain doping concentration is explained in detail. Additionally, the effects of the drain induced barrier lowering (DIBL) and negative differential resistance (NDR) are precisely analyzed in the NC-JLFET. Sentaurus TCAD simulation demonstrates that the additional source-drain-doped NC-JLFET exhibits a higher on/off current ratio ( I ON / I OFF ) and steeper subthreshold swing ( SS < 60 mV/dec) compared to a traditional JLFET. Besides, the negative capacitance effect causes the internal voltage of the gate to be amplified, resulting in negative DIBL and NDR phenomena. Finally, the performance of NC-JLFET can also be optimized by choosing suitable ferroelectric material parameters, such as ferroelectric thickness, coercive field, and remnant polarization. Our simulation study provides theoretical and experimental support for further performance improvement of low-power NCFETs by local structure adjustment.

Analysis on Variations of Metal Gate Work Function on Junctionless Double Gate MOSFET with High-k Spacers

Abstract: The fabrication of nanometer-scale traditional MOSFETs with junctions has become very challenging. The newer devices like junction less double gate MOSFETs are in focus as they have shown good electrostatic behavior compared with traditional MOSFETs. In this paper, we introduce new device architecture with high-k spacers placed on either side of both the gates of a junctionless double gate MOSFET. The effect of the high dielectric constant (ksp) of the spacer on the device characteristics has been studied. This paper investigates the junctionless double gate MOSFETs with high-k spacers of materials like silicon dioxide (SiO 2 ), hafnium oxide (HfO2) and aluminum oxide (Al 2 O 3 ). One of the important considerations for selecting the particular metal gate material is metal work function as it directly affects threshold voltage and the performance of the transistor. The work is done on the device to carry out analysis for drain induced barrier lowering (DIBL), output characteristics, transfer characteristics and I ON/ I OFF ratio.

Performance Analysis of Charge Plasma Based Five Layered Black Phosphorus-Silicon Heterostructure Tunnel Field Effect Transistor

Abstract: In this paper, five layered Black Phosphorus (BP) – Silicon (Si) based Tunnel Field Effect Transistor (TFET) is used to overcome the thermionic limits faced by Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and analysis of the device validates that TFET is a better alternative as nano scale transistor. To enhance the ON state current for five layered BP-Si based TFET, multi electrode (source and drain) based structure is used. For the first time, the charge plasma technique is implemented on BP. The proper work function of metal electrodes has been selected to accordingly implement the charge plasma based technique for BP and Si. Charge plasma will result in generation of electron and hole cloud depending on the work functions at source/drain electrode. Different device properties and characteristics curves viz. IDS-VGS and IDS-VDS are compared for monolayered TFET to five layered based TFET. Different analog/RF properties, as well as linear and distortion parameters of the device such as output conductance (gd), transconductance (gm), cut-off frequency (fT), third order intermodulation distortion, second and third order harmonic distortion, second and third order voltage intercept point and current intercept point, are examined for five layered BP-Si based TFET only. For five layered BP-Si based configuration, the proposed device offers a threshold voltage of 0.42 V, an average subthreshold slope of 24.14 mV/dec, ION of 1.7 × 10−4 A/μm, Drain Induced Barrier Lowering (DIBL) of 1.02 mV/V.

Electrical Characteristics of Bulk FinFET According to Spacer Length

Abstract: This paper confirms that the electrical characteristics of FinFETs such as the on/off ratio, drain-induced barrier lowering (DIBL), and sub-threshold slope (SS) can be improved by optimizing the FinFET spacer structure. An operating voltage that can maintain a life of 10 years or more when hot-carrier injection is extracted. An excellent on/off ratio (7.73×107) and the best SS value were found at 64.29 mV/dec with a spacer length of 90 nm. Under hot carrier-injection conditions, the supply voltages that meet the 10-year lifetime condition are 1.11 V, 1.18 V, and 1.32 V for spacer lengths of 40 nm, 80 nm, and 120 nm, respectively. This experiment confirmed that, even at low drain voltages, the shorter is the spacer length, the greater is the deterioration. However, this increasing maximum operating voltage is very small when compared to the increase in the driving voltage required to achieve similar performance when the spacer length is increased; therefore, the effective life is expected to decrease. The results indicate that structural optimization must be performed to increase the driving current of the FinFET and prevent degradation of the analog performance.