Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.

Insulated-gate field-effect transistor with self-aligned contact hole to source or drain

Abstract: An oxide dielectric layer is interposed between the polysilicon gate and the contact hole to the source or drain of an insulated-gate field-effect transistor to prevent electrical shorts between the gate and metal contact to the source or drain. The oxide dielectric layer enables the contact hole to be extremely close to the polysilicon gate without electrical shorts occurring therebetween, thereby eliminating the need for a minimum separation between the gate and contact hole.

Multiple-gate MOS transistor and a method of manufacturing the same

Abstract: Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability.

Apparatus and method for adjusting the threshold voltage of mos transistors

Abstract: An apparatus and method for adjusting the effective threshold voltage of a MOS transistor is disclosed. Reference voltage generation circuitry is used for generating a first voltage signal. Threshold voltage monitoring circuitry that includes the MOS transistor is used for measuring the effective threshold voltage of the MOS transistor and for generating a second voltage signal. Feedback circuitry compares the first voltage signal to the second voltage signal and adjusts the effective threshold voltage of the MOS transistor so that the first voltage signal is substantially equal to the second voltage signal. The effective threshold voltage of the MOS transistor is adjusted by adjusting its source-body voltage potential. The method includes the steps of generating a first voltage signal, measuring the effective threshold voltage of the MOS transistor, generating a second voltage signal, comparing the first voltage signal to the second voltage signal, and adjusting the effective threshold voltage of the MOS transistor so that the second voltage signal is substantially equal to the first voltage signal.

Decoupling capacitors for thin gate oxides

Abstract: In some embodiments, the invention involves a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage. A semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage. Various configurations may be used including: n+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and n+ source/drain regions in a p-body. The power supply voltage may have a larger absolute value than does a flatband voltage.

Semiconductor on silicon (SOI) transistor with a halo implant

Abstract: A semiconductor over insulator transistor (100) includes a semiconductor mesa (36) formed over an insulating layer (34) which overlies a semiconductor substrate (32). Source and drain regions (66, 68) of a first conductivity type are formed at opposite ends of the mesa. A body node (56) of a second conductivity type is located between the source and drain regions in the mesa. A gate insulator (40) and a gate electrode (46) lie over the body node. Halo implants (54, 56) are placed to completely separate the source and drain regions from the body node, or channel regions, for improving short channel effect. The transistor is useful as a pass gate and as a peripheral transistor in a DRAM, and also is useful in digital and analog applications and in low power applications.