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Drain-induced barrier lowering

About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.


Papers
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Journal ArticleDOI
TL;DR: In this article, the effect of radiation enhanced drain induced barrier lowering (DIBL) was experimentally observed and verified by 3D simulations for submicron MOSFETs with trench isolation oxides.
Abstract: Radiation enhanced drain induced barrier lowering (DIBL) was experimentally observed and verified by 3D simulations for submicron devices with trench isolation oxides. Submicron MOSFETs with shallow trench isolation were exposed to total-ionizing-dose radiation. Prior to irradiation, the devices exhibited near-ideal current-voltage characteristics, with no significant short-channel effects for as-drawn gate lengths of 0.4 /spl mu/m. Following irradiation, the off-state leakage current increased significantly for total doses above about 650 krad(SiO/sub 2/). In addition, the irradiated devices exhibited DIBL that increased the drain current by 5-10/spl times/ for a gate length of 0.4 /spl mu/m (the nominal minimum gate length for this process) and much more for slightly shorter devices (0.35 /spl mu/m). The increase in the off-state leakage current and the accompanying DIBL are shown to be associated with a parasitic field-effect transistor that is present at the edge of the shallow trench. Three-dimensional simulations are used to illustrate the effect. Simulations show that trapped charge at the trench sidewalls enhances the DIBL by depleting the edges of the channel. Radiation-induced charge may decrease the effectiveness of short-channel engineering.

42 citations

Journal ArticleDOI
TL;DR: In this paper, a self-forming nanostructure has been modified by reactive-ion etching in plasma to form a periodic nanomask on the surface of the channel region of a metaloxide-semiconductor field effect transistor (MOSFET).
Abstract: A self-forming nanostructure—a wave-ordered structure with a controllable period (20–180 nm)—results from the off-normal bombardment of amorphous silicon layers by low-energy (~ 1–10 keV) nitrogen ions. The nanostructure has been modified by reactive-ion etching in plasma to form a periodic nanomask on the surface of the channel region of a metal–oxide–semiconductor field-effect transistor (MOSFET). Implantation of arsenic ions through the nanomask followed by the technological steps completing the fabrication of the MOSFET resulted in a periodically doped channel field-effect transistor (PDCFET), which can be considered as a chain of short-channel MOSFETs with a common gate. Having worse subthreshold characteristics, PDCFETs show greater drain current and transconductance than to MOSFETs without a periodically doped channel. This improvement in device performance is attributed to the fact that the channel length is cut by the length of high-conductivity doped areas in the channel and that the voltage is distributed between the areas, depressing the scaling rules for short-channel MOSFETs and allowing the channel to be less doped between the areas, thus keeping drift mobility high.

42 citations

Patent
12 Oct 1990
TL;DR: In this article, a clamping region having a spherical shape is provided in the gater region of an enclosed transistor cell, which has a lower breakdown voltage than do the active portions of the transistor cell.
Abstract: A power transistor takes advantage of the lower breakdown voltage capability of a spherical junction. A clamping region having a spherical shape is provided in the gater region of an enclosed transistor cell. The clamping region has a lower breakdown voltage than do the active portions of the transistor cell. Both a DMOSFET and an IGBT transistor may be provided with the clamping region. The clamping region is a zener diode in the case of the DMOSFET, and is a bipolar junction transistor in the case of the insulated gate bipolar transistor. The clamping region is preferably an island in the center of each cell of a closed cell structure.

42 citations

Patent
30 Dec 2004
TL;DR: In this article, the transistor structure is integrated into a memory cell array of a DRAM having hole trench capacitors or stacked capacitors by a suitable integration concept, and a selection transistor is used in order to improve the switching behavior of the memory cell.
Abstract: A transistor structure having source/drain regions arranged in a horizontal plane along an x axis has a recess structure, which separates the two source/drain regions from one another and increases the effective channel length L eff of the transistor structure. A vertical gate electrode with respect to the horizontal plane extends along the x axis and in this case encloses an active zone of the transistor structure from two sides or completely. The effective channel width W eff is dependent on the depth to which the gate electrode is formed. A memory cell having a selection transistor in accordance with the transistor structure has both a low leakage current and a good switching behavior. By a suitable integration concept, the transistor structure is integrated into a memory cell array of a DRAM having hole trench capacitors or stacked capacitors.

42 citations

Journal ArticleDOI
TL;DR: In this paper, the authors developed a compact analytical model for the drain current of a silicon-on-insulator tunneling field effect transistor, which includes the effects of oxide thickness, body doping, drain voltage, and gate metal work function.
Abstract: In this paper, we have developed a compact analytical model for the drain current of a silicon-on-insulator tunneling field-effect transistor. The model includes the effects of oxide thickness, body doping, drain voltage, and gate metal work function. The model calculates the drain current using a tangent line approximation method to integrate the tunneling generation rate in the source–body depletion region. The accuracy of the model is tested against 2-D numerical simulations. The model predicts the drain current accurately in both the ON state (strong inversion) as well as in the subthreshold region.

42 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202330
202279
202161
202055
201958
201845