Topic
Drain-induced barrier lowering
About: Drain-induced barrier lowering is a research topic. Over the lifetime, 6163 publications have been published within this topic receiving 101547 citations.
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NEC1
TL;DR: An overcurrent sensing circuit for sensing an overcurrent flowing through a power MOS transistor is described in this article, where a voltage drop equal to the voltage across the drain and source of a power mOS transistor that changes due to change in a load current is generated in a sensing resistor that is connected between the source of the sensing MOS transistors having its gate and drain connected in common with those of the power transistors.
Abstract: An overcurrent sensing circuit for sensing an overcurrent flowing through a power MOS transistor is described. A voltage drop equal to the voltage across the drain and source of a power MOS transistor that changes due to change in a load current is generated in a sensing resistor that is connected between the source of a sensing MOS transistor having its gate and drain connected in common with those of the power MOS transistor and the source of the power MOS transistor due to current that flows through the sensing MOS transistor. This voltage is inputted to a comparator that has an added offset voltage, and the comparator judges that the power MOS transistor is in an overcurrent condition when this inputted voltage exceeds an input offset voltage value that is set inside the comparator.
41 citations
Patent•
10 Sep 1997TL;DR: In this article, a method for soft programming memory cells and floating gate memory devices is described. But the method requires a constant current source to the drain, and the well voltage must be at least 4 V lower than the gate voltage.
Abstract: A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.
41 citations
Patent•
14 Apr 2010TL;DR: In this article, a shift register circuit comprises a plurality of stages, each stage being for providing an output signal to an output load and comprising a pull up transistor for pulling the output signal up to a high voltage rail and a pull down transistor for pulling output signal down to a low voltage rail.
Abstract: A shift register circuit comprises a plurality of stages, each stage being for providing an output signal to an output load and comprising a pull up transistor for pulling the output signal up to a high voltage rail and a pull down transistor for pulling the output signal down to a low voltage rail. Each stage comprises a circuit for sampling the threshold voltage of at least one of the pull up and pull down transistors and for adding the sampled threshold voltage to a control voltage offset, to provide a threshold-voltage-compensated signal for controlling the gate of the at least one of the pull up and pull down transistors. This provides threshold voltage sampling, in particular for the thin film transistor whose threshold voltage drift must be compensated (for example the pull-down thin film transistor).
41 citations
TL;DR: In this article, the threshold voltage of an organic field effect transistor (OFET) was adjusted using a design similar to a dual-gate structure with an insulating Teflon-based electret layer as a second gate.
Abstract: Here, the authors present a technique to adjust the threshold voltage of an organic field-effect transistor (OFET) using a design similar to a dual-gate structure with an insulating Teflon-based electret layer as a second gate The threshold voltage of a pentacene bottom gate OFET was shifted from +131to−23V by depositon of a 17μm thick electret layer, proving the principal feasibility of this approach This controlled tuning of the threshold voltage compensates one of the main drawbacks of organic electronics and even allows switching from a depletion to an enhancement-type transistor behavior
41 citations
Patent•
21 Apr 1997TL;DR: In this article, a method of establishing a differential threshold voltage during the fabrication of first and second IGFETs having like conductivity type is disclosed, where a dopant is introduced into the gate electrode of each transistor of the pair.
Abstract: A method of establishing a differential threshold voltage during the fabrication of first and second IGFETs having like conductivity type is disclosed. A dopant is introduced into the gate electrode of each transistor of the pair. The dopant is differentially diffused into respective channel regions to provide a differential dopant concentration therebetween, which results in a differential threshold voltage between the two transistors. One embodiment includes introducing a diffusion-retarding material, such as nitrogen, into the first gate electrode before the dopant is diffused into the respective channel regions, and without introducing a significant amount of the diffusion-retarding material into the second gate electrode. Advantageously, a single dopant implant can provide both threshold voltage values. The two threshold voltages may be chosen to provide various combinations of enhancement mode and depletion mode IGFETs.
41 citations